2 * PIC32 watchdog driver
4 * Joshua Henderson <joshua.henderson@microchip.com>
5 * Copyright (c) 2016, Microchip Technology Inc.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
12 #include <linux/clk.h>
13 #include <linux/device.h>
14 #include <linux/err.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/platform_device.h>
22 #include <linux/watchdog.h>
24 #include <asm/mach-pic32/pic32.h>
26 /* Watchdog Timer Registers */
27 #define WDTCON_REG 0x00
29 /* Watchdog Timer Control Register fields */
30 #define WDTCON_WIN_EN BIT(0)
31 #define WDTCON_RMCS_MASK 0x0003
32 #define WDTCON_RMCS_SHIFT 0x0006
33 #define WDTCON_RMPS_MASK 0x001F
34 #define WDTCON_RMPS_SHIFT 0x0008
35 #define WDTCON_ON BIT(15)
36 #define WDTCON_CLR_KEY 0x5743
38 /* Reset Control Register fields for watchdog */
39 #define RESETCON_TIMEOUT_IDLE BIT(2)
40 #define RESETCON_TIMEOUT_SLEEP BIT(3)
41 #define RESETCON_WDT_TIMEOUT BIT(4)
45 void __iomem
*rst_base
;
49 static inline bool pic32_wdt_is_win_enabled(struct pic32_wdt
*wdt
)
51 return !!(readl(wdt
->regs
+ WDTCON_REG
) & WDTCON_WIN_EN
);
54 static inline u32
pic32_wdt_get_post_scaler(struct pic32_wdt
*wdt
)
56 u32 v
= readl(wdt
->regs
+ WDTCON_REG
);
58 return (v
>> WDTCON_RMPS_SHIFT
) & WDTCON_RMPS_MASK
;
61 static inline u32
pic32_wdt_get_clk_id(struct pic32_wdt
*wdt
)
63 u32 v
= readl(wdt
->regs
+ WDTCON_REG
);
65 return (v
>> WDTCON_RMCS_SHIFT
) & WDTCON_RMCS_MASK
;
68 static int pic32_wdt_bootstatus(struct pic32_wdt
*wdt
)
70 u32 v
= readl(wdt
->rst_base
);
72 writel(RESETCON_WDT_TIMEOUT
, PIC32_CLR(wdt
->rst_base
));
74 return v
& RESETCON_WDT_TIMEOUT
;
77 static u32
pic32_wdt_get_timeout_secs(struct pic32_wdt
*wdt
, struct device
*dev
)
80 u32 period
, ps
, terminal
;
82 rate
= clk_get_rate(wdt
->clk
);
84 dev_dbg(dev
, "wdt: clk_id %d, clk_rate %lu (prescale)\n",
85 pic32_wdt_get_clk_id(wdt
), rate
);
87 /* default, prescaler of 32 (i.e. div-by-32) is implicit. */
92 /* calculate terminal count from postscaler. */
93 ps
= pic32_wdt_get_post_scaler(wdt
);
96 /* find time taken (in secs) to reach terminal count */
97 period
= terminal
/ rate
;
99 "wdt: clk_rate %lu (postscale) / terminal %d, timeout %dsec\n",
100 rate
, terminal
, period
);
105 static void pic32_wdt_keepalive(struct pic32_wdt
*wdt
)
107 /* write key through single half-word */
108 writew(WDTCON_CLR_KEY
, wdt
->regs
+ WDTCON_REG
+ 2);
111 static int pic32_wdt_start(struct watchdog_device
*wdd
)
113 struct pic32_wdt
*wdt
= watchdog_get_drvdata(wdd
);
115 writel(WDTCON_ON
, PIC32_SET(wdt
->regs
+ WDTCON_REG
));
116 pic32_wdt_keepalive(wdt
);
121 static int pic32_wdt_stop(struct watchdog_device
*wdd
)
123 struct pic32_wdt
*wdt
= watchdog_get_drvdata(wdd
);
125 writel(WDTCON_ON
, PIC32_CLR(wdt
->regs
+ WDTCON_REG
));
128 * Cannot touch registers in the CPU cycle following clearing the
136 static int pic32_wdt_ping(struct watchdog_device
*wdd
)
138 struct pic32_wdt
*wdt
= watchdog_get_drvdata(wdd
);
140 pic32_wdt_keepalive(wdt
);
145 static const struct watchdog_ops pic32_wdt_fops
= {
146 .owner
= THIS_MODULE
,
147 .start
= pic32_wdt_start
,
148 .stop
= pic32_wdt_stop
,
149 .ping
= pic32_wdt_ping
,
152 static const struct watchdog_info pic32_wdt_ident
= {
153 .options
= WDIOF_KEEPALIVEPING
|
154 WDIOF_MAGICCLOSE
| WDIOF_CARDRESET
,
155 .identity
= "PIC32 Watchdog",
158 static struct watchdog_device pic32_wdd
= {
159 .info
= &pic32_wdt_ident
,
160 .ops
= &pic32_wdt_fops
,
163 static const struct of_device_id pic32_wdt_dt_ids
[] = {
164 { .compatible
= "microchip,pic32mzda-wdt", },
167 MODULE_DEVICE_TABLE(of
, pic32_wdt_dt_ids
);
169 static int pic32_wdt_drv_probe(struct platform_device
*pdev
)
172 struct watchdog_device
*wdd
= &pic32_wdd
;
173 struct pic32_wdt
*wdt
;
175 wdt
= devm_kzalloc(&pdev
->dev
, sizeof(*wdt
), GFP_KERNEL
);
179 wdt
->regs
= devm_platform_ioremap_resource(pdev
, 0);
180 if (IS_ERR(wdt
->regs
))
181 return PTR_ERR(wdt
->regs
);
183 wdt
->rst_base
= devm_ioremap(&pdev
->dev
, PIC32_BASE_RESET
, 0x10);
187 wdt
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
188 if (IS_ERR(wdt
->clk
)) {
189 dev_err(&pdev
->dev
, "clk not found\n");
190 return PTR_ERR(wdt
->clk
);
193 ret
= clk_prepare_enable(wdt
->clk
);
195 dev_err(&pdev
->dev
, "clk enable failed\n");
199 if (pic32_wdt_is_win_enabled(wdt
)) {
200 dev_err(&pdev
->dev
, "windowed-clear mode is not supported.\n");
202 goto out_disable_clk
;
205 wdd
->timeout
= pic32_wdt_get_timeout_secs(wdt
, &pdev
->dev
);
208 "failed to read watchdog register timeout\n");
210 goto out_disable_clk
;
213 dev_info(&pdev
->dev
, "timeout %d\n", wdd
->timeout
);
215 wdd
->bootstatus
= pic32_wdt_bootstatus(wdt
) ? WDIOF_CARDRESET
: 0;
217 watchdog_set_nowayout(wdd
, WATCHDOG_NOWAYOUT
);
218 watchdog_set_drvdata(wdd
, wdt
);
220 ret
= watchdog_register_device(wdd
);
222 dev_err(&pdev
->dev
, "watchdog register failed, err %d\n", ret
);
223 goto out_disable_clk
;
226 platform_set_drvdata(pdev
, wdd
);
231 clk_disable_unprepare(wdt
->clk
);
236 static int pic32_wdt_drv_remove(struct platform_device
*pdev
)
238 struct watchdog_device
*wdd
= platform_get_drvdata(pdev
);
239 struct pic32_wdt
*wdt
= watchdog_get_drvdata(wdd
);
241 watchdog_unregister_device(wdd
);
242 clk_disable_unprepare(wdt
->clk
);
247 static struct platform_driver pic32_wdt_driver
= {
248 .probe
= pic32_wdt_drv_probe
,
249 .remove
= pic32_wdt_drv_remove
,
252 .of_match_table
= of_match_ptr(pic32_wdt_dt_ids
),
256 module_platform_driver(pic32_wdt_driver
);
258 MODULE_AUTHOR("Joshua Henderson <joshua.henderson@microchip.com>");
259 MODULE_DESCRIPTION("Microchip PIC32 Watchdog Timer");
260 MODULE_LICENSE("GPL");