2 * Copyright (c) 2004 Simtec Electronics
3 * Ben Dooks <ben@simtec.co.uk>
5 * S3C2410 Watchdog Timer Support
7 * Based on, softdog.c by Alan Cox,
8 * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/types.h>
24 #include <linux/timer.h>
25 #include <linux/watchdog.h>
26 #include <linux/platform_device.h>
27 #include <linux/interrupt.h>
28 #include <linux/clk.h>
29 #include <linux/uaccess.h>
31 #include <linux/cpufreq.h>
32 #include <linux/slab.h>
33 #include <linux/err.h>
35 #include <linux/of_device.h>
36 #include <linux/mfd/syscon.h>
37 #include <linux/regmap.h>
38 #include <linux/delay.h>
40 #define S3C2410_WTCON 0x00
41 #define S3C2410_WTDAT 0x04
42 #define S3C2410_WTCNT 0x08
43 #define S3C2410_WTCLRINT 0x0c
45 #define S3C2410_WTCNT_MAXCNT 0xffff
47 #define S3C2410_WTCON_RSTEN (1 << 0)
48 #define S3C2410_WTCON_INTEN (1 << 2)
49 #define S3C2410_WTCON_ENABLE (1 << 5)
51 #define S3C2410_WTCON_DIV16 (0 << 3)
52 #define S3C2410_WTCON_DIV32 (1 << 3)
53 #define S3C2410_WTCON_DIV64 (2 << 3)
54 #define S3C2410_WTCON_DIV128 (3 << 3)
56 #define S3C2410_WTCON_MAXDIV 0x80
58 #define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
59 #define S3C2410_WTCON_PRESCALE_MASK (0xff << 8)
60 #define S3C2410_WTCON_PRESCALE_MAX 0xff
62 #define S3C2410_WATCHDOG_ATBOOT (0)
63 #define S3C2410_WATCHDOG_DEFAULT_TIME (15)
65 #define EXYNOS5_RST_STAT_REG_OFFSET 0x0404
66 #define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408
67 #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c
68 #define QUIRK_HAS_PMU_CONFIG (1 << 0)
69 #define QUIRK_HAS_RST_STAT (1 << 1)
70 #define QUIRK_HAS_WTCLRINT_REG (1 << 2)
72 /* These quirks require that we have a PMU register map */
73 #define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \
76 static bool nowayout
= WATCHDOG_NOWAYOUT
;
77 static int tmr_margin
;
78 static int tmr_atboot
= S3C2410_WATCHDOG_ATBOOT
;
79 static int soft_noboot
;
81 module_param(tmr_margin
, int, 0);
82 module_param(tmr_atboot
, int, 0);
83 module_param(nowayout
, bool, 0);
84 module_param(soft_noboot
, int, 0);
86 MODULE_PARM_DESC(tmr_margin
, "Watchdog tmr_margin in seconds. (default="
87 __MODULE_STRING(S3C2410_WATCHDOG_DEFAULT_TIME
) ")");
88 MODULE_PARM_DESC(tmr_atboot
,
89 "Watchdog is started at boot time if set to 1, default="
90 __MODULE_STRING(S3C2410_WATCHDOG_ATBOOT
));
91 MODULE_PARM_DESC(nowayout
, "Watchdog cannot be stopped once started (default="
92 __MODULE_STRING(WATCHDOG_NOWAYOUT
) ")");
93 MODULE_PARM_DESC(soft_noboot
, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default 0)");
96 * struct s3c2410_wdt_variant - Per-variant config data
98 * @disable_reg: Offset in pmureg for the register that disables the watchdog
99 * timer reset functionality.
100 * @mask_reset_reg: Offset in pmureg for the register that masks the watchdog
101 * timer reset functionality.
102 * @mask_bit: Bit number for the watchdog timer in the disable register and the
103 * mask reset register.
104 * @rst_stat_reg: Offset in pmureg for the register that has the reset status.
105 * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog
107 * @quirks: A bitfield of quirks.
110 struct s3c2410_wdt_variant
{
122 void __iomem
*reg_base
;
125 unsigned long wtcon_save
;
126 unsigned long wtdat_save
;
127 struct watchdog_device wdt_device
;
128 struct notifier_block freq_transition
;
129 const struct s3c2410_wdt_variant
*drv_data
;
130 struct regmap
*pmureg
;
133 static const struct s3c2410_wdt_variant drv_data_s3c2410
= {
138 static const struct s3c2410_wdt_variant drv_data_s3c6410
= {
139 .quirks
= QUIRK_HAS_WTCLRINT_REG
,
142 static const struct s3c2410_wdt_variant drv_data_exynos5250
= {
143 .disable_reg
= EXYNOS5_WDT_DISABLE_REG_OFFSET
,
144 .mask_reset_reg
= EXYNOS5_WDT_MASK_RESET_REG_OFFSET
,
146 .rst_stat_reg
= EXYNOS5_RST_STAT_REG_OFFSET
,
148 .quirks
= QUIRK_HAS_PMU_CONFIG
| QUIRK_HAS_RST_STAT \
149 | QUIRK_HAS_WTCLRINT_REG
,
152 static const struct s3c2410_wdt_variant drv_data_exynos5420
= {
153 .disable_reg
= EXYNOS5_WDT_DISABLE_REG_OFFSET
,
154 .mask_reset_reg
= EXYNOS5_WDT_MASK_RESET_REG_OFFSET
,
156 .rst_stat_reg
= EXYNOS5_RST_STAT_REG_OFFSET
,
158 .quirks
= QUIRK_HAS_PMU_CONFIG
| QUIRK_HAS_RST_STAT \
159 | QUIRK_HAS_WTCLRINT_REG
,
162 static const struct s3c2410_wdt_variant drv_data_exynos7
= {
163 .disable_reg
= EXYNOS5_WDT_DISABLE_REG_OFFSET
,
164 .mask_reset_reg
= EXYNOS5_WDT_MASK_RESET_REG_OFFSET
,
166 .rst_stat_reg
= EXYNOS5_RST_STAT_REG_OFFSET
,
167 .rst_stat_bit
= 23, /* A57 WDTRESET */
168 .quirks
= QUIRK_HAS_PMU_CONFIG
| QUIRK_HAS_RST_STAT \
169 | QUIRK_HAS_WTCLRINT_REG
,
172 static const struct of_device_id s3c2410_wdt_match
[] = {
173 { .compatible
= "samsung,s3c2410-wdt",
174 .data
= &drv_data_s3c2410
},
175 { .compatible
= "samsung,s3c6410-wdt",
176 .data
= &drv_data_s3c6410
},
177 { .compatible
= "samsung,exynos5250-wdt",
178 .data
= &drv_data_exynos5250
},
179 { .compatible
= "samsung,exynos5420-wdt",
180 .data
= &drv_data_exynos5420
},
181 { .compatible
= "samsung,exynos7-wdt",
182 .data
= &drv_data_exynos7
},
185 MODULE_DEVICE_TABLE(of
, s3c2410_wdt_match
);
188 static const struct platform_device_id s3c2410_wdt_ids
[] = {
190 .name
= "s3c2410-wdt",
191 .driver_data
= (unsigned long)&drv_data_s3c2410
,
195 MODULE_DEVICE_TABLE(platform
, s3c2410_wdt_ids
);
199 static inline unsigned int s3c2410wdt_max_timeout(struct clk
*clock
)
201 unsigned long freq
= clk_get_rate(clock
);
203 return S3C2410_WTCNT_MAXCNT
/ (freq
/ (S3C2410_WTCON_PRESCALE_MAX
+ 1)
204 / S3C2410_WTCON_MAXDIV
);
207 static inline struct s3c2410_wdt
*freq_to_wdt(struct notifier_block
*nb
)
209 return container_of(nb
, struct s3c2410_wdt
, freq_transition
);
212 static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt
*wdt
, bool mask
)
215 u32 mask_val
= 1 << wdt
->drv_data
->mask_bit
;
218 /* No need to do anything if no PMU CONFIG needed */
219 if (!(wdt
->drv_data
->quirks
& QUIRK_HAS_PMU_CONFIG
))
225 ret
= regmap_update_bits(wdt
->pmureg
,
226 wdt
->drv_data
->disable_reg
,
231 ret
= regmap_update_bits(wdt
->pmureg
,
232 wdt
->drv_data
->mask_reset_reg
,
236 dev_err(wdt
->dev
, "failed to update reg(%d)\n", ret
);
241 static int s3c2410wdt_keepalive(struct watchdog_device
*wdd
)
243 struct s3c2410_wdt
*wdt
= watchdog_get_drvdata(wdd
);
245 spin_lock(&wdt
->lock
);
246 writel(wdt
->count
, wdt
->reg_base
+ S3C2410_WTCNT
);
247 spin_unlock(&wdt
->lock
);
252 static void __s3c2410wdt_stop(struct s3c2410_wdt
*wdt
)
256 wtcon
= readl(wdt
->reg_base
+ S3C2410_WTCON
);
257 wtcon
&= ~(S3C2410_WTCON_ENABLE
| S3C2410_WTCON_RSTEN
);
258 writel(wtcon
, wdt
->reg_base
+ S3C2410_WTCON
);
261 static int s3c2410wdt_stop(struct watchdog_device
*wdd
)
263 struct s3c2410_wdt
*wdt
= watchdog_get_drvdata(wdd
);
265 spin_lock(&wdt
->lock
);
266 __s3c2410wdt_stop(wdt
);
267 spin_unlock(&wdt
->lock
);
272 static int s3c2410wdt_start(struct watchdog_device
*wdd
)
275 struct s3c2410_wdt
*wdt
= watchdog_get_drvdata(wdd
);
277 spin_lock(&wdt
->lock
);
279 __s3c2410wdt_stop(wdt
);
281 wtcon
= readl(wdt
->reg_base
+ S3C2410_WTCON
);
282 wtcon
|= S3C2410_WTCON_ENABLE
| S3C2410_WTCON_DIV128
;
285 wtcon
|= S3C2410_WTCON_INTEN
;
286 wtcon
&= ~S3C2410_WTCON_RSTEN
;
288 wtcon
&= ~S3C2410_WTCON_INTEN
;
289 wtcon
|= S3C2410_WTCON_RSTEN
;
292 dev_dbg(wdt
->dev
, "Starting watchdog: count=0x%08x, wtcon=%08lx\n",
295 writel(wdt
->count
, wdt
->reg_base
+ S3C2410_WTDAT
);
296 writel(wdt
->count
, wdt
->reg_base
+ S3C2410_WTCNT
);
297 writel(wtcon
, wdt
->reg_base
+ S3C2410_WTCON
);
298 spin_unlock(&wdt
->lock
);
303 static inline int s3c2410wdt_is_running(struct s3c2410_wdt
*wdt
)
305 return readl(wdt
->reg_base
+ S3C2410_WTCON
) & S3C2410_WTCON_ENABLE
;
308 static int s3c2410wdt_set_heartbeat(struct watchdog_device
*wdd
,
309 unsigned int timeout
)
311 struct s3c2410_wdt
*wdt
= watchdog_get_drvdata(wdd
);
312 unsigned long freq
= clk_get_rate(wdt
->clock
);
314 unsigned int divisor
= 1;
320 freq
= DIV_ROUND_UP(freq
, 128);
321 count
= timeout
* freq
;
323 dev_dbg(wdt
->dev
, "Heartbeat: count=%d, timeout=%d, freq=%lu\n",
324 count
, timeout
, freq
);
326 /* if the count is bigger than the watchdog register,
327 then work out what we need to do (and if) we can
328 actually make this value
331 if (count
>= 0x10000) {
332 divisor
= DIV_ROUND_UP(count
, 0xffff);
334 if (divisor
> 0x100) {
335 dev_err(wdt
->dev
, "timeout %d too big\n", timeout
);
340 dev_dbg(wdt
->dev
, "Heartbeat: timeout=%d, divisor=%d, count=%d (%08x)\n",
341 timeout
, divisor
, count
, DIV_ROUND_UP(count
, divisor
));
343 count
= DIV_ROUND_UP(count
, divisor
);
346 /* update the pre-scaler */
347 wtcon
= readl(wdt
->reg_base
+ S3C2410_WTCON
);
348 wtcon
&= ~S3C2410_WTCON_PRESCALE_MASK
;
349 wtcon
|= S3C2410_WTCON_PRESCALE(divisor
-1);
351 writel(count
, wdt
->reg_base
+ S3C2410_WTDAT
);
352 writel(wtcon
, wdt
->reg_base
+ S3C2410_WTCON
);
354 wdd
->timeout
= (count
* divisor
) / freq
;
359 static int s3c2410wdt_restart(struct watchdog_device
*wdd
, unsigned long action
,
362 struct s3c2410_wdt
*wdt
= watchdog_get_drvdata(wdd
);
363 void __iomem
*wdt_base
= wdt
->reg_base
;
365 /* disable watchdog, to be safe */
366 writel(0, wdt_base
+ S3C2410_WTCON
);
368 /* put initial values into count and data */
369 writel(0x80, wdt_base
+ S3C2410_WTCNT
);
370 writel(0x80, wdt_base
+ S3C2410_WTDAT
);
372 /* set the watchdog to go and reset... */
373 writel(S3C2410_WTCON_ENABLE
| S3C2410_WTCON_DIV16
|
374 S3C2410_WTCON_RSTEN
| S3C2410_WTCON_PRESCALE(0x20),
375 wdt_base
+ S3C2410_WTCON
);
377 /* wait for reset to assert... */
383 #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
385 static const struct watchdog_info s3c2410_wdt_ident
= {
387 .firmware_version
= 0,
388 .identity
= "S3C2410 Watchdog",
391 static const struct watchdog_ops s3c2410wdt_ops
= {
392 .owner
= THIS_MODULE
,
393 .start
= s3c2410wdt_start
,
394 .stop
= s3c2410wdt_stop
,
395 .ping
= s3c2410wdt_keepalive
,
396 .set_timeout
= s3c2410wdt_set_heartbeat
,
397 .restart
= s3c2410wdt_restart
,
400 static const struct watchdog_device s3c2410_wdd
= {
401 .info
= &s3c2410_wdt_ident
,
402 .ops
= &s3c2410wdt_ops
,
403 .timeout
= S3C2410_WATCHDOG_DEFAULT_TIME
,
406 /* interrupt handler code */
408 static irqreturn_t
s3c2410wdt_irq(int irqno
, void *param
)
410 struct s3c2410_wdt
*wdt
= platform_get_drvdata(param
);
412 dev_info(wdt
->dev
, "watchdog timer expired (irq)\n");
414 s3c2410wdt_keepalive(&wdt
->wdt_device
);
416 if (wdt
->drv_data
->quirks
& QUIRK_HAS_WTCLRINT_REG
)
417 writel(0x1, wdt
->reg_base
+ S3C2410_WTCLRINT
);
422 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
424 static int s3c2410wdt_cpufreq_transition(struct notifier_block
*nb
,
425 unsigned long val
, void *data
)
428 struct s3c2410_wdt
*wdt
= freq_to_wdt(nb
);
430 if (!s3c2410wdt_is_running(wdt
))
433 if (val
== CPUFREQ_PRECHANGE
) {
434 /* To ensure that over the change we don't cause the
435 * watchdog to trigger, we perform an keep-alive if
436 * the watchdog is running.
439 s3c2410wdt_keepalive(&wdt
->wdt_device
);
440 } else if (val
== CPUFREQ_POSTCHANGE
) {
441 s3c2410wdt_stop(&wdt
->wdt_device
);
443 ret
= s3c2410wdt_set_heartbeat(&wdt
->wdt_device
,
444 wdt
->wdt_device
.timeout
);
447 s3c2410wdt_start(&wdt
->wdt_device
);
456 dev_err(wdt
->dev
, "cannot set new value for timeout %d\n",
457 wdt
->wdt_device
.timeout
);
461 static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt
*wdt
)
463 wdt
->freq_transition
.notifier_call
= s3c2410wdt_cpufreq_transition
;
465 return cpufreq_register_notifier(&wdt
->freq_transition
,
466 CPUFREQ_TRANSITION_NOTIFIER
);
469 static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt
*wdt
)
471 wdt
->freq_transition
.notifier_call
= s3c2410wdt_cpufreq_transition
;
473 cpufreq_unregister_notifier(&wdt
->freq_transition
,
474 CPUFREQ_TRANSITION_NOTIFIER
);
479 static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt
*wdt
)
484 static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt
*wdt
)
489 static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt
*wdt
)
491 unsigned int rst_stat
;
494 if (!(wdt
->drv_data
->quirks
& QUIRK_HAS_RST_STAT
))
497 ret
= regmap_read(wdt
->pmureg
, wdt
->drv_data
->rst_stat_reg
, &rst_stat
);
499 dev_warn(wdt
->dev
, "Couldn't get RST_STAT register\n");
500 else if (rst_stat
& BIT(wdt
->drv_data
->rst_stat_bit
))
501 return WDIOF_CARDRESET
;
506 static inline const struct s3c2410_wdt_variant
*
507 s3c2410_get_wdt_drv_data(struct platform_device
*pdev
)
509 const struct s3c2410_wdt_variant
*variant
;
511 variant
= of_device_get_match_data(&pdev
->dev
);
513 /* Device matched by platform_device_id */
514 variant
= (struct s3c2410_wdt_variant
*)
515 platform_get_device_id(pdev
)->driver_data
;
521 static int s3c2410wdt_probe(struct platform_device
*pdev
)
523 struct device
*dev
= &pdev
->dev
;
524 struct s3c2410_wdt
*wdt
;
525 struct resource
*wdt_irq
;
530 wdt
= devm_kzalloc(dev
, sizeof(*wdt
), GFP_KERNEL
);
535 spin_lock_init(&wdt
->lock
);
536 wdt
->wdt_device
= s3c2410_wdd
;
538 wdt
->drv_data
= s3c2410_get_wdt_drv_data(pdev
);
539 if (wdt
->drv_data
->quirks
& QUIRKS_HAVE_PMUREG
) {
540 wdt
->pmureg
= syscon_regmap_lookup_by_phandle(dev
->of_node
,
541 "samsung,syscon-phandle");
542 if (IS_ERR(wdt
->pmureg
)) {
543 dev_err(dev
, "syscon regmap lookup failed.\n");
544 return PTR_ERR(wdt
->pmureg
);
548 wdt_irq
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
549 if (wdt_irq
== NULL
) {
550 dev_err(dev
, "no irq resource specified\n");
555 /* get the memory region for the watchdog timer */
556 wdt
->reg_base
= devm_platform_ioremap_resource(pdev
, 0);
557 if (IS_ERR(wdt
->reg_base
)) {
558 ret
= PTR_ERR(wdt
->reg_base
);
562 wdt
->clock
= devm_clk_get(dev
, "watchdog");
563 if (IS_ERR(wdt
->clock
)) {
564 dev_err(dev
, "failed to find watchdog clock source\n");
565 ret
= PTR_ERR(wdt
->clock
);
569 ret
= clk_prepare_enable(wdt
->clock
);
571 dev_err(dev
, "failed to enable clock\n");
575 wdt
->wdt_device
.min_timeout
= 1;
576 wdt
->wdt_device
.max_timeout
= s3c2410wdt_max_timeout(wdt
->clock
);
578 ret
= s3c2410wdt_cpufreq_register(wdt
);
580 dev_err(dev
, "failed to register cpufreq\n");
584 watchdog_set_drvdata(&wdt
->wdt_device
, wdt
);
586 /* see if we can actually set the requested timer margin, and if
587 * not, try the default value */
589 watchdog_init_timeout(&wdt
->wdt_device
, tmr_margin
, dev
);
590 ret
= s3c2410wdt_set_heartbeat(&wdt
->wdt_device
,
591 wdt
->wdt_device
.timeout
);
593 started
= s3c2410wdt_set_heartbeat(&wdt
->wdt_device
,
594 S3C2410_WATCHDOG_DEFAULT_TIME
);
598 "tmr_margin value out of range, default %d used\n",
599 S3C2410_WATCHDOG_DEFAULT_TIME
);
601 dev_info(dev
, "default timer value is out of range, cannot start\n");
604 ret
= devm_request_irq(dev
, wdt_irq
->start
, s3c2410wdt_irq
, 0,
607 dev_err(dev
, "failed to install irq (%d)\n", ret
);
611 watchdog_set_nowayout(&wdt
->wdt_device
, nowayout
);
612 watchdog_set_restart_priority(&wdt
->wdt_device
, 128);
614 wdt
->wdt_device
.bootstatus
= s3c2410wdt_get_bootstatus(wdt
);
615 wdt
->wdt_device
.parent
= dev
;
617 ret
= watchdog_register_device(&wdt
->wdt_device
);
619 dev_err(dev
, "cannot register watchdog (%d)\n", ret
);
623 ret
= s3c2410wdt_mask_and_disable_reset(wdt
, false);
627 if (tmr_atboot
&& started
== 0) {
628 dev_info(dev
, "starting watchdog timer\n");
629 s3c2410wdt_start(&wdt
->wdt_device
);
630 } else if (!tmr_atboot
) {
631 /* if we're not enabling the watchdog, then ensure it is
632 * disabled if it has been left running from the bootloader
635 s3c2410wdt_stop(&wdt
->wdt_device
);
638 platform_set_drvdata(pdev
, wdt
);
640 /* print out a statement of readiness */
642 wtcon
= readl(wdt
->reg_base
+ S3C2410_WTCON
);
644 dev_info(dev
, "watchdog %sactive, reset %sabled, irq %sabled\n",
645 (wtcon
& S3C2410_WTCON_ENABLE
) ? "" : "in",
646 (wtcon
& S3C2410_WTCON_RSTEN
) ? "en" : "dis",
647 (wtcon
& S3C2410_WTCON_INTEN
) ? "en" : "dis");
652 watchdog_unregister_device(&wdt
->wdt_device
);
655 s3c2410wdt_cpufreq_deregister(wdt
);
658 clk_disable_unprepare(wdt
->clock
);
664 static int s3c2410wdt_remove(struct platform_device
*dev
)
667 struct s3c2410_wdt
*wdt
= platform_get_drvdata(dev
);
669 ret
= s3c2410wdt_mask_and_disable_reset(wdt
, true);
673 watchdog_unregister_device(&wdt
->wdt_device
);
675 s3c2410wdt_cpufreq_deregister(wdt
);
677 clk_disable_unprepare(wdt
->clock
);
682 static void s3c2410wdt_shutdown(struct platform_device
*dev
)
684 struct s3c2410_wdt
*wdt
= platform_get_drvdata(dev
);
686 s3c2410wdt_mask_and_disable_reset(wdt
, true);
688 s3c2410wdt_stop(&wdt
->wdt_device
);
691 #ifdef CONFIG_PM_SLEEP
693 static int s3c2410wdt_suspend(struct device
*dev
)
696 struct s3c2410_wdt
*wdt
= dev_get_drvdata(dev
);
698 /* Save watchdog state, and turn it off. */
699 wdt
->wtcon_save
= readl(wdt
->reg_base
+ S3C2410_WTCON
);
700 wdt
->wtdat_save
= readl(wdt
->reg_base
+ S3C2410_WTDAT
);
702 ret
= s3c2410wdt_mask_and_disable_reset(wdt
, true);
706 /* Note that WTCNT doesn't need to be saved. */
707 s3c2410wdt_stop(&wdt
->wdt_device
);
712 static int s3c2410wdt_resume(struct device
*dev
)
715 struct s3c2410_wdt
*wdt
= dev_get_drvdata(dev
);
717 /* Restore watchdog state. */
718 writel(wdt
->wtdat_save
, wdt
->reg_base
+ S3C2410_WTDAT
);
719 writel(wdt
->wtdat_save
, wdt
->reg_base
+ S3C2410_WTCNT
);/* Reset count */
720 writel(wdt
->wtcon_save
, wdt
->reg_base
+ S3C2410_WTCON
);
722 ret
= s3c2410wdt_mask_and_disable_reset(wdt
, false);
726 dev_info(dev
, "watchdog %sabled\n",
727 (wdt
->wtcon_save
& S3C2410_WTCON_ENABLE
) ? "en" : "dis");
733 static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops
, s3c2410wdt_suspend
,
736 static struct platform_driver s3c2410wdt_driver
= {
737 .probe
= s3c2410wdt_probe
,
738 .remove
= s3c2410wdt_remove
,
739 .shutdown
= s3c2410wdt_shutdown
,
740 .id_table
= s3c2410_wdt_ids
,
742 .name
= "s3c2410-wdt",
743 .pm
= &s3c2410wdt_pm_ops
,
744 .of_match_table
= of_match_ptr(s3c2410_wdt_match
),
748 module_platform_driver(s3c2410wdt_driver
);
750 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Dimitry Andric <dimitry.andric@tomtom.com>");
751 MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
752 MODULE_LICENSE("GPL");