drivers/watchdog/shwdt.c

   1 /*
   2  * drivers/watchdog/shwdt.c
   3  *
   4  * Watchdog driver for integrated watchdog in the SuperH processors.
   5  *
   6  * Copyright (C) 2001 - 2012  Paul Mundt <lethal@linux-sh.org>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License as published by the
  10  * Free Software Foundation; either version 2 of the License, or (at your
  11  * option) any later version.
  12  *
  13  * 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com>
  14  *     Added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT
  15  *
  16  * 19-Apr-2002 Rob Radez <rob@osinvestor.com>
  17  *     Added expect close support, made emulated timeout runtime changeable
  18  *     general cleanups, add some ioctls
  19  */
  20
  21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  22
  23 #include <linux/module.h>
  24 #include <linux/moduleparam.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/init.h>
  27 #include <linux/types.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/miscdevice.h>
  30 #include <linux/watchdog.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/fs.h>
  33 #include <linux/mm.h>
  34 #include <linux/slab.h>
  35 #include <linux/io.h>
  36 #include <linux/clk.h>
  37 #include <asm/watchdog.h>
  38
  39 #define DRV_NAME "sh-wdt"
  40
  41 /*
  42  * Default clock division ratio is 5.25 msecs. For an additional table of
  43  * values, consult the asm-sh/watchdog.h. Overload this at module load
  44  * time.
  45  *
  46  * In order for this to work reliably we need to have HZ set to 1000 or
  47  * something quite higher than 100 (or we need a proper high-res timer
  48  * implementation that will deal with this properly), otherwise the 10ms
  49  * resolution of a jiffy is enough to trigger the overflow. For things like
  50  * the SH-4 and SH-5, this isn't necessarily that big of a problem, though
  51  * for the SH-2 and SH-3, this isn't recommended unless the WDT is absolutely
  52  * necssary.
  53  *
  54  * As a result of this timing problem, the only modes that are particularly
  55  * feasible are the 4096 and the 2048 divisors, which yield 5.25 and 2.62ms
  56  * overflow periods respectively.
  57  *
  58  * Also, since we can't really expect userspace to be responsive enough
  59  * before the overflow happens, we maintain two separate timers .. One in
  60  * the kernel for clearing out WOVF every 2ms or so (again, this depends on
  61  * HZ == 1000), and another for monitoring userspace writes to the WDT device.
  62  *
  63  * As such, we currently use a configurable heartbeat interval which defaults
  64  * to 30s. In this case, the userspace daemon is only responsible for periodic
  65  * writes to the device before the next heartbeat is scheduled. If the daemon
  66  * misses its deadline, the kernel timer will allow the WDT to overflow.
  67  */
  68 static int clock_division_ratio = WTCSR_CKS_4096;
  69 #define next_ping_period(cks)   (jiffies + msecs_to_jiffies(cks - 4))
  70
  71 #define WATCHDOG_HEARTBEAT 30                   /* 30 sec default heartbeat */
  72 static int heartbeat = WATCHDOG_HEARTBEAT;      /* in seconds */
  73 static bool nowayout = WATCHDOG_NOWAYOUT;
  74 static unsigned long next_heartbeat;
  75
  76 struct sh_wdt {
  77         void __iomem            *base;
  78         struct device           *dev;
  79         struct clk              *clk;
  80         spinlock_t              lock;
  81
  82         struct timer_list       timer;
  83 };
  84
  85 static int sh_wdt_start(struct watchdog_device *wdt_dev)
  86 {
  87         struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
  88         unsigned long flags;
  89         u8 csr;
  90
  91         pm_runtime_get_sync(wdt->dev);
  92
  93         spin_lock_irqsave(&wdt->lock, flags);
  94
  95         next_heartbeat = jiffies + (heartbeat * HZ);
  96         mod_timer(&wdt->timer, next_ping_period(clock_division_ratio));
  97
  98         csr = sh_wdt_read_csr();
  99         csr |= WTCSR_WT | clock_division_ratio;
 100         sh_wdt_write_csr(csr);
 101
 102         sh_wdt_write_cnt(0);
 103
 104         /*
 105          * These processors have a bit of an inconsistent initialization
 106          * process.. starting with SH-3, RSTS was moved to WTCSR, and the
 107          * RSTCSR register was removed.
 108          *
 109          * On the SH-2 however, in addition with bits being in different
 110          * locations, we must deal with RSTCSR outright..
 111          */
 112         csr = sh_wdt_read_csr();
 113         csr |= WTCSR_TME;
 114         csr &= ~WTCSR_RSTS;
 115         sh_wdt_write_csr(csr);
 116
 117 #ifdef CONFIG_CPU_SH2
 118         csr = sh_wdt_read_rstcsr();
 119         csr &= ~RSTCSR_RSTS;
 120         sh_wdt_write_rstcsr(csr);
 121 #endif
 122         spin_unlock_irqrestore(&wdt->lock, flags);
 123
 124         return 0;
 125 }
 126
 127 static int sh_wdt_stop(struct watchdog_device *wdt_dev)
 128 {
 129         struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
 130         unsigned long flags;
 131         u8 csr;
 132
 133         spin_lock_irqsave(&wdt->lock, flags);
 134
 135         del_timer(&wdt->timer);
 136
 137         csr = sh_wdt_read_csr();
 138         csr &= ~WTCSR_TME;
 139         sh_wdt_write_csr(csr);
 140
 141         spin_unlock_irqrestore(&wdt->lock, flags);
 142
 143         pm_runtime_put_sync(wdt->dev);
 144
 145         return 0;
 146 }
 147
 148 static int sh_wdt_keepalive(struct watchdog_device *wdt_dev)
 149 {
 150         struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
 151         unsigned long flags;
 152
 153         spin_lock_irqsave(&wdt->lock, flags);
 154         next_heartbeat = jiffies + (heartbeat * HZ);
 155         spin_unlock_irqrestore(&wdt->lock, flags);
 156
 157         return 0;
 158 }
 159
 160 static int sh_wdt_set_heartbeat(struct watchdog_device *wdt_dev, unsigned t)
 161 {
 162         struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
 163         unsigned long flags;
 164
 165         if (unlikely(t < 1 || t > 3600)) /* arbitrary upper limit */
 166                 return -EINVAL;
 167
 168         spin_lock_irqsave(&wdt->lock, flags);
 169         heartbeat = t;
 170         wdt_dev->timeout = t;
 171         spin_unlock_irqrestore(&wdt->lock, flags);
 172
 173         return 0;
 174 }
 175
 176 static void sh_wdt_ping(unsigned long data)
 177 {
 178         struct sh_wdt *wdt = (struct sh_wdt *)data;
 179         unsigned long flags;
 180
 181         spin_lock_irqsave(&wdt->lock, flags);
 182         if (time_before(jiffies, next_heartbeat)) {
 183                 u8 csr;
 184
 185                 csr = sh_wdt_read_csr();
 186                 csr &= ~WTCSR_IOVF;
 187                 sh_wdt_write_csr(csr);
 188
 189                 sh_wdt_write_cnt(0);
 190
 191                 mod_timer(&wdt->timer, next_ping_period(clock_division_ratio));
 192         } else
 193                 dev_warn(wdt->dev, "Heartbeat lost! Will not ping "
 194                          "the watchdog\n");
 195         spin_unlock_irqrestore(&wdt->lock, flags);
 196 }
 197
 198 static const struct watchdog_info sh_wdt_info = {
 199         .options                = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
 200                                   WDIOF_MAGICCLOSE,
 201         .firmware_version       = 1,
 202         .identity               = "SH WDT",
 203 };
 204
 205 static const struct watchdog_ops sh_wdt_ops = {
 206         .owner          = THIS_MODULE,
 207         .start          = sh_wdt_start,
 208         .stop           = sh_wdt_stop,
 209         .ping           = sh_wdt_keepalive,
 210         .set_timeout    = sh_wdt_set_heartbeat,
 211 };
 212
 213 static struct watchdog_device sh_wdt_dev = {
 214         .info   = &sh_wdt_info,
 215         .ops    = &sh_wdt_ops,
 216 };
 217
 218 static int __devinit sh_wdt_probe(struct platform_device *pdev)
 219 {
 220         struct sh_wdt *wdt;
 221         struct resource *res;
 222         int rc;
 223
 224         /*
 225          * As this driver only covers the global watchdog case, reject
 226          * any attempts to register per-CPU watchdogs.
 227          */
 228         if (pdev->id != -1)
 229                 return -EINVAL;
 230
 231         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 232         if (unlikely(!res))
 233                 return -EINVAL;
 234
 235         wdt = devm_kzalloc(&pdev->dev, sizeof(struct sh_wdt), GFP_KERNEL);
 236         if (unlikely(!wdt))
 237                 return -ENOMEM;
 238
 239         wdt->dev = &pdev->dev;
 240
 241         wdt->clk = clk_get(&pdev->dev, NULL);
 242         if (IS_ERR(wdt->clk)) {
 243                 /*
 244                  * Clock framework support is optional, continue on
 245                  * anyways if we don't find a matching clock.
 246                  */
 247                 wdt->clk = NULL;
 248         }
 249
 250         clk_enable(wdt->clk);
 251
 252         wdt->base = devm_request_and_ioremap(wdt->dev, res);
 253         if (unlikely(!wdt->base)) {
 254                 rc = -EADDRNOTAVAIL;
 255                 goto out_disable;
 256         }
 257
 258         watchdog_set_nowayout(&sh_wdt_dev, nowayout);
 259         watchdog_set_drvdata(&sh_wdt_dev, wdt);
 260
 261         spin_lock_init(&wdt->lock);
 262
 263         rc = sh_wdt_set_heartbeat(&sh_wdt_dev, heartbeat);
 264         if (unlikely(rc)) {
 265                 /* Default timeout if invalid */
 266                 sh_wdt_set_heartbeat(&sh_wdt_dev, WATCHDOG_HEARTBEAT);
 267
 268                 dev_warn(&pdev->dev,
 269                          "heartbeat value must be 1<=x<=3600, using %d\n",
 270                          sh_wdt_dev.timeout);
 271         }
 272
 273         dev_info(&pdev->dev, "configured with heartbeat=%d sec (nowayout=%d)\n",
 274                  sh_wdt_dev.timeout, nowayout);
 275
 276         rc = watchdog_register_device(&sh_wdt_dev);
 277         if (unlikely(rc)) {
 278                 dev_err(&pdev->dev, "Can't register watchdog (err=%d)\n", rc);
 279                 goto out_disable;
 280         }
 281
 282         init_timer(&wdt->timer);
 283         wdt->timer.function     = sh_wdt_ping;
 284         wdt->timer.data         = (unsigned long)wdt;
 285         wdt->timer.expires      = next_ping_period(clock_division_ratio);
 286
 287         platform_set_drvdata(pdev, wdt);
 288
 289         dev_info(&pdev->dev, "initialized.\n");
 290
 291         pm_runtime_enable(&pdev->dev);
 292
 293         return 0;
 294
 295 out_disable:
 296         clk_disable(wdt->clk);
 297         clk_put(wdt->clk);
 298
 299         return rc;
 300 }
 301
 302 static int __devexit sh_wdt_remove(struct platform_device *pdev)
 303 {
 304         struct sh_wdt *wdt = platform_get_drvdata(pdev);
 305
 306         platform_set_drvdata(pdev, NULL);
 307
 308         watchdog_unregister_device(&sh_wdt_dev);
 309
 310         pm_runtime_disable(&pdev->dev);
 311         clk_disable(wdt->clk);
 312         clk_put(wdt->clk);
 313
 314         return 0;
 315 }
 316
 317 static void sh_wdt_shutdown(struct platform_device *pdev)
 318 {
 319         sh_wdt_stop(&sh_wdt_dev);
 320 }
 321
 322 static struct platform_driver sh_wdt_driver = {
 323         .driver         = {
 324                 .name   = DRV_NAME,
 325                 .owner  = THIS_MODULE,
 326         },
 327
 328         .probe          = sh_wdt_probe,
 329         .remove         = __devexit_p(sh_wdt_remove),
 330         .shutdown       = sh_wdt_shutdown,
 331 };
 332
 333 static int __init sh_wdt_init(void)
 334 {
 335         if (unlikely(clock_division_ratio < 0x5 ||
 336                      clock_division_ratio > 0x7)) {
 337                 clock_division_ratio = WTCSR_CKS_4096;
 338
 339                 pr_info("divisor must be 0x5<=x<=0x7, using %d\n",
 340                         clock_division_ratio);
 341         }
 342
 343         return platform_driver_register(&sh_wdt_driver);
 344 }
 345
 346 static void __exit sh_wdt_exit(void)
 347 {
 348         platform_driver_unregister(&sh_wdt_driver);
 349 }
 350 module_init(sh_wdt_init);
 351 module_exit(sh_wdt_exit);
 352
 353 MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>");
 354 MODULE_DESCRIPTION("SuperH watchdog driver");
 355 MODULE_LICENSE("GPL");
 356 MODULE_ALIAS("platform:" DRV_NAME);
 357 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
 358
 359 module_param(clock_division_ratio, int, 0);
 360 MODULE_PARM_DESC(clock_division_ratio,
 361         "Clock division ratio. Valid ranges are from 0x5 (1.31ms) "
 362         "to 0x7 (5.25ms). (default=" __MODULE_STRING(WTCSR_CKS_4096) ")");
 363
 364 module_param(heartbeat, int, 0);
 365 MODULE_PARM_DESC(heartbeat,
 366         "Watchdog heartbeat in seconds. (1 <= heartbeat <= 3600, default="
 367                                 __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
 368
 369 module_param(nowayout, bool, 0);
 370 MODULE_PARM_DESC(nowayout,
 371         "Watchdog cannot be stopped once started (default="
 372                                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");