exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  22 #define DEBUG_DISAS
  23
  24 #ifndef glue
  25 #define xglue(x, y) x ## y
  26 #define glue(x, y) xglue(x, y)
  27 #define stringify(s)    tostring(s)
  28 #define tostring(s)     #s
  29 #endif
  30
  31 #if __GNUC__ < 3
  32 #define __builtin_expect(x, n) (x)
  33 #endif
  34
  35 #define likely(x)   __builtin_expect(!!(x), 1)
  36 #define unlikely(x)   __builtin_expect(!!(x), 0)
  37
  38 #ifdef __i386__
  39 #define REGPARM(n) __attribute((regparm(n)))
  40 #else
  41 #define REGPARM(n)
  42 #endif
  43
  44 /* is_jmp field values */
  45 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  46 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  47 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  48 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  49
  50 struct TranslationBlock;
  51
  52 /* XXX: make safe guess about sizes */
  53 #define MAX_OP_PER_INSTR 32
  54 #define OPC_BUF_SIZE 512
  55 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  56
  57 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
  58
  59 extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
  60 extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
  61 extern long gen_labels[OPC_BUF_SIZE];
  62 extern int nb_gen_labels;
  63 extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
  64 extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
  65 extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
  66 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
  67 extern target_ulong gen_opc_jump_pc[2];
  68 extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
  69
  70 typedef void (GenOpFunc)(void);
  71 typedef void (GenOpFunc1)(long);
  72 typedef void (GenOpFunc2)(long, long);
  73 typedef void (GenOpFunc3)(long, long, long);
  74
  75 #if defined(TARGET_I386)
  76
  77 void optimize_flags_init(void);
  78
  79 #endif
  80
  81 extern FILE *logfile;
  82 extern int loglevel;
  83
  84 void muls64(int64_t *phigh, int64_t *plow, int64_t a, int64_t b);
  85 void mulu64(uint64_t *phigh, uint64_t *plow, uint64_t a, uint64_t b);
  86
  87 int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
  88 int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
  89 void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
  90 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
  91                  int max_code_size, int *gen_code_size_ptr);
  92 int cpu_restore_state(struct TranslationBlock *tb,
  93                       CPUState *env, unsigned long searched_pc,
  94                       void *puc);
  95 int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb,
  96                       int max_code_size, int *gen_code_size_ptr);
  97 int cpu_restore_state_copy(struct TranslationBlock *tb,
  98                            CPUState *env, unsigned long searched_pc,
  99                            void *puc);
 100 void cpu_resume_from_signal(CPUState *env1, void *puc);
 101 void cpu_exec_init(CPUState *env);
 102 int page_unprotect(target_ulong address, unsigned long pc, void *puc);
 103 void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
 104                                    int is_cpu_write_access);
 105 void tb_invalidate_page_range(target_ulong start, target_ulong end);
 106 void tlb_flush_page(CPUState *env, target_ulong addr);
 107 void tlb_flush(CPUState *env, int flush_global);
 108 int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
 109                       target_phys_addr_t paddr, int prot,
 110                       int is_user, int is_softmmu);
 111 static inline int tlb_set_page(CPUState *env, target_ulong vaddr,
 112                                target_phys_addr_t paddr, int prot,
 113                                int is_user, int is_softmmu)
 114 {
 115     if (prot & PAGE_READ)
 116         prot |= PAGE_EXEC;
 117     return tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
 118 }
 119
 120 #define CODE_GEN_MAX_SIZE        65536
 121 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 122
 123 #define CODE_GEN_PHYS_HASH_BITS     15
 124 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 125
 126 /* maximum total translate dcode allocated */
 127
 128 /* NOTE: the translated code area cannot be too big because on some
 129    archs the range of "fast" function calls is limited. Here is a
 130    summary of the ranges:
 131
 132    i386  : signed 32 bits
 133    arm   : signed 26 bits
 134    ppc   : signed 24 bits
 135    sparc : signed 32 bits
 136    alpha : signed 23 bits
 137 */
 138
 139 #if defined(__alpha__)
 140 #define CODE_GEN_BUFFER_SIZE     (2 * 1024 * 1024)
 141 #elif defined(__ia64)
 142 #define CODE_GEN_BUFFER_SIZE     (4 * 1024 * 1024)      /* range of addl */
 143 #elif defined(__powerpc__)
 144 #define CODE_GEN_BUFFER_SIZE     (6 * 1024 * 1024)
 145 #else
 146 #define CODE_GEN_BUFFER_SIZE     (16 * 1024 * 1024)
 147 #endif
 148
 149 //#define CODE_GEN_BUFFER_SIZE     (128 * 1024)
 150
 151 /* estimated block size for TB allocation */
 152 /* XXX: use a per code average code fragment size and modulate it
 153    according to the host CPU */
 154 #if defined(CONFIG_SOFTMMU)
 155 #define CODE_GEN_AVG_BLOCK_SIZE 128
 156 #else
 157 #define CODE_GEN_AVG_BLOCK_SIZE 64
 158 #endif
 159
 160 #define CODE_GEN_MAX_BLOCKS    (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
 161
 162 #if defined(__powerpc__)
 163 #define USE_DIRECT_JUMP
 164 #endif
 165 #if defined(__i386__) && !defined(_WIN32)
 166 #define USE_DIRECT_JUMP
 167 #endif
 168
 169 typedef struct TranslationBlock {
 170     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 171     target_ulong cs_base; /* CS base for this block */
 172     unsigned int flags; /* flags defining in which context the code was generated */
 173     uint16_t size;      /* size of target code for this block (1 <=
 174                            size <= TARGET_PAGE_SIZE) */
 175     uint16_t cflags;    /* compile flags */
 176 #define CF_CODE_COPY   0x0001 /* block was generated in code copy mode */
 177 #define CF_TB_FP_USED  0x0002 /* fp ops are used in the TB */
 178 #define CF_FP_USED     0x0004 /* fp ops are used in the TB or in a chained TB */
 179 #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
 180
 181     uint8_t *tc_ptr;    /* pointer to the translated code */
 182     /* next matching tb for physical address. */
 183     struct TranslationBlock *phys_hash_next;
 184     /* first and second physical page containing code. The lower bit
 185        of the pointer tells the index in page_next[] */
 186     struct TranslationBlock *page_next[2];
 187     target_ulong page_addr[2];
 188
 189     /* the following data are used to directly call another TB from
 190        the code of this one. */
 191     uint16_t tb_next_offset[2]; /* offset of original jump target */
 192 #ifdef USE_DIRECT_JUMP
 193     uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
 194 #else
 195     uint32_t tb_next[2]; /* address of jump generated code */
 196 #endif
 197     /* list of TBs jumping to this one. This is a circular list using
 198        the two least significant bits of the pointers to tell what is
 199        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 200        jmp_first */
 201     struct TranslationBlock *jmp_next[2];
 202     struct TranslationBlock *jmp_first;
 203 } TranslationBlock;
 204
 205 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
 206 {
 207     target_ulong tmp;
 208     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 209     return (tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK;
 210 }
 211
 212 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
 213 {
 214     target_ulong tmp;
 215     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 216     return (((tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK) |
 217             (tmp & TB_JMP_ADDR_MASK));
 218 }
 219
 220 static inline unsigned int tb_phys_hash_func(unsigned long pc)
 221 {
 222     return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
 223 }
 224
 225 TranslationBlock *tb_alloc(target_ulong pc);
 226 void tb_flush(CPUState *env);
 227 void tb_link_phys(TranslationBlock *tb,
 228                   target_ulong phys_pc, target_ulong phys_page2);
 229
 230 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 231
 232 extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
 233 extern uint8_t *code_gen_ptr;
 234
 235 #if defined(USE_DIRECT_JUMP)
 236
 237 #if defined(__powerpc__)
 238 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 239 {
 240     uint32_t val, *ptr;
 241
 242     /* patch the branch destination */
 243     ptr = (uint32_t *)jmp_addr;
 244     val = *ptr;
 245     val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
 246     *ptr = val;
 247     /* flush icache */
 248     asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
 249     asm volatile ("sync" : : : "memory");
 250     asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
 251     asm volatile ("sync" : : : "memory");
 252     asm volatile ("isync" : : : "memory");
 253 }
 254 #elif defined(__i386__)
 255 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 256 {
 257     /* patch the branch destination */
 258     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 259     /* no need to flush icache explicitely */
 260 }
 261 #endif
 262
 263 static inline void tb_set_jmp_target(TranslationBlock *tb,
 264                                      int n, unsigned long addr)
 265 {
 266     unsigned long offset;
 267
 268     offset = tb->tb_jmp_offset[n];
 269     tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 270     offset = tb->tb_jmp_offset[n + 2];
 271     if (offset != 0xffff)
 272         tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 273 }
 274
 275 #else
 276
 277 /* set the jump target */
 278 static inline void tb_set_jmp_target(TranslationBlock *tb,
 279                                      int n, unsigned long addr)
 280 {
 281     tb->tb_next[n] = addr;
 282 }
 283
 284 #endif
 285
 286 static inline void tb_add_jump(TranslationBlock *tb, int n,
 287                                TranslationBlock *tb_next)
 288 {
 289     /* NOTE: this test is only needed for thread safety */
 290     if (!tb->jmp_next[n]) {
 291         /* patch the native jump address */
 292         tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
 293
 294         /* add in TB jmp circular list */
 295         tb->jmp_next[n] = tb_next->jmp_first;
 296         tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
 297     }
 298 }
 299
 300 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
 301
 302 #ifndef offsetof
 303 #define offsetof(type, field) ((size_t) &((type *)0)->field)
 304 #endif
 305
 306 #if defined(_WIN32)
 307 #define ASM_DATA_SECTION ".section \".data\"\n"
 308 #define ASM_PREVIOUS_SECTION ".section .text\n"
 309 #elif defined(__APPLE__)
 310 #define ASM_DATA_SECTION ".data\n"
 311 #define ASM_PREVIOUS_SECTION ".text\n"
 312 #else
 313 #define ASM_DATA_SECTION ".section \".data\"\n"
 314 #define ASM_PREVIOUS_SECTION ".previous\n"
 315 #endif
 316
 317 #define ASM_OP_LABEL_NAME(n, opname) \
 318     ASM_NAME(__op_label) #n "." ASM_NAME(opname)
 319
 320 #if defined(__powerpc__)
 321
 322 /* we patch the jump instruction directly */
 323 #define GOTO_TB(opname, tbparam, n)\
 324 do {\
 325     asm volatile (ASM_DATA_SECTION\
 326                   ASM_OP_LABEL_NAME(n, opname) ":\n"\
 327                   ".long 1f\n"\
 328                   ASM_PREVIOUS_SECTION \
 329                   "b " ASM_NAME(__op_jmp) #n "\n"\
 330                   "1:\n");\
 331 } while (0)
 332
 333 #elif defined(__i386__) && defined(USE_DIRECT_JUMP)
 334
 335 /* we patch the jump instruction directly */
 336 #define GOTO_TB(opname, tbparam, n)\
 337 do {\
 338     asm volatile (".section .data\n"\
 339                   ASM_OP_LABEL_NAME(n, opname) ":\n"\
 340                   ".long 1f\n"\
 341                   ASM_PREVIOUS_SECTION \
 342                   "jmp " ASM_NAME(__op_jmp) #n "\n"\
 343                   "1:\n");\
 344 } while (0)
 345
 346 #elif defined(__s390__)
 347 /* GCC spills R13, so we have to restore it before branching away */
 348
 349 #define GOTO_TB(opname, tbparam, n)\
 350 do {\
 351     static void __attribute__((used)) *dummy ## n = &&dummy_label ## n;\
 352     static void __attribute__((used)) *__op_label ## n \
 353         __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\
 354         __asm__ __volatile__ ( \
 355                 "l %%r13,52(%%r15)\n" \
 356                 "br %0\n" \
 357         : : "r" (((TranslationBlock*)tbparam)->tb_next[n]));\
 358         \
 359         for(;*((int*)0);); /* just to keep GCC busy */ \
 360 label ## n: ;\
 361 dummy_label ## n: ;\
 362 } while(0)
 363
 364 #else
 365
 366 /* jump to next block operations (more portable code, does not need
 367    cache flushing, but slower because of indirect jump) */
 368 #define GOTO_TB(opname, tbparam, n)\
 369 do {\
 370     static void __attribute__((used)) *dummy ## n = &&dummy_label ## n;\
 371     static void __attribute__((used)) *__op_label ## n \
 372         __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\
 373     goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
 374 label ## n: ;\
 375 dummy_label ## n: ;\
 376 } while (0)
 377
 378 #endif
 379
 380 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
 381 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
 382 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
 383
 384 #if defined(__powerpc__)
 385 static inline int testandset (int *p)
 386 {
 387     int ret;
 388     __asm__ __volatile__ (
 389                           "0:    lwarx %0,0,%1\n"
 390                           "      xor. %0,%3,%0\n"
 391                           "      bne 1f\n"
 392                           "      stwcx. %2,0,%1\n"
 393                           "      bne- 0b\n"
 394                           "1:    "
 395                           : "=&r" (ret)
 396                           : "r" (p), "r" (1), "r" (0)
 397                           : "cr0", "memory");
 398     return ret;
 399 }
 400 #elif defined(__i386__)
 401 static inline int testandset (int *p)
 402 {
 403     long int readval = 0;
 404
 405     __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
 406                           : "+m" (*p), "+a" (readval)
 407                           : "r" (1)
 408                           : "cc");
 409     return readval;
 410 }
 411 #elif defined(__x86_64__)
 412 static inline int testandset (int *p)
 413 {
 414     long int readval = 0;
 415
 416     __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
 417                           : "+m" (*p), "+a" (readval)
 418                           : "r" (1)
 419                           : "cc");
 420     return readval;
 421 }
 422 #elif defined(__s390__)
 423 static inline int testandset (int *p)
 424 {
 425     int ret;
 426
 427     __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
 428                           "   jl    0b"
 429                           : "=&d" (ret)
 430                           : "r" (1), "a" (p), "0" (*p)
 431                           : "cc", "memory" );
 432     return ret;
 433 }
 434 #elif defined(__alpha__)
 435 static inline int testandset (int *p)
 436 {
 437     int ret;
 438     unsigned long one;
 439
 440     __asm__ __volatile__ ("0:   mov 1,%2\n"
 441                           "     ldl_l %0,%1\n"
 442                           "     stl_c %2,%1\n"
 443                           "     beq %2,1f\n"
 444                           ".subsection 2\n"
 445                           "1:   br 0b\n"
 446                           ".previous"
 447                           : "=r" (ret), "=m" (*p), "=r" (one)
 448                           : "m" (*p));
 449     return ret;
 450 }
 451 #elif defined(__sparc__)
 452 static inline int testandset (int *p)
 453 {
 454         int ret;
 455
 456         __asm__ __volatile__("ldstub    [%1], %0"
 457                              : "=r" (ret)
 458                              : "r" (p)
 459                              : "memory");
 460
 461         return (ret ? 1 : 0);
 462 }
 463 #elif defined(__arm__)
 464 static inline int testandset (int *spinlock)
 465 {
 466     register unsigned int ret;
 467     __asm__ __volatile__("swp %0, %1, [%2]"
 468                          : "=r"(ret)
 469                          : "0"(1), "r"(spinlock));
 470
 471     return ret;
 472 }
 473 #elif defined(__mc68000)
 474 static inline int testandset (int *p)
 475 {
 476     char ret;
 477     __asm__ __volatile__("tas %1; sne %0"
 478                          : "=r" (ret)
 479                          : "m" (p)
 480                          : "cc","memory");
 481     return ret;
 482 }
 483 #elif defined(__ia64)
 484
 485 #include <ia64intrin.h>
 486
 487 static inline int testandset (int *p)
 488 {
 489     return __sync_lock_test_and_set (p, 1);
 490 }
 491 #elif defined(__mips__)
 492 static inline int testandset (int *p)
 493 {
 494     int ret;
 495
 496     __asm__ __volatile__ (
 497         "       .set push               \n"
 498         "       .set noat               \n"
 499         "       .set mips2              \n"
 500         "1:     li      $1, 1           \n"
 501         "       ll      %0, %1          \n"
 502         "       sc      $1, %1          \n"
 503         "       beqz    $1, 1b          \n"
 504         "       .set pop                "
 505         : "=r" (ret), "+R" (*p)
 506         :
 507         : "memory");
 508
 509     return ret;
 510 }
 511 #else
 512 #error unimplemented CPU support
 513 #endif
 514
 515 typedef int spinlock_t;
 516
 517 #define SPIN_LOCK_UNLOCKED 0
 518
 519 #if defined(CONFIG_USER_ONLY)
 520 static inline void spin_lock(spinlock_t *lock)
 521 {
 522     while (testandset(lock));
 523 }
 524
 525 static inline void spin_unlock(spinlock_t *lock)
 526 {
 527     *lock = 0;
 528 }
 529
 530 static inline int spin_trylock(spinlock_t *lock)
 531 {
 532     return !testandset(lock);
 533 }
 534 #else
 535 static inline void spin_lock(spinlock_t *lock)
 536 {
 537 }
 538
 539 static inline void spin_unlock(spinlock_t *lock)
 540 {
 541 }
 542
 543 static inline int spin_trylock(spinlock_t *lock)
 544 {
 545     return 1;
 546 }
 547 #endif
 548
 549 extern spinlock_t tb_lock;
 550
 551 extern int tb_invalidated_flag;
 552
 553 #if !defined(CONFIG_USER_ONLY)
 554
 555 void tlb_fill(target_ulong addr, int is_write, int is_user,
 556               void *retaddr);
 557
 558 #define ACCESS_TYPE 3
 559 #define MEMSUFFIX _code
 560 #define env cpu_single_env
 561
 562 #define DATA_SIZE 1
 563 #include "softmmu_header.h"
 564
 565 #define DATA_SIZE 2
 566 #include "softmmu_header.h"
 567
 568 #define DATA_SIZE 4
 569 #include "softmmu_header.h"
 570
 571 #define DATA_SIZE 8
 572 #include "softmmu_header.h"
 573
 574 #undef ACCESS_TYPE
 575 #undef MEMSUFFIX
 576 #undef env
 577
 578 #endif
 579
 580 #if defined(CONFIG_USER_ONLY)
 581 static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
 582 {
 583     return addr;
 584 }
 585 #else
 586 /* NOTE: this function can trigger an exception */
 587 /* NOTE2: the returned address is not exactly the physical address: it
 588    is the offset relative to phys_ram_base */
 589 static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
 590 {
 591     int is_user, index, pd;
 592
 593     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 594 #if defined(TARGET_I386)
 595     is_user = ((env->hflags & HF_CPL_MASK) == 3);
 596 #elif defined (TARGET_PPC)
 597     is_user = msr_pr;
 598 #elif defined (TARGET_MIPS)
 599     is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);
 600 #elif defined (TARGET_SPARC)
 601     is_user = (env->psrs == 0);
 602 #elif defined (TARGET_ARM)
 603     is_user = ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR);
 604 #elif defined (TARGET_SH4)
 605     is_user = ((env->sr & SR_MD) == 0);
 606 #elif defined (TARGET_ALPHA)
 607     is_user = ((env->ps >> 3) & 3);
 608 #elif defined (TARGET_M68K)
 609     is_user = ((env->sr & SR_S) == 0);
 610 #else
 611 #error unimplemented CPU
 612 #endif
 613     if (__builtin_expect(env->tlb_table[is_user][index].addr_code !=
 614                          (addr & TARGET_PAGE_MASK), 0)) {
 615         ldub_code(addr);
 616     }
 617     pd = env->tlb_table[is_user][index].addr_code & ~TARGET_PAGE_MASK;
 618     if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
 619 #ifdef TARGET_SPARC
 620         do_unassigned_access(addr, 0, 1, 0);
 621 #else
 622         cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
 623 #endif
 624     }
 625     return addr + env->tlb_table[is_user][index].addend - (unsigned long)phys_ram_base;
 626 }
 627 #endif
 628
 629 #ifdef USE_KQEMU
 630 #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))
 631
 632 int kqemu_init(CPUState *env);
 633 int kqemu_cpu_exec(CPUState *env);
 634 void kqemu_flush_page(CPUState *env, target_ulong addr);
 635 void kqemu_flush(CPUState *env, int global);
 636 void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
 637 void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
 638 void kqemu_cpu_interrupt(CPUState *env);
 639 void kqemu_record_dump(void);
 640
 641 static inline int kqemu_is_ok(CPUState *env)
 642 {
 643     return(env->kqemu_enabled &&
 644            (env->cr[0] & CR0_PE_MASK) &&
 645            !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
 646            (env->eflags & IF_MASK) &&
 647            !(env->eflags & VM_MASK) &&
 648            (env->kqemu_enabled == 2 ||
 649             ((env->hflags & HF_CPL_MASK) == 3 &&
 650              (env->eflags & IOPL_MASK) != IOPL_MASK)));
 651 }
 652
 653 #endif