4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
22 #include "qemu/cutils.h"
24 #include "exec/exec-all.h"
25 #include "exec/target_page.h"
27 #include "hw/qdev-core.h"
28 #include "hw/qdev-properties.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #include "hw/boards.h"
31 #include "hw/xen/xen.h"
33 #include "sysemu/kvm.h"
34 #include "sysemu/sysemu.h"
35 #include "qemu/timer.h"
36 #include "qemu/config-file.h"
37 #include "qemu/error-report.h"
38 #include "qemu/qemu-print.h"
39 #if defined(CONFIG_USER_ONLY)
41 #else /* !CONFIG_USER_ONLY */
43 #include "exec/memory.h"
44 #include "exec/ioport.h"
45 #include "sysemu/dma.h"
46 #include "sysemu/numa.h"
47 #include "sysemu/hw_accel.h"
48 #include "exec/address-spaces.h"
49 #include "sysemu/xen-mapcache.h"
50 #include "trace-root.h"
52 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
53 #include <linux/falloc.h>
57 #include "qemu/rcu_queue.h"
58 #include "qemu/main-loop.h"
59 #include "translate-all.h"
60 #include "sysemu/replay.h"
62 #include "exec/memory-internal.h"
63 #include "exec/ram_addr.h"
66 #include "migration/vmstate.h"
68 #include "qemu/range.h"
70 #include "qemu/mmap-alloc.h"
73 #include "monitor/monitor.h"
75 //#define DEBUG_SUBPAGE
77 #if !defined(CONFIG_USER_ONLY)
78 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
79 * are protected by the ramlist lock.
81 RAMList ram_list
= { .blocks
= QLIST_HEAD_INITIALIZER(ram_list
.blocks
) };
83 static MemoryRegion
*system_memory
;
84 static MemoryRegion
*system_io
;
86 AddressSpace address_space_io
;
87 AddressSpace address_space_memory
;
89 MemoryRegion io_mem_rom
, io_mem_notdirty
;
90 static MemoryRegion io_mem_unassigned
;
93 #ifdef TARGET_PAGE_BITS_VARY
95 bool target_page_bits_decided
;
98 CPUTailQ cpus
= QTAILQ_HEAD_INITIALIZER(cpus
);
100 /* current CPU in the current thread. It is only valid inside
102 __thread CPUState
*current_cpu
;
103 /* 0 = Do not count executed instructions.
104 1 = Precise instruction counting.
105 2 = Adaptive rate instruction counting. */
108 uintptr_t qemu_host_page_size
;
109 intptr_t qemu_host_page_mask
;
111 bool set_preferred_target_page_bits(int bits
)
113 /* The target page size is the lowest common denominator for all
114 * the CPUs in the system, so we can only make it smaller, never
115 * larger. And we can't make it smaller once we've committed to
118 #ifdef TARGET_PAGE_BITS_VARY
119 assert(bits
>= TARGET_PAGE_BITS_MIN
);
120 if (target_page_bits
== 0 || target_page_bits
> bits
) {
121 if (target_page_bits_decided
) {
124 target_page_bits
= bits
;
130 #if !defined(CONFIG_USER_ONLY)
132 static void finalize_target_page_bits(void)
134 #ifdef TARGET_PAGE_BITS_VARY
135 if (target_page_bits
== 0) {
136 target_page_bits
= TARGET_PAGE_BITS_MIN
;
138 target_page_bits_decided
= true;
142 typedef struct PhysPageEntry PhysPageEntry
;
144 struct PhysPageEntry
{
145 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
147 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
151 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
153 /* Size of the L2 (and L3, etc) page tables. */
154 #define ADDR_SPACE_BITS 64
157 #define P_L2_SIZE (1 << P_L2_BITS)
159 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
161 typedef PhysPageEntry Node
[P_L2_SIZE
];
163 typedef struct PhysPageMap
{
166 unsigned sections_nb
;
167 unsigned sections_nb_alloc
;
169 unsigned nodes_nb_alloc
;
171 MemoryRegionSection
*sections
;
174 struct AddressSpaceDispatch
{
175 MemoryRegionSection
*mru_section
;
176 /* This is a multi-level map on the physical address space.
177 * The bottom level has pointers to MemoryRegionSections.
179 PhysPageEntry phys_map
;
183 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
184 typedef struct subpage_t
{
188 uint16_t sub_section
[];
191 #define PHYS_SECTION_UNASSIGNED 0
192 #define PHYS_SECTION_NOTDIRTY 1
193 #define PHYS_SECTION_ROM 2
194 #define PHYS_SECTION_WATCH 3
196 static void io_mem_init(void);
197 static void memory_map_init(void);
198 static void tcg_commit(MemoryListener
*listener
);
200 static MemoryRegion io_mem_watch
;
203 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
204 * @cpu: the CPU whose AddressSpace this is
205 * @as: the AddressSpace itself
206 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
207 * @tcg_as_listener: listener for tracking changes to the AddressSpace
209 struct CPUAddressSpace
{
212 struct AddressSpaceDispatch
*memory_dispatch
;
213 MemoryListener tcg_as_listener
;
216 struct DirtyBitmapSnapshot
{
219 unsigned long dirty
[];
224 #if !defined(CONFIG_USER_ONLY)
226 static void phys_map_node_reserve(PhysPageMap
*map
, unsigned nodes
)
228 static unsigned alloc_hint
= 16;
229 if (map
->nodes_nb
+ nodes
> map
->nodes_nb_alloc
) {
230 map
->nodes_nb_alloc
= MAX(map
->nodes_nb_alloc
, alloc_hint
);
231 map
->nodes_nb_alloc
= MAX(map
->nodes_nb_alloc
, map
->nodes_nb
+ nodes
);
232 map
->nodes
= g_renew(Node
, map
->nodes
, map
->nodes_nb_alloc
);
233 alloc_hint
= map
->nodes_nb_alloc
;
237 static uint32_t phys_map_node_alloc(PhysPageMap
*map
, bool leaf
)
244 ret
= map
->nodes_nb
++;
246 assert(ret
!= PHYS_MAP_NODE_NIL
);
247 assert(ret
!= map
->nodes_nb_alloc
);
249 e
.skip
= leaf
? 0 : 1;
250 e
.ptr
= leaf
? PHYS_SECTION_UNASSIGNED
: PHYS_MAP_NODE_NIL
;
251 for (i
= 0; i
< P_L2_SIZE
; ++i
) {
252 memcpy(&p
[i
], &e
, sizeof(e
));
257 static void phys_page_set_level(PhysPageMap
*map
, PhysPageEntry
*lp
,
258 hwaddr
*index
, hwaddr
*nb
, uint16_t leaf
,
262 hwaddr step
= (hwaddr
)1 << (level
* P_L2_BITS
);
264 if (lp
->skip
&& lp
->ptr
== PHYS_MAP_NODE_NIL
) {
265 lp
->ptr
= phys_map_node_alloc(map
, level
== 0);
267 p
= map
->nodes
[lp
->ptr
];
268 lp
= &p
[(*index
>> (level
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
270 while (*nb
&& lp
< &p
[P_L2_SIZE
]) {
271 if ((*index
& (step
- 1)) == 0 && *nb
>= step
) {
277 phys_page_set_level(map
, lp
, index
, nb
, leaf
, level
- 1);
283 static void phys_page_set(AddressSpaceDispatch
*d
,
284 hwaddr index
, hwaddr nb
,
287 /* Wildly overreserve - it doesn't matter much. */
288 phys_map_node_reserve(&d
->map
, 3 * P_L2_LEVELS
);
290 phys_page_set_level(&d
->map
, &d
->phys_map
, &index
, &nb
, leaf
, P_L2_LEVELS
- 1);
293 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
294 * and update our entry so we can skip it and go directly to the destination.
296 static void phys_page_compact(PhysPageEntry
*lp
, Node
*nodes
)
298 unsigned valid_ptr
= P_L2_SIZE
;
303 if (lp
->ptr
== PHYS_MAP_NODE_NIL
) {
308 for (i
= 0; i
< P_L2_SIZE
; i
++) {
309 if (p
[i
].ptr
== PHYS_MAP_NODE_NIL
) {
316 phys_page_compact(&p
[i
], nodes
);
320 /* We can only compress if there's only one child. */
325 assert(valid_ptr
< P_L2_SIZE
);
327 /* Don't compress if it won't fit in the # of bits we have. */
328 if (lp
->skip
+ p
[valid_ptr
].skip
>= (1 << 3)) {
332 lp
->ptr
= p
[valid_ptr
].ptr
;
333 if (!p
[valid_ptr
].skip
) {
334 /* If our only child is a leaf, make this a leaf. */
335 /* By design, we should have made this node a leaf to begin with so we
336 * should never reach here.
337 * But since it's so simple to handle this, let's do it just in case we
342 lp
->skip
+= p
[valid_ptr
].skip
;
346 void address_space_dispatch_compact(AddressSpaceDispatch
*d
)
348 if (d
->phys_map
.skip
) {
349 phys_page_compact(&d
->phys_map
, d
->map
.nodes
);
353 static inline bool section_covers_addr(const MemoryRegionSection
*section
,
356 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
357 * the section must cover the entire address space.
359 return int128_gethi(section
->size
) ||
360 range_covers_byte(section
->offset_within_address_space
,
361 int128_getlo(section
->size
), addr
);
364 static MemoryRegionSection
*phys_page_find(AddressSpaceDispatch
*d
, hwaddr addr
)
366 PhysPageEntry lp
= d
->phys_map
, *p
;
367 Node
*nodes
= d
->map
.nodes
;
368 MemoryRegionSection
*sections
= d
->map
.sections
;
369 hwaddr index
= addr
>> TARGET_PAGE_BITS
;
372 for (i
= P_L2_LEVELS
; lp
.skip
&& (i
-= lp
.skip
) >= 0;) {
373 if (lp
.ptr
== PHYS_MAP_NODE_NIL
) {
374 return §ions
[PHYS_SECTION_UNASSIGNED
];
377 lp
= p
[(index
>> (i
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
380 if (section_covers_addr(§ions
[lp
.ptr
], addr
)) {
381 return §ions
[lp
.ptr
];
383 return §ions
[PHYS_SECTION_UNASSIGNED
];
387 /* Called from RCU critical section */
388 static MemoryRegionSection
*address_space_lookup_region(AddressSpaceDispatch
*d
,
390 bool resolve_subpage
)
392 MemoryRegionSection
*section
= atomic_read(&d
->mru_section
);
395 if (!section
|| section
== &d
->map
.sections
[PHYS_SECTION_UNASSIGNED
] ||
396 !section_covers_addr(section
, addr
)) {
397 section
= phys_page_find(d
, addr
);
398 atomic_set(&d
->mru_section
, section
);
400 if (resolve_subpage
&& section
->mr
->subpage
) {
401 subpage
= container_of(section
->mr
, subpage_t
, iomem
);
402 section
= &d
->map
.sections
[subpage
->sub_section
[SUBPAGE_IDX(addr
)]];
407 /* Called from RCU critical section */
408 static MemoryRegionSection
*
409 address_space_translate_internal(AddressSpaceDispatch
*d
, hwaddr addr
, hwaddr
*xlat
,
410 hwaddr
*plen
, bool resolve_subpage
)
412 MemoryRegionSection
*section
;
416 section
= address_space_lookup_region(d
, addr
, resolve_subpage
);
417 /* Compute offset within MemoryRegionSection */
418 addr
-= section
->offset_within_address_space
;
420 /* Compute offset within MemoryRegion */
421 *xlat
= addr
+ section
->offset_within_region
;
425 /* MMIO registers can be expected to perform full-width accesses based only
426 * on their address, without considering adjacent registers that could
427 * decode to completely different MemoryRegions. When such registers
428 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
429 * regions overlap wildly. For this reason we cannot clamp the accesses
432 * If the length is small (as is the case for address_space_ldl/stl),
433 * everything works fine. If the incoming length is large, however,
434 * the caller really has to do the clamping through memory_access_size.
436 if (memory_region_is_ram(mr
)) {
437 diff
= int128_sub(section
->size
, int128_make64(addr
));
438 *plen
= int128_get64(int128_min(diff
, int128_make64(*plen
)));
444 * address_space_translate_iommu - translate an address through an IOMMU
445 * memory region and then through the target address space.
447 * @iommu_mr: the IOMMU memory region that we start the translation from
448 * @addr: the address to be translated through the MMU
449 * @xlat: the translated address offset within the destination memory region.
450 * It cannot be %NULL.
451 * @plen_out: valid read/write length of the translated address. It
453 * @page_mask_out: page mask for the translated address. This
454 * should only be meaningful for IOMMU translated
455 * addresses, since there may be huge pages that this bit
456 * would tell. It can be %NULL if we don't care about it.
457 * @is_write: whether the translation operation is for write
458 * @is_mmio: whether this can be MMIO, set true if it can
459 * @target_as: the address space targeted by the IOMMU
460 * @attrs: transaction attributes
462 * This function is called from RCU critical section. It is the common
463 * part of flatview_do_translate and address_space_translate_cached.
465 static MemoryRegionSection
address_space_translate_iommu(IOMMUMemoryRegion
*iommu_mr
,
468 hwaddr
*page_mask_out
,
471 AddressSpace
**target_as
,
474 MemoryRegionSection
*section
;
475 hwaddr page_mask
= (hwaddr
)-1;
479 IOMMUMemoryRegionClass
*imrc
= memory_region_get_iommu_class_nocheck(iommu_mr
);
483 if (imrc
->attrs_to_index
) {
484 iommu_idx
= imrc
->attrs_to_index(iommu_mr
, attrs
);
487 iotlb
= imrc
->translate(iommu_mr
, addr
, is_write
?
488 IOMMU_WO
: IOMMU_RO
, iommu_idx
);
490 if (!(iotlb
.perm
& (1 << is_write
))) {
494 addr
= ((iotlb
.translated_addr
& ~iotlb
.addr_mask
)
495 | (addr
& iotlb
.addr_mask
));
496 page_mask
&= iotlb
.addr_mask
;
497 *plen_out
= MIN(*plen_out
, (addr
| iotlb
.addr_mask
) - addr
+ 1);
498 *target_as
= iotlb
.target_as
;
500 section
= address_space_translate_internal(
501 address_space_to_dispatch(iotlb
.target_as
), addr
, xlat
,
504 iommu_mr
= memory_region_get_iommu(section
->mr
);
505 } while (unlikely(iommu_mr
));
508 *page_mask_out
= page_mask
;
513 return (MemoryRegionSection
) { .mr
= &io_mem_unassigned
};
517 * flatview_do_translate - translate an address in FlatView
519 * @fv: the flat view that we want to translate on
520 * @addr: the address to be translated in above address space
521 * @xlat: the translated address offset within memory region. It
523 * @plen_out: valid read/write length of the translated address. It
524 * can be @NULL when we don't care about it.
525 * @page_mask_out: page mask for the translated address. This
526 * should only be meaningful for IOMMU translated
527 * addresses, since there may be huge pages that this bit
528 * would tell. It can be @NULL if we don't care about it.
529 * @is_write: whether the translation operation is for write
530 * @is_mmio: whether this can be MMIO, set true if it can
531 * @target_as: the address space targeted by the IOMMU
532 * @attrs: memory transaction attributes
534 * This function is called from RCU critical section
536 static MemoryRegionSection
flatview_do_translate(FlatView
*fv
,
540 hwaddr
*page_mask_out
,
543 AddressSpace
**target_as
,
546 MemoryRegionSection
*section
;
547 IOMMUMemoryRegion
*iommu_mr
;
548 hwaddr plen
= (hwaddr
)(-1);
554 section
= address_space_translate_internal(
555 flatview_to_dispatch(fv
), addr
, xlat
,
558 iommu_mr
= memory_region_get_iommu(section
->mr
);
559 if (unlikely(iommu_mr
)) {
560 return address_space_translate_iommu(iommu_mr
, xlat
,
561 plen_out
, page_mask_out
,
566 /* Not behind an IOMMU, use default page size. */
567 *page_mask_out
= ~TARGET_PAGE_MASK
;
573 /* Called from RCU critical section */
574 IOMMUTLBEntry
address_space_get_iotlb_entry(AddressSpace
*as
, hwaddr addr
,
575 bool is_write
, MemTxAttrs attrs
)
577 MemoryRegionSection section
;
578 hwaddr xlat
, page_mask
;
581 * This can never be MMIO, and we don't really care about plen,
584 section
= flatview_do_translate(address_space_to_flatview(as
), addr
, &xlat
,
585 NULL
, &page_mask
, is_write
, false, &as
,
588 /* Illegal translation */
589 if (section
.mr
== &io_mem_unassigned
) {
593 /* Convert memory region offset into address space offset */
594 xlat
+= section
.offset_within_address_space
-
595 section
.offset_within_region
;
597 return (IOMMUTLBEntry
) {
599 .iova
= addr
& ~page_mask
,
600 .translated_addr
= xlat
& ~page_mask
,
601 .addr_mask
= page_mask
,
602 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
607 return (IOMMUTLBEntry
) {0};
610 /* Called from RCU critical section */
611 MemoryRegion
*flatview_translate(FlatView
*fv
, hwaddr addr
, hwaddr
*xlat
,
612 hwaddr
*plen
, bool is_write
,
616 MemoryRegionSection section
;
617 AddressSpace
*as
= NULL
;
619 /* This can be MMIO, so setup MMIO bit. */
620 section
= flatview_do_translate(fv
, addr
, xlat
, plen
, NULL
,
621 is_write
, true, &as
, attrs
);
624 if (xen_enabled() && memory_access_is_direct(mr
, is_write
)) {
625 hwaddr page
= ((addr
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
) - addr
;
626 *plen
= MIN(page
, *plen
);
632 typedef struct TCGIOMMUNotifier
{
640 static void tcg_iommu_unmap_notify(IOMMUNotifier
*n
, IOMMUTLBEntry
*iotlb
)
642 TCGIOMMUNotifier
*notifier
= container_of(n
, TCGIOMMUNotifier
, n
);
644 if (!notifier
->active
) {
647 tlb_flush(notifier
->cpu
);
648 notifier
->active
= false;
649 /* We leave the notifier struct on the list to avoid reallocating it later.
650 * Generally the number of IOMMUs a CPU deals with will be small.
651 * In any case we can't unregister the iommu notifier from a notify
656 static void tcg_register_iommu_notifier(CPUState
*cpu
,
657 IOMMUMemoryRegion
*iommu_mr
,
660 /* Make sure this CPU has an IOMMU notifier registered for this
661 * IOMMU/IOMMU index combination, so that we can flush its TLB
662 * when the IOMMU tells us the mappings we've cached have changed.
664 MemoryRegion
*mr
= MEMORY_REGION(iommu_mr
);
665 TCGIOMMUNotifier
*notifier
;
668 for (i
= 0; i
< cpu
->iommu_notifiers
->len
; i
++) {
669 notifier
= g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
*, i
);
670 if (notifier
->mr
== mr
&& notifier
->iommu_idx
== iommu_idx
) {
674 if (i
== cpu
->iommu_notifiers
->len
) {
675 /* Not found, add a new entry at the end of the array */
676 cpu
->iommu_notifiers
= g_array_set_size(cpu
->iommu_notifiers
, i
+ 1);
677 notifier
= g_new0(TCGIOMMUNotifier
, 1);
678 g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
*, i
) = notifier
;
681 notifier
->iommu_idx
= iommu_idx
;
683 /* Rather than trying to register interest in the specific part
684 * of the iommu's address space that we've accessed and then
685 * expand it later as subsequent accesses touch more of it, we
686 * just register interest in the whole thing, on the assumption
687 * that iommu reconfiguration will be rare.
689 iommu_notifier_init(¬ifier
->n
,
690 tcg_iommu_unmap_notify
,
691 IOMMU_NOTIFIER_UNMAP
,
695 memory_region_register_iommu_notifier(notifier
->mr
, ¬ifier
->n
);
698 if (!notifier
->active
) {
699 notifier
->active
= true;
703 static void tcg_iommu_free_notifier_list(CPUState
*cpu
)
705 /* Destroy the CPU's notifier list */
707 TCGIOMMUNotifier
*notifier
;
709 for (i
= 0; i
< cpu
->iommu_notifiers
->len
; i
++) {
710 notifier
= g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
*, i
);
711 memory_region_unregister_iommu_notifier(notifier
->mr
, ¬ifier
->n
);
714 g_array_free(cpu
->iommu_notifiers
, true);
717 /* Called from RCU critical section */
718 MemoryRegionSection
*
719 address_space_translate_for_iotlb(CPUState
*cpu
, int asidx
, hwaddr addr
,
720 hwaddr
*xlat
, hwaddr
*plen
,
721 MemTxAttrs attrs
, int *prot
)
723 MemoryRegionSection
*section
;
724 IOMMUMemoryRegion
*iommu_mr
;
725 IOMMUMemoryRegionClass
*imrc
;
728 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpu
->cpu_ases
[asidx
].memory_dispatch
);
731 section
= address_space_translate_internal(d
, addr
, &addr
, plen
, false);
733 iommu_mr
= memory_region_get_iommu(section
->mr
);
738 imrc
= memory_region_get_iommu_class_nocheck(iommu_mr
);
740 iommu_idx
= imrc
->attrs_to_index(iommu_mr
, attrs
);
741 tcg_register_iommu_notifier(cpu
, iommu_mr
, iommu_idx
);
742 /* We need all the permissions, so pass IOMMU_NONE so the IOMMU
743 * doesn't short-cut its translation table walk.
745 iotlb
= imrc
->translate(iommu_mr
, addr
, IOMMU_NONE
, iommu_idx
);
746 addr
= ((iotlb
.translated_addr
& ~iotlb
.addr_mask
)
747 | (addr
& iotlb
.addr_mask
));
748 /* Update the caller's prot bits to remove permissions the IOMMU
749 * is giving us a failure response for. If we get down to no
750 * permissions left at all we can give up now.
752 if (!(iotlb
.perm
& IOMMU_RO
)) {
753 *prot
&= ~(PAGE_READ
| PAGE_EXEC
);
755 if (!(iotlb
.perm
& IOMMU_WO
)) {
756 *prot
&= ~PAGE_WRITE
;
763 d
= flatview_to_dispatch(address_space_to_flatview(iotlb
.target_as
));
766 assert(!memory_region_is_iommu(section
->mr
));
771 return &d
->map
.sections
[PHYS_SECTION_UNASSIGNED
];
775 #if !defined(CONFIG_USER_ONLY)
777 static int cpu_common_post_load(void *opaque
, int version_id
)
779 CPUState
*cpu
= opaque
;
781 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
782 version_id is increased. */
783 cpu
->interrupt_request
&= ~0x01;
786 /* loadvm has just updated the content of RAM, bypassing the
787 * usual mechanisms that ensure we flush TBs for writes to
788 * memory we've translated code from. So we must flush all TBs,
789 * which will now be stale.
796 static int cpu_common_pre_load(void *opaque
)
798 CPUState
*cpu
= opaque
;
800 cpu
->exception_index
= -1;
805 static bool cpu_common_exception_index_needed(void *opaque
)
807 CPUState
*cpu
= opaque
;
809 return tcg_enabled() && cpu
->exception_index
!= -1;
812 static const VMStateDescription vmstate_cpu_common_exception_index
= {
813 .name
= "cpu_common/exception_index",
815 .minimum_version_id
= 1,
816 .needed
= cpu_common_exception_index_needed
,
817 .fields
= (VMStateField
[]) {
818 VMSTATE_INT32(exception_index
, CPUState
),
819 VMSTATE_END_OF_LIST()
823 static bool cpu_common_crash_occurred_needed(void *opaque
)
825 CPUState
*cpu
= opaque
;
827 return cpu
->crash_occurred
;
830 static const VMStateDescription vmstate_cpu_common_crash_occurred
= {
831 .name
= "cpu_common/crash_occurred",
833 .minimum_version_id
= 1,
834 .needed
= cpu_common_crash_occurred_needed
,
835 .fields
= (VMStateField
[]) {
836 VMSTATE_BOOL(crash_occurred
, CPUState
),
837 VMSTATE_END_OF_LIST()
841 const VMStateDescription vmstate_cpu_common
= {
842 .name
= "cpu_common",
844 .minimum_version_id
= 1,
845 .pre_load
= cpu_common_pre_load
,
846 .post_load
= cpu_common_post_load
,
847 .fields
= (VMStateField
[]) {
848 VMSTATE_UINT32(halted
, CPUState
),
849 VMSTATE_UINT32(interrupt_request
, CPUState
),
850 VMSTATE_END_OF_LIST()
852 .subsections
= (const VMStateDescription
*[]) {
853 &vmstate_cpu_common_exception_index
,
854 &vmstate_cpu_common_crash_occurred
,
861 CPUState
*qemu_get_cpu(int index
)
866 if (cpu
->cpu_index
== index
) {
874 #if !defined(CONFIG_USER_ONLY)
875 void cpu_address_space_init(CPUState
*cpu
, int asidx
,
876 const char *prefix
, MemoryRegion
*mr
)
878 CPUAddressSpace
*newas
;
879 AddressSpace
*as
= g_new0(AddressSpace
, 1);
883 as_name
= g_strdup_printf("%s-%d", prefix
, cpu
->cpu_index
);
884 address_space_init(as
, mr
, as_name
);
887 /* Target code should have set num_ases before calling us */
888 assert(asidx
< cpu
->num_ases
);
891 /* address space 0 gets the convenience alias */
895 /* KVM cannot currently support multiple address spaces. */
896 assert(asidx
== 0 || !kvm_enabled());
898 if (!cpu
->cpu_ases
) {
899 cpu
->cpu_ases
= g_new0(CPUAddressSpace
, cpu
->num_ases
);
902 newas
= &cpu
->cpu_ases
[asidx
];
906 newas
->tcg_as_listener
.commit
= tcg_commit
;
907 memory_listener_register(&newas
->tcg_as_listener
, as
);
911 AddressSpace
*cpu_get_address_space(CPUState
*cpu
, int asidx
)
913 /* Return the AddressSpace corresponding to the specified index */
914 return cpu
->cpu_ases
[asidx
].as
;
918 void cpu_exec_unrealizefn(CPUState
*cpu
)
920 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
922 cpu_list_remove(cpu
);
924 if (cc
->vmsd
!= NULL
) {
925 vmstate_unregister(NULL
, cc
->vmsd
, cpu
);
927 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
928 vmstate_unregister(NULL
, &vmstate_cpu_common
, cpu
);
930 #ifndef CONFIG_USER_ONLY
931 tcg_iommu_free_notifier_list(cpu
);
935 Property cpu_common_props
[] = {
936 #ifndef CONFIG_USER_ONLY
937 /* Create a memory property for softmmu CPU object,
938 * so users can wire up its memory. (This can't go in qom/cpu.c
939 * because that file is compiled only once for both user-mode
940 * and system builds.) The default if no link is set up is to use
941 * the system address space.
943 DEFINE_PROP_LINK("memory", CPUState
, memory
, TYPE_MEMORY_REGION
,
946 DEFINE_PROP_END_OF_LIST(),
949 void cpu_exec_initfn(CPUState
*cpu
)
954 #ifndef CONFIG_USER_ONLY
955 cpu
->thread_id
= qemu_get_thread_id();
956 cpu
->memory
= system_memory
;
957 object_ref(OBJECT(cpu
->memory
));
961 void cpu_exec_realizefn(CPUState
*cpu
, Error
**errp
)
963 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
964 static bool tcg_target_initialized
;
968 if (tcg_enabled() && !tcg_target_initialized
) {
969 tcg_target_initialized
= true;
970 cc
->tcg_initialize();
974 #ifndef CONFIG_USER_ONLY
975 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
976 vmstate_register(NULL
, cpu
->cpu_index
, &vmstate_cpu_common
, cpu
);
978 if (cc
->vmsd
!= NULL
) {
979 vmstate_register(NULL
, cpu
->cpu_index
, cc
->vmsd
, cpu
);
982 cpu
->iommu_notifiers
= g_array_new(false, true, sizeof(TCGIOMMUNotifier
*));
986 const char *parse_cpu_option(const char *cpu_option
)
990 gchar
**model_pieces
;
991 const char *cpu_type
;
993 model_pieces
= g_strsplit(cpu_option
, ",", 2);
994 if (!model_pieces
[0]) {
995 error_report("-cpu option cannot be empty");
999 oc
= cpu_class_by_name(CPU_RESOLVING_TYPE
, model_pieces
[0]);
1001 error_report("unable to find CPU model '%s'", model_pieces
[0]);
1002 g_strfreev(model_pieces
);
1006 cpu_type
= object_class_get_name(oc
);
1008 cc
->parse_features(cpu_type
, model_pieces
[1], &error_fatal
);
1009 g_strfreev(model_pieces
);
1013 #if defined(CONFIG_USER_ONLY)
1014 void tb_invalidate_phys_addr(target_ulong addr
)
1017 tb_invalidate_phys_page_range(addr
, addr
+ 1, 0);
1021 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
1023 tb_invalidate_phys_addr(pc
);
1026 void tb_invalidate_phys_addr(AddressSpace
*as
, hwaddr addr
, MemTxAttrs attrs
)
1028 ram_addr_t ram_addr
;
1032 if (!tcg_enabled()) {
1037 mr
= address_space_translate(as
, addr
, &addr
, &l
, false, attrs
);
1038 if (!(memory_region_is_ram(mr
)
1039 || memory_region_is_romd(mr
))) {
1043 ram_addr
= memory_region_get_ram_addr(mr
) + addr
;
1044 tb_invalidate_phys_page_range(ram_addr
, ram_addr
+ 1, 0);
1048 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
1051 hwaddr phys
= cpu_get_phys_page_attrs_debug(cpu
, pc
, &attrs
);
1052 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
1054 /* Locks grabbed by tb_invalidate_phys_addr */
1055 tb_invalidate_phys_addr(cpu
->cpu_ases
[asidx
].as
,
1056 phys
| (pc
& ~TARGET_PAGE_MASK
), attrs
);
1061 #if defined(CONFIG_USER_ONLY)
1062 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
1067 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
, vaddr len
,
1073 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
)
1077 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
1078 int flags
, CPUWatchpoint
**watchpoint
)
1083 /* Add a watchpoint. */
1084 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
1085 int flags
, CPUWatchpoint
**watchpoint
)
1089 /* forbid ranges which are empty or run off the end of the address space */
1090 if (len
== 0 || (addr
+ len
- 1) < addr
) {
1091 error_report("tried to set invalid watchpoint at %"
1092 VADDR_PRIx
", len=%" VADDR_PRIu
, addr
, len
);
1095 wp
= g_malloc(sizeof(*wp
));
1101 /* keep all GDB-injected watchpoints in front */
1102 if (flags
& BP_GDB
) {
1103 QTAILQ_INSERT_HEAD(&cpu
->watchpoints
, wp
, entry
);
1105 QTAILQ_INSERT_TAIL(&cpu
->watchpoints
, wp
, entry
);
1108 tlb_flush_page(cpu
, addr
);
1115 /* Remove a specific watchpoint. */
1116 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
, vaddr len
,
1121 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
1122 if (addr
== wp
->vaddr
&& len
== wp
->len
1123 && flags
== (wp
->flags
& ~BP_WATCHPOINT_HIT
)) {
1124 cpu_watchpoint_remove_by_ref(cpu
, wp
);
1131 /* Remove a specific watchpoint by reference. */
1132 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
)
1134 QTAILQ_REMOVE(&cpu
->watchpoints
, watchpoint
, entry
);
1136 tlb_flush_page(cpu
, watchpoint
->vaddr
);
1141 /* Remove all matching watchpoints. */
1142 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
1144 CPUWatchpoint
*wp
, *next
;
1146 QTAILQ_FOREACH_SAFE(wp
, &cpu
->watchpoints
, entry
, next
) {
1147 if (wp
->flags
& mask
) {
1148 cpu_watchpoint_remove_by_ref(cpu
, wp
);
1153 /* Return true if this watchpoint address matches the specified
1154 * access (ie the address range covered by the watchpoint overlaps
1155 * partially or completely with the address range covered by the
1158 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint
*wp
,
1162 /* We know the lengths are non-zero, but a little caution is
1163 * required to avoid errors in the case where the range ends
1164 * exactly at the top of the address space and so addr + len
1165 * wraps round to zero.
1167 vaddr wpend
= wp
->vaddr
+ wp
->len
- 1;
1168 vaddr addrend
= addr
+ len
- 1;
1170 return !(addr
> wpend
|| wp
->vaddr
> addrend
);
1175 /* Add a breakpoint. */
1176 int cpu_breakpoint_insert(CPUState
*cpu
, vaddr pc
, int flags
,
1177 CPUBreakpoint
**breakpoint
)
1181 bp
= g_malloc(sizeof(*bp
));
1186 /* keep all GDB-injected breakpoints in front */
1187 if (flags
& BP_GDB
) {
1188 QTAILQ_INSERT_HEAD(&cpu
->breakpoints
, bp
, entry
);
1190 QTAILQ_INSERT_TAIL(&cpu
->breakpoints
, bp
, entry
);
1193 breakpoint_invalidate(cpu
, pc
);
1201 /* Remove a specific breakpoint. */
1202 int cpu_breakpoint_remove(CPUState
*cpu
, vaddr pc
, int flags
)
1206 QTAILQ_FOREACH(bp
, &cpu
->breakpoints
, entry
) {
1207 if (bp
->pc
== pc
&& bp
->flags
== flags
) {
1208 cpu_breakpoint_remove_by_ref(cpu
, bp
);
1215 /* Remove a specific breakpoint by reference. */
1216 void cpu_breakpoint_remove_by_ref(CPUState
*cpu
, CPUBreakpoint
*breakpoint
)
1218 QTAILQ_REMOVE(&cpu
->breakpoints
, breakpoint
, entry
);
1220 breakpoint_invalidate(cpu
, breakpoint
->pc
);
1225 /* Remove all matching breakpoints. */
1226 void cpu_breakpoint_remove_all(CPUState
*cpu
, int mask
)
1228 CPUBreakpoint
*bp
, *next
;
1230 QTAILQ_FOREACH_SAFE(bp
, &cpu
->breakpoints
, entry
, next
) {
1231 if (bp
->flags
& mask
) {
1232 cpu_breakpoint_remove_by_ref(cpu
, bp
);
1237 /* enable or disable single step mode. EXCP_DEBUG is returned by the
1238 CPU loop after each instruction */
1239 void cpu_single_step(CPUState
*cpu
, int enabled
)
1241 if (cpu
->singlestep_enabled
!= enabled
) {
1242 cpu
->singlestep_enabled
= enabled
;
1243 if (kvm_enabled()) {
1244 kvm_update_guest_debug(cpu
, 0);
1246 /* must flush all the translated code to avoid inconsistencies */
1247 /* XXX: only flush what is necessary */
1253 void cpu_abort(CPUState
*cpu
, const char *fmt
, ...)
1260 fprintf(stderr
, "qemu: fatal: ");
1261 vfprintf(stderr
, fmt
, ap
);
1262 fprintf(stderr
, "\n");
1263 cpu_dump_state(cpu
, stderr
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1264 if (qemu_log_separate()) {
1266 qemu_log("qemu: fatal: ");
1267 qemu_log_vprintf(fmt
, ap2
);
1269 log_cpu_state(cpu
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1277 #if defined(CONFIG_USER_ONLY)
1279 struct sigaction act
;
1280 sigfillset(&act
.sa_mask
);
1281 act
.sa_handler
= SIG_DFL
;
1283 sigaction(SIGABRT
, &act
, NULL
);
1289 #if !defined(CONFIG_USER_ONLY)
1290 /* Called from RCU critical section */
1291 static RAMBlock
*qemu_get_ram_block(ram_addr_t addr
)
1295 block
= atomic_rcu_read(&ram_list
.mru_block
);
1296 if (block
&& addr
- block
->offset
< block
->max_length
) {
1299 RAMBLOCK_FOREACH(block
) {
1300 if (addr
- block
->offset
< block
->max_length
) {
1305 fprintf(stderr
, "Bad ram offset %" PRIx64
"\n", (uint64_t)addr
);
1309 /* It is safe to write mru_block outside the iothread lock. This
1314 * xxx removed from list
1318 * call_rcu(reclaim_ramblock, xxx);
1321 * atomic_rcu_set is not needed here. The block was already published
1322 * when it was placed into the list. Here we're just making an extra
1323 * copy of the pointer.
1325 ram_list
.mru_block
= block
;
1329 static void tlb_reset_dirty_range_all(ram_addr_t start
, ram_addr_t length
)
1336 assert(tcg_enabled());
1337 end
= TARGET_PAGE_ALIGN(start
+ length
);
1338 start
&= TARGET_PAGE_MASK
;
1341 block
= qemu_get_ram_block(start
);
1342 assert(block
== qemu_get_ram_block(end
- 1));
1343 start1
= (uintptr_t)ramblock_ptr(block
, start
- block
->offset
);
1345 tlb_reset_dirty(cpu
, start1
, length
);
1350 /* Note: start and end must be within the same ram block. */
1351 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start
,
1355 DirtyMemoryBlocks
*blocks
;
1356 unsigned long end
, page
;
1363 end
= TARGET_PAGE_ALIGN(start
+ length
) >> TARGET_PAGE_BITS
;
1364 page
= start
>> TARGET_PAGE_BITS
;
1368 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1370 while (page
< end
) {
1371 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1372 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1373 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1375 dirty
|= bitmap_test_and_clear_atomic(blocks
->blocks
[idx
],
1382 if (dirty
&& tcg_enabled()) {
1383 tlb_reset_dirty_range_all(start
, length
);
1389 DirtyBitmapSnapshot
*cpu_physical_memory_snapshot_and_clear_dirty
1390 (ram_addr_t start
, ram_addr_t length
, unsigned client
)
1392 DirtyMemoryBlocks
*blocks
;
1393 unsigned long align
= 1UL << (TARGET_PAGE_BITS
+ BITS_PER_LEVEL
);
1394 ram_addr_t first
= QEMU_ALIGN_DOWN(start
, align
);
1395 ram_addr_t last
= QEMU_ALIGN_UP(start
+ length
, align
);
1396 DirtyBitmapSnapshot
*snap
;
1397 unsigned long page
, end
, dest
;
1399 snap
= g_malloc0(sizeof(*snap
) +
1400 ((last
- first
) >> (TARGET_PAGE_BITS
+ 3)));
1401 snap
->start
= first
;
1404 page
= first
>> TARGET_PAGE_BITS
;
1405 end
= last
>> TARGET_PAGE_BITS
;
1410 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1412 while (page
< end
) {
1413 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1414 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1415 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1417 assert(QEMU_IS_ALIGNED(offset
, (1 << BITS_PER_LEVEL
)));
1418 assert(QEMU_IS_ALIGNED(num
, (1 << BITS_PER_LEVEL
)));
1419 offset
>>= BITS_PER_LEVEL
;
1421 bitmap_copy_and_clear_atomic(snap
->dirty
+ dest
,
1422 blocks
->blocks
[idx
] + offset
,
1425 dest
+= num
>> BITS_PER_LEVEL
;
1430 if (tcg_enabled()) {
1431 tlb_reset_dirty_range_all(start
, length
);
1437 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot
*snap
,
1441 unsigned long page
, end
;
1443 assert(start
>= snap
->start
);
1444 assert(start
+ length
<= snap
->end
);
1446 end
= TARGET_PAGE_ALIGN(start
+ length
- snap
->start
) >> TARGET_PAGE_BITS
;
1447 page
= (start
- snap
->start
) >> TARGET_PAGE_BITS
;
1449 while (page
< end
) {
1450 if (test_bit(page
, snap
->dirty
)) {
1458 /* Called from RCU critical section */
1459 hwaddr
memory_region_section_get_iotlb(CPUState
*cpu
,
1460 MemoryRegionSection
*section
,
1462 hwaddr paddr
, hwaddr xlat
,
1464 target_ulong
*address
)
1469 if (memory_region_is_ram(section
->mr
)) {
1471 iotlb
= memory_region_get_ram_addr(section
->mr
) + xlat
;
1472 if (!section
->readonly
) {
1473 iotlb
|= PHYS_SECTION_NOTDIRTY
;
1475 iotlb
|= PHYS_SECTION_ROM
;
1478 AddressSpaceDispatch
*d
;
1480 d
= flatview_to_dispatch(section
->fv
);
1481 iotlb
= section
- d
->map
.sections
;
1485 /* Make accesses to pages with watchpoints go via the
1486 watchpoint trap routines. */
1487 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
1488 if (cpu_watchpoint_address_matches(wp
, vaddr
, TARGET_PAGE_SIZE
)) {
1489 /* Avoid trapping reads of pages with a write breakpoint. */
1490 if ((prot
& PAGE_WRITE
) || (wp
->flags
& BP_MEM_READ
)) {
1491 iotlb
= PHYS_SECTION_WATCH
+ paddr
;
1492 *address
|= TLB_MMIO
;
1500 #endif /* defined(CONFIG_USER_ONLY) */
1502 #if !defined(CONFIG_USER_ONLY)
1504 static int subpage_register (subpage_t
*mmio
, uint32_t start
, uint32_t end
,
1506 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
);
1508 static void *(*phys_mem_alloc
)(size_t size
, uint64_t *align
, bool shared
) =
1509 qemu_anon_ram_alloc
;
1512 * Set a custom physical guest memory alloator.
1513 * Accelerators with unusual needs may need this. Hopefully, we can
1514 * get rid of it eventually.
1516 void phys_mem_set_alloc(void *(*alloc
)(size_t, uint64_t *align
, bool shared
))
1518 phys_mem_alloc
= alloc
;
1521 static uint16_t phys_section_add(PhysPageMap
*map
,
1522 MemoryRegionSection
*section
)
1524 /* The physical section number is ORed with a page-aligned
1525 * pointer to produce the iotlb entries. Thus it should
1526 * never overflow into the page-aligned value.
1528 assert(map
->sections_nb
< TARGET_PAGE_SIZE
);
1530 if (map
->sections_nb
== map
->sections_nb_alloc
) {
1531 map
->sections_nb_alloc
= MAX(map
->sections_nb_alloc
* 2, 16);
1532 map
->sections
= g_renew(MemoryRegionSection
, map
->sections
,
1533 map
->sections_nb_alloc
);
1535 map
->sections
[map
->sections_nb
] = *section
;
1536 memory_region_ref(section
->mr
);
1537 return map
->sections_nb
++;
1540 static void phys_section_destroy(MemoryRegion
*mr
)
1542 bool have_sub_page
= mr
->subpage
;
1544 memory_region_unref(mr
);
1546 if (have_sub_page
) {
1547 subpage_t
*subpage
= container_of(mr
, subpage_t
, iomem
);
1548 object_unref(OBJECT(&subpage
->iomem
));
1553 static void phys_sections_free(PhysPageMap
*map
)
1555 while (map
->sections_nb
> 0) {
1556 MemoryRegionSection
*section
= &map
->sections
[--map
->sections_nb
];
1557 phys_section_destroy(section
->mr
);
1559 g_free(map
->sections
);
1563 static void register_subpage(FlatView
*fv
, MemoryRegionSection
*section
)
1565 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1567 hwaddr base
= section
->offset_within_address_space
1569 MemoryRegionSection
*existing
= phys_page_find(d
, base
);
1570 MemoryRegionSection subsection
= {
1571 .offset_within_address_space
= base
,
1572 .size
= int128_make64(TARGET_PAGE_SIZE
),
1576 assert(existing
->mr
->subpage
|| existing
->mr
== &io_mem_unassigned
);
1578 if (!(existing
->mr
->subpage
)) {
1579 subpage
= subpage_init(fv
, base
);
1581 subsection
.mr
= &subpage
->iomem
;
1582 phys_page_set(d
, base
>> TARGET_PAGE_BITS
, 1,
1583 phys_section_add(&d
->map
, &subsection
));
1585 subpage
= container_of(existing
->mr
, subpage_t
, iomem
);
1587 start
= section
->offset_within_address_space
& ~TARGET_PAGE_MASK
;
1588 end
= start
+ int128_get64(section
->size
) - 1;
1589 subpage_register(subpage
, start
, end
,
1590 phys_section_add(&d
->map
, section
));
1594 static void register_multipage(FlatView
*fv
,
1595 MemoryRegionSection
*section
)
1597 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1598 hwaddr start_addr
= section
->offset_within_address_space
;
1599 uint16_t section_index
= phys_section_add(&d
->map
, section
);
1600 uint64_t num_pages
= int128_get64(int128_rshift(section
->size
,
1604 phys_page_set(d
, start_addr
>> TARGET_PAGE_BITS
, num_pages
, section_index
);
1608 * The range in *section* may look like this:
1612 * where s stands for subpage and P for page.
1614 void flatview_add_to_dispatch(FlatView
*fv
, MemoryRegionSection
*section
)
1616 MemoryRegionSection remain
= *section
;
1617 Int128 page_size
= int128_make64(TARGET_PAGE_SIZE
);
1619 /* register first subpage */
1620 if (remain
.offset_within_address_space
& ~TARGET_PAGE_MASK
) {
1621 uint64_t left
= TARGET_PAGE_ALIGN(remain
.offset_within_address_space
)
1622 - remain
.offset_within_address_space
;
1624 MemoryRegionSection now
= remain
;
1625 now
.size
= int128_min(int128_make64(left
), now
.size
);
1626 register_subpage(fv
, &now
);
1627 if (int128_eq(remain
.size
, now
.size
)) {
1630 remain
.size
= int128_sub(remain
.size
, now
.size
);
1631 remain
.offset_within_address_space
+= int128_get64(now
.size
);
1632 remain
.offset_within_region
+= int128_get64(now
.size
);
1635 /* register whole pages */
1636 if (int128_ge(remain
.size
, page_size
)) {
1637 MemoryRegionSection now
= remain
;
1638 now
.size
= int128_and(now
.size
, int128_neg(page_size
));
1639 register_multipage(fv
, &now
);
1640 if (int128_eq(remain
.size
, now
.size
)) {
1643 remain
.size
= int128_sub(remain
.size
, now
.size
);
1644 remain
.offset_within_address_space
+= int128_get64(now
.size
);
1645 remain
.offset_within_region
+= int128_get64(now
.size
);
1648 /* register last subpage */
1649 register_subpage(fv
, &remain
);
1652 void qemu_flush_coalesced_mmio_buffer(void)
1655 kvm_flush_coalesced_mmio_buffer();
1658 void qemu_mutex_lock_ramlist(void)
1660 qemu_mutex_lock(&ram_list
.mutex
);
1663 void qemu_mutex_unlock_ramlist(void)
1665 qemu_mutex_unlock(&ram_list
.mutex
);
1668 void ram_block_dump(Monitor
*mon
)
1674 monitor_printf(mon
, "%24s %8s %18s %18s %18s\n",
1675 "Block Name", "PSize", "Offset", "Used", "Total");
1676 RAMBLOCK_FOREACH(block
) {
1677 psize
= size_to_str(block
->page_size
);
1678 monitor_printf(mon
, "%24s %8s 0x%016" PRIx64
" 0x%016" PRIx64
1679 " 0x%016" PRIx64
"\n", block
->idstr
, psize
,
1680 (uint64_t)block
->offset
,
1681 (uint64_t)block
->used_length
,
1682 (uint64_t)block
->max_length
);
1690 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1691 * may or may not name the same files / on the same filesystem now as
1692 * when we actually open and map them. Iterate over the file
1693 * descriptors instead, and use qemu_fd_getpagesize().
1695 static int find_max_supported_pagesize(Object
*obj
, void *opaque
)
1697 long *hpsize_min
= opaque
;
1699 if (object_dynamic_cast(obj
, TYPE_MEMORY_BACKEND
)) {
1700 HostMemoryBackend
*backend
= MEMORY_BACKEND(obj
);
1701 long hpsize
= host_memory_backend_pagesize(backend
);
1703 if (host_memory_backend_is_mapped(backend
) && (hpsize
< *hpsize_min
)) {
1704 *hpsize_min
= hpsize
;
1711 long qemu_getrampagesize(void)
1713 long hpsize
= LONG_MAX
;
1714 long mainrampagesize
;
1715 Object
*memdev_root
;
1717 mainrampagesize
= qemu_mempath_getpagesize(mem_path
);
1719 /* it's possible we have memory-backend objects with
1720 * hugepage-backed RAM. these may get mapped into system
1721 * address space via -numa parameters or memory hotplug
1722 * hooks. we want to take these into account, but we
1723 * also want to make sure these supported hugepage
1724 * sizes are applicable across the entire range of memory
1725 * we may boot from, so we take the min across all
1726 * backends, and assume normal pages in cases where a
1727 * backend isn't backed by hugepages.
1729 memdev_root
= object_resolve_path("/objects", NULL
);
1731 object_child_foreach(memdev_root
, find_max_supported_pagesize
, &hpsize
);
1733 if (hpsize
== LONG_MAX
) {
1734 /* No additional memory regions found ==> Report main RAM page size */
1735 return mainrampagesize
;
1738 /* If NUMA is disabled or the NUMA nodes are not backed with a
1739 * memory-backend, then there is at least one node using "normal" RAM,
1740 * so if its page size is smaller we have got to report that size instead.
1742 if (hpsize
> mainrampagesize
&&
1743 (nb_numa_nodes
== 0 || numa_info
[0].node_memdev
== NULL
)) {
1746 error_report("Huge page support disabled (n/a for main memory).");
1749 return mainrampagesize
;
1755 long qemu_getrampagesize(void)
1757 return getpagesize();
1762 static int64_t get_file_size(int fd
)
1764 int64_t size
= lseek(fd
, 0, SEEK_END
);
1771 static int file_ram_open(const char *path
,
1772 const char *region_name
,
1777 char *sanitized_name
;
1783 fd
= open(path
, O_RDWR
);
1785 /* @path names an existing file, use it */
1788 if (errno
== ENOENT
) {
1789 /* @path names a file that doesn't exist, create it */
1790 fd
= open(path
, O_RDWR
| O_CREAT
| O_EXCL
, 0644);
1795 } else if (errno
== EISDIR
) {
1796 /* @path names a directory, create a file there */
1797 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1798 sanitized_name
= g_strdup(region_name
);
1799 for (c
= sanitized_name
; *c
!= '\0'; c
++) {
1805 filename
= g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path
,
1807 g_free(sanitized_name
);
1809 fd
= mkstemp(filename
);
1817 if (errno
!= EEXIST
&& errno
!= EINTR
) {
1818 error_setg_errno(errp
, errno
,
1819 "can't open backing store %s for guest RAM",
1824 * Try again on EINTR and EEXIST. The latter happens when
1825 * something else creates the file between our two open().
1832 static void *file_ram_alloc(RAMBlock
*block
,
1840 block
->page_size
= qemu_fd_getpagesize(fd
);
1841 if (block
->mr
->align
% block
->page_size
) {
1842 error_setg(errp
, "alignment 0x%" PRIx64
1843 " must be multiples of page size 0x%zx",
1844 block
->mr
->align
, block
->page_size
);
1846 } else if (block
->mr
->align
&& !is_power_of_2(block
->mr
->align
)) {
1847 error_setg(errp
, "alignment 0x%" PRIx64
1848 " must be a power of two", block
->mr
->align
);
1851 block
->mr
->align
= MAX(block
->page_size
, block
->mr
->align
);
1852 #if defined(__s390x__)
1853 if (kvm_enabled()) {
1854 block
->mr
->align
= MAX(block
->mr
->align
, QEMU_VMALLOC_ALIGN
);
1858 if (memory
< block
->page_size
) {
1859 error_setg(errp
, "memory size 0x" RAM_ADDR_FMT
" must be equal to "
1860 "or larger than page size 0x%zx",
1861 memory
, block
->page_size
);
1865 memory
= ROUND_UP(memory
, block
->page_size
);
1868 * ftruncate is not supported by hugetlbfs in older
1869 * hosts, so don't bother bailing out on errors.
1870 * If anything goes wrong with it under other filesystems,
1873 * Do not truncate the non-empty backend file to avoid corrupting
1874 * the existing data in the file. Disabling shrinking is not
1875 * enough. For example, the current vNVDIMM implementation stores
1876 * the guest NVDIMM labels at the end of the backend file. If the
1877 * backend file is later extended, QEMU will not be able to find
1878 * those labels. Therefore, extending the non-empty backend file
1879 * is disabled as well.
1881 if (truncate
&& ftruncate(fd
, memory
)) {
1882 perror("ftruncate");
1885 area
= qemu_ram_mmap(fd
, memory
, block
->mr
->align
,
1886 block
->flags
& RAM_SHARED
);
1887 if (area
== MAP_FAILED
) {
1888 error_setg_errno(errp
, errno
,
1889 "unable to map backing store for guest RAM");
1894 os_mem_prealloc(fd
, area
, memory
, smp_cpus
, errp
);
1895 if (errp
&& *errp
) {
1896 qemu_ram_munmap(fd
, area
, memory
);
1906 /* Allocate space within the ram_addr_t space that governs the
1908 * Called with the ramlist lock held.
1910 static ram_addr_t
find_ram_offset(ram_addr_t size
)
1912 RAMBlock
*block
, *next_block
;
1913 ram_addr_t offset
= RAM_ADDR_MAX
, mingap
= RAM_ADDR_MAX
;
1915 assert(size
!= 0); /* it would hand out same offset multiple times */
1917 if (QLIST_EMPTY_RCU(&ram_list
.blocks
)) {
1921 RAMBLOCK_FOREACH(block
) {
1922 ram_addr_t candidate
, next
= RAM_ADDR_MAX
;
1924 /* Align blocks to start on a 'long' in the bitmap
1925 * which makes the bitmap sync'ing take the fast path.
1927 candidate
= block
->offset
+ block
->max_length
;
1928 candidate
= ROUND_UP(candidate
, BITS_PER_LONG
<< TARGET_PAGE_BITS
);
1930 /* Search for the closest following block
1933 RAMBLOCK_FOREACH(next_block
) {
1934 if (next_block
->offset
>= candidate
) {
1935 next
= MIN(next
, next_block
->offset
);
1939 /* If it fits remember our place and remember the size
1940 * of gap, but keep going so that we might find a smaller
1941 * gap to fill so avoiding fragmentation.
1943 if (next
- candidate
>= size
&& next
- candidate
< mingap
) {
1945 mingap
= next
- candidate
;
1948 trace_find_ram_offset_loop(size
, candidate
, offset
, next
, mingap
);
1951 if (offset
== RAM_ADDR_MAX
) {
1952 fprintf(stderr
, "Failed to find gap of requested size: %" PRIu64
"\n",
1957 trace_find_ram_offset(size
, offset
);
1962 static unsigned long last_ram_page(void)
1965 ram_addr_t last
= 0;
1968 RAMBLOCK_FOREACH(block
) {
1969 last
= MAX(last
, block
->offset
+ block
->max_length
);
1972 return last
>> TARGET_PAGE_BITS
;
1975 static void qemu_ram_setup_dump(void *addr
, ram_addr_t size
)
1979 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1980 if (!machine_dump_guest_core(current_machine
)) {
1981 ret
= qemu_madvise(addr
, size
, QEMU_MADV_DONTDUMP
);
1983 perror("qemu_madvise");
1984 fprintf(stderr
, "madvise doesn't support MADV_DONTDUMP, "
1985 "but dump_guest_core=off specified\n");
1990 const char *qemu_ram_get_idstr(RAMBlock
*rb
)
1995 void *qemu_ram_get_host_addr(RAMBlock
*rb
)
2000 ram_addr_t
qemu_ram_get_offset(RAMBlock
*rb
)
2005 ram_addr_t
qemu_ram_get_used_length(RAMBlock
*rb
)
2007 return rb
->used_length
;
2010 bool qemu_ram_is_shared(RAMBlock
*rb
)
2012 return rb
->flags
& RAM_SHARED
;
2015 /* Note: Only set at the start of postcopy */
2016 bool qemu_ram_is_uf_zeroable(RAMBlock
*rb
)
2018 return rb
->flags
& RAM_UF_ZEROPAGE
;
2021 void qemu_ram_set_uf_zeroable(RAMBlock
*rb
)
2023 rb
->flags
|= RAM_UF_ZEROPAGE
;
2026 bool qemu_ram_is_migratable(RAMBlock
*rb
)
2028 return rb
->flags
& RAM_MIGRATABLE
;
2031 void qemu_ram_set_migratable(RAMBlock
*rb
)
2033 rb
->flags
|= RAM_MIGRATABLE
;
2036 void qemu_ram_unset_migratable(RAMBlock
*rb
)
2038 rb
->flags
&= ~RAM_MIGRATABLE
;
2041 /* Called with iothread lock held. */
2042 void qemu_ram_set_idstr(RAMBlock
*new_block
, const char *name
, DeviceState
*dev
)
2047 assert(!new_block
->idstr
[0]);
2050 char *id
= qdev_get_dev_path(dev
);
2052 snprintf(new_block
->idstr
, sizeof(new_block
->idstr
), "%s/", id
);
2056 pstrcat(new_block
->idstr
, sizeof(new_block
->idstr
), name
);
2059 RAMBLOCK_FOREACH(block
) {
2060 if (block
!= new_block
&&
2061 !strcmp(block
->idstr
, new_block
->idstr
)) {
2062 fprintf(stderr
, "RAMBlock \"%s\" already registered, abort!\n",
2070 /* Called with iothread lock held. */
2071 void qemu_ram_unset_idstr(RAMBlock
*block
)
2073 /* FIXME: arch_init.c assumes that this is not called throughout
2074 * migration. Ignore the problem since hot-unplug during migration
2075 * does not work anyway.
2078 memset(block
->idstr
, 0, sizeof(block
->idstr
));
2082 size_t qemu_ram_pagesize(RAMBlock
*rb
)
2084 return rb
->page_size
;
2087 /* Returns the largest size of page in use */
2088 size_t qemu_ram_pagesize_largest(void)
2093 RAMBLOCK_FOREACH(block
) {
2094 largest
= MAX(largest
, qemu_ram_pagesize(block
));
2100 static int memory_try_enable_merging(void *addr
, size_t len
)
2102 if (!machine_mem_merge(current_machine
)) {
2103 /* disabled by the user */
2107 return qemu_madvise(addr
, len
, QEMU_MADV_MERGEABLE
);
2110 /* Only legal before guest might have detected the memory size: e.g. on
2111 * incoming migration, or right after reset.
2113 * As memory core doesn't know how is memory accessed, it is up to
2114 * resize callback to update device state and/or add assertions to detect
2115 * misuse, if necessary.
2117 int qemu_ram_resize(RAMBlock
*block
, ram_addr_t newsize
, Error
**errp
)
2121 newsize
= HOST_PAGE_ALIGN(newsize
);
2123 if (block
->used_length
== newsize
) {
2127 if (!(block
->flags
& RAM_RESIZEABLE
)) {
2128 error_setg_errno(errp
, EINVAL
,
2129 "Length mismatch: %s: 0x" RAM_ADDR_FMT
2130 " in != 0x" RAM_ADDR_FMT
, block
->idstr
,
2131 newsize
, block
->used_length
);
2135 if (block
->max_length
< newsize
) {
2136 error_setg_errno(errp
, EINVAL
,
2137 "Length too large: %s: 0x" RAM_ADDR_FMT
2138 " > 0x" RAM_ADDR_FMT
, block
->idstr
,
2139 newsize
, block
->max_length
);
2143 cpu_physical_memory_clear_dirty_range(block
->offset
, block
->used_length
);
2144 block
->used_length
= newsize
;
2145 cpu_physical_memory_set_dirty_range(block
->offset
, block
->used_length
,
2147 memory_region_set_size(block
->mr
, newsize
);
2148 if (block
->resized
) {
2149 block
->resized(block
->idstr
, newsize
, block
->host
);
2154 /* Called with ram_list.mutex held */
2155 static void dirty_memory_extend(ram_addr_t old_ram_size
,
2156 ram_addr_t new_ram_size
)
2158 ram_addr_t old_num_blocks
= DIV_ROUND_UP(old_ram_size
,
2159 DIRTY_MEMORY_BLOCK_SIZE
);
2160 ram_addr_t new_num_blocks
= DIV_ROUND_UP(new_ram_size
,
2161 DIRTY_MEMORY_BLOCK_SIZE
);
2164 /* Only need to extend if block count increased */
2165 if (new_num_blocks
<= old_num_blocks
) {
2169 for (i
= 0; i
< DIRTY_MEMORY_NUM
; i
++) {
2170 DirtyMemoryBlocks
*old_blocks
;
2171 DirtyMemoryBlocks
*new_blocks
;
2174 old_blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[i
]);
2175 new_blocks
= g_malloc(sizeof(*new_blocks
) +
2176 sizeof(new_blocks
->blocks
[0]) * new_num_blocks
);
2178 if (old_num_blocks
) {
2179 memcpy(new_blocks
->blocks
, old_blocks
->blocks
,
2180 old_num_blocks
* sizeof(old_blocks
->blocks
[0]));
2183 for (j
= old_num_blocks
; j
< new_num_blocks
; j
++) {
2184 new_blocks
->blocks
[j
] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE
);
2187 atomic_rcu_set(&ram_list
.dirty_memory
[i
], new_blocks
);
2190 g_free_rcu(old_blocks
, rcu
);
2195 static void ram_block_add(RAMBlock
*new_block
, Error
**errp
, bool shared
)
2198 RAMBlock
*last_block
= NULL
;
2199 ram_addr_t old_ram_size
, new_ram_size
;
2202 old_ram_size
= last_ram_page();
2204 qemu_mutex_lock_ramlist();
2205 new_block
->offset
= find_ram_offset(new_block
->max_length
);
2207 if (!new_block
->host
) {
2208 if (xen_enabled()) {
2209 xen_ram_alloc(new_block
->offset
, new_block
->max_length
,
2210 new_block
->mr
, &err
);
2212 error_propagate(errp
, err
);
2213 qemu_mutex_unlock_ramlist();
2217 new_block
->host
= phys_mem_alloc(new_block
->max_length
,
2218 &new_block
->mr
->align
, shared
);
2219 if (!new_block
->host
) {
2220 error_setg_errno(errp
, errno
,
2221 "cannot set up guest memory '%s'",
2222 memory_region_name(new_block
->mr
));
2223 qemu_mutex_unlock_ramlist();
2226 memory_try_enable_merging(new_block
->host
, new_block
->max_length
);
2230 new_ram_size
= MAX(old_ram_size
,
2231 (new_block
->offset
+ new_block
->max_length
) >> TARGET_PAGE_BITS
);
2232 if (new_ram_size
> old_ram_size
) {
2233 dirty_memory_extend(old_ram_size
, new_ram_size
);
2235 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
2236 * QLIST (which has an RCU-friendly variant) does not have insertion at
2237 * tail, so save the last element in last_block.
2239 RAMBLOCK_FOREACH(block
) {
2241 if (block
->max_length
< new_block
->max_length
) {
2246 QLIST_INSERT_BEFORE_RCU(block
, new_block
, next
);
2247 } else if (last_block
) {
2248 QLIST_INSERT_AFTER_RCU(last_block
, new_block
, next
);
2249 } else { /* list is empty */
2250 QLIST_INSERT_HEAD_RCU(&ram_list
.blocks
, new_block
, next
);
2252 ram_list
.mru_block
= NULL
;
2254 /* Write list before version */
2257 qemu_mutex_unlock_ramlist();
2259 cpu_physical_memory_set_dirty_range(new_block
->offset
,
2260 new_block
->used_length
,
2263 if (new_block
->host
) {
2264 qemu_ram_setup_dump(new_block
->host
, new_block
->max_length
);
2265 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_HUGEPAGE
);
2266 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
2267 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_DONTFORK
);
2268 ram_block_notify_add(new_block
->host
, new_block
->max_length
);
2273 RAMBlock
*qemu_ram_alloc_from_fd(ram_addr_t size
, MemoryRegion
*mr
,
2274 uint32_t ram_flags
, int fd
,
2277 RAMBlock
*new_block
;
2278 Error
*local_err
= NULL
;
2281 /* Just support these ram flags by now. */
2282 assert((ram_flags
& ~(RAM_SHARED
| RAM_PMEM
)) == 0);
2284 if (xen_enabled()) {
2285 error_setg(errp
, "-mem-path not supported with Xen");
2289 if (kvm_enabled() && !kvm_has_sync_mmu()) {
2291 "host lacks kvm mmu notifiers, -mem-path unsupported");
2295 if (phys_mem_alloc
!= qemu_anon_ram_alloc
) {
2297 * file_ram_alloc() needs to allocate just like
2298 * phys_mem_alloc, but we haven't bothered to provide
2302 "-mem-path not supported with this accelerator");
2306 size
= HOST_PAGE_ALIGN(size
);
2307 file_size
= get_file_size(fd
);
2308 if (file_size
> 0 && file_size
< size
) {
2309 error_setg(errp
, "backing store %s size 0x%" PRIx64
2310 " does not match 'size' option 0x" RAM_ADDR_FMT
,
2311 mem_path
, file_size
, size
);
2315 new_block
= g_malloc0(sizeof(*new_block
));
2317 new_block
->used_length
= size
;
2318 new_block
->max_length
= size
;
2319 new_block
->flags
= ram_flags
;
2320 new_block
->host
= file_ram_alloc(new_block
, size
, fd
, !file_size
, errp
);
2321 if (!new_block
->host
) {
2326 ram_block_add(new_block
, &local_err
, ram_flags
& RAM_SHARED
);
2329 error_propagate(errp
, local_err
);
2337 RAMBlock
*qemu_ram_alloc_from_file(ram_addr_t size
, MemoryRegion
*mr
,
2338 uint32_t ram_flags
, const char *mem_path
,
2345 fd
= file_ram_open(mem_path
, memory_region_name(mr
), &created
, errp
);
2350 block
= qemu_ram_alloc_from_fd(size
, mr
, ram_flags
, fd
, errp
);
2364 RAMBlock
*qemu_ram_alloc_internal(ram_addr_t size
, ram_addr_t max_size
,
2365 void (*resized
)(const char*,
2368 void *host
, bool resizeable
, bool share
,
2369 MemoryRegion
*mr
, Error
**errp
)
2371 RAMBlock
*new_block
;
2372 Error
*local_err
= NULL
;
2374 size
= HOST_PAGE_ALIGN(size
);
2375 max_size
= HOST_PAGE_ALIGN(max_size
);
2376 new_block
= g_malloc0(sizeof(*new_block
));
2378 new_block
->resized
= resized
;
2379 new_block
->used_length
= size
;
2380 new_block
->max_length
= max_size
;
2381 assert(max_size
>= size
);
2383 new_block
->page_size
= getpagesize();
2384 new_block
->host
= host
;
2386 new_block
->flags
|= RAM_PREALLOC
;
2389 new_block
->flags
|= RAM_RESIZEABLE
;
2391 ram_block_add(new_block
, &local_err
, share
);
2394 error_propagate(errp
, local_err
);
2400 RAMBlock
*qemu_ram_alloc_from_ptr(ram_addr_t size
, void *host
,
2401 MemoryRegion
*mr
, Error
**errp
)
2403 return qemu_ram_alloc_internal(size
, size
, NULL
, host
, false,
2407 RAMBlock
*qemu_ram_alloc(ram_addr_t size
, bool share
,
2408 MemoryRegion
*mr
, Error
**errp
)
2410 return qemu_ram_alloc_internal(size
, size
, NULL
, NULL
, false,
2414 RAMBlock
*qemu_ram_alloc_resizeable(ram_addr_t size
, ram_addr_t maxsz
,
2415 void (*resized
)(const char*,
2418 MemoryRegion
*mr
, Error
**errp
)
2420 return qemu_ram_alloc_internal(size
, maxsz
, resized
, NULL
, true,
2424 static void reclaim_ramblock(RAMBlock
*block
)
2426 if (block
->flags
& RAM_PREALLOC
) {
2428 } else if (xen_enabled()) {
2429 xen_invalidate_map_cache_entry(block
->host
);
2431 } else if (block
->fd
>= 0) {
2432 qemu_ram_munmap(block
->fd
, block
->host
, block
->max_length
);
2436 qemu_anon_ram_free(block
->host
, block
->max_length
);
2441 void qemu_ram_free(RAMBlock
*block
)
2448 ram_block_notify_remove(block
->host
, block
->max_length
);
2451 qemu_mutex_lock_ramlist();
2452 QLIST_REMOVE_RCU(block
, next
);
2453 ram_list
.mru_block
= NULL
;
2454 /* Write list before version */
2457 call_rcu(block
, reclaim_ramblock
, rcu
);
2458 qemu_mutex_unlock_ramlist();
2462 void qemu_ram_remap(ram_addr_t addr
, ram_addr_t length
)
2469 RAMBLOCK_FOREACH(block
) {
2470 offset
= addr
- block
->offset
;
2471 if (offset
< block
->max_length
) {
2472 vaddr
= ramblock_ptr(block
, offset
);
2473 if (block
->flags
& RAM_PREALLOC
) {
2475 } else if (xen_enabled()) {
2479 if (block
->fd
>= 0) {
2480 flags
|= (block
->flags
& RAM_SHARED
?
2481 MAP_SHARED
: MAP_PRIVATE
);
2482 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2483 flags
, block
->fd
, offset
);
2486 * Remap needs to match alloc. Accelerators that
2487 * set phys_mem_alloc never remap. If they did,
2488 * we'd need a remap hook here.
2490 assert(phys_mem_alloc
== qemu_anon_ram_alloc
);
2492 flags
|= MAP_PRIVATE
| MAP_ANONYMOUS
;
2493 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2496 if (area
!= vaddr
) {
2497 error_report("Could not remap addr: "
2498 RAM_ADDR_FMT
"@" RAM_ADDR_FMT
"",
2502 memory_try_enable_merging(vaddr
, length
);
2503 qemu_ram_setup_dump(vaddr
, length
);
2508 #endif /* !_WIN32 */
2510 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2511 * This should not be used for general purpose DMA. Use address_space_map
2512 * or address_space_rw instead. For local memory (e.g. video ram) that the
2513 * device owns, use memory_region_get_ram_ptr.
2515 * Called within RCU critical section.
2517 void *qemu_map_ram_ptr(RAMBlock
*ram_block
, ram_addr_t addr
)
2519 RAMBlock
*block
= ram_block
;
2521 if (block
== NULL
) {
2522 block
= qemu_get_ram_block(addr
);
2523 addr
-= block
->offset
;
2526 if (xen_enabled() && block
->host
== NULL
) {
2527 /* We need to check if the requested address is in the RAM
2528 * because we don't want to map the entire memory in QEMU.
2529 * In that case just map until the end of the page.
2531 if (block
->offset
== 0) {
2532 return xen_map_cache(addr
, 0, 0, false);
2535 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, false);
2537 return ramblock_ptr(block
, addr
);
2540 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2541 * but takes a size argument.
2543 * Called within RCU critical section.
2545 static void *qemu_ram_ptr_length(RAMBlock
*ram_block
, ram_addr_t addr
,
2546 hwaddr
*size
, bool lock
)
2548 RAMBlock
*block
= ram_block
;
2553 if (block
== NULL
) {
2554 block
= qemu_get_ram_block(addr
);
2555 addr
-= block
->offset
;
2557 *size
= MIN(*size
, block
->max_length
- addr
);
2559 if (xen_enabled() && block
->host
== NULL
) {
2560 /* We need to check if the requested address is in the RAM
2561 * because we don't want to map the entire memory in QEMU.
2562 * In that case just map the requested area.
2564 if (block
->offset
== 0) {
2565 return xen_map_cache(addr
, *size
, lock
, lock
);
2568 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, lock
);
2571 return ramblock_ptr(block
, addr
);
2574 /* Return the offset of a hostpointer within a ramblock */
2575 ram_addr_t
qemu_ram_block_host_offset(RAMBlock
*rb
, void *host
)
2577 ram_addr_t res
= (uint8_t *)host
- (uint8_t *)rb
->host
;
2578 assert((uintptr_t)host
>= (uintptr_t)rb
->host
);
2579 assert(res
< rb
->max_length
);
2585 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2588 * ptr: Host pointer to look up
2589 * round_offset: If true round the result offset down to a page boundary
2590 * *ram_addr: set to result ram_addr
2591 * *offset: set to result offset within the RAMBlock
2593 * Returns: RAMBlock (or NULL if not found)
2595 * By the time this function returns, the returned pointer is not protected
2596 * by RCU anymore. If the caller is not within an RCU critical section and
2597 * does not hold the iothread lock, it must have other means of protecting the
2598 * pointer, such as a reference to the region that includes the incoming
2601 RAMBlock
*qemu_ram_block_from_host(void *ptr
, bool round_offset
,
2605 uint8_t *host
= ptr
;
2607 if (xen_enabled()) {
2608 ram_addr_t ram_addr
;
2610 ram_addr
= xen_ram_addr_from_mapcache(ptr
);
2611 block
= qemu_get_ram_block(ram_addr
);
2613 *offset
= ram_addr
- block
->offset
;
2620 block
= atomic_rcu_read(&ram_list
.mru_block
);
2621 if (block
&& block
->host
&& host
- block
->host
< block
->max_length
) {
2625 RAMBLOCK_FOREACH(block
) {
2626 /* This case append when the block is not mapped. */
2627 if (block
->host
== NULL
) {
2630 if (host
- block
->host
< block
->max_length
) {
2639 *offset
= (host
- block
->host
);
2641 *offset
&= TARGET_PAGE_MASK
;
2648 * Finds the named RAMBlock
2650 * name: The name of RAMBlock to find
2652 * Returns: RAMBlock (or NULL if not found)
2654 RAMBlock
*qemu_ram_block_by_name(const char *name
)
2658 RAMBLOCK_FOREACH(block
) {
2659 if (!strcmp(name
, block
->idstr
)) {
2667 /* Some of the softmmu routines need to translate from a host pointer
2668 (typically a TLB entry) back to a ram offset. */
2669 ram_addr_t
qemu_ram_addr_from_host(void *ptr
)
2674 block
= qemu_ram_block_from_host(ptr
, false, &offset
);
2676 return RAM_ADDR_INVALID
;
2679 return block
->offset
+ offset
;
2682 /* Called within RCU critical section. */
2683 void memory_notdirty_write_prepare(NotDirtyInfo
*ndi
,
2686 ram_addr_t ram_addr
,
2690 ndi
->ram_addr
= ram_addr
;
2691 ndi
->mem_vaddr
= mem_vaddr
;
2695 assert(tcg_enabled());
2696 if (!cpu_physical_memory_get_dirty_flag(ram_addr
, DIRTY_MEMORY_CODE
)) {
2697 ndi
->pages
= page_collection_lock(ram_addr
, ram_addr
+ size
);
2698 tb_invalidate_phys_page_fast(ndi
->pages
, ram_addr
, size
);
2702 /* Called within RCU critical section. */
2703 void memory_notdirty_write_complete(NotDirtyInfo
*ndi
)
2706 assert(tcg_enabled());
2707 page_collection_unlock(ndi
->pages
);
2711 /* Set both VGA and migration bits for simplicity and to remove
2712 * the notdirty callback faster.
2714 cpu_physical_memory_set_dirty_range(ndi
->ram_addr
, ndi
->size
,
2715 DIRTY_CLIENTS_NOCODE
);
2716 /* we remove the notdirty callback only if the code has been
2718 if (!cpu_physical_memory_is_clean(ndi
->ram_addr
)) {
2719 tlb_set_dirty(ndi
->cpu
, ndi
->mem_vaddr
);
2723 /* Called within RCU critical section. */
2724 static void notdirty_mem_write(void *opaque
, hwaddr ram_addr
,
2725 uint64_t val
, unsigned size
)
2729 memory_notdirty_write_prepare(&ndi
, current_cpu
, current_cpu
->mem_io_vaddr
,
2732 stn_p(qemu_map_ram_ptr(NULL
, ram_addr
), size
, val
);
2733 memory_notdirty_write_complete(&ndi
);
2736 static bool notdirty_mem_accepts(void *opaque
, hwaddr addr
,
2737 unsigned size
, bool is_write
,
2743 static const MemoryRegionOps notdirty_mem_ops
= {
2744 .write
= notdirty_mem_write
,
2745 .valid
.accepts
= notdirty_mem_accepts
,
2746 .endianness
= DEVICE_NATIVE_ENDIAN
,
2748 .min_access_size
= 1,
2749 .max_access_size
= 8,
2753 .min_access_size
= 1,
2754 .max_access_size
= 8,
2759 /* Generate a debug exception if a watchpoint has been hit. */
2760 static void check_watchpoint(int offset
, int len
, MemTxAttrs attrs
, int flags
)
2762 CPUState
*cpu
= current_cpu
;
2763 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
2767 assert(tcg_enabled());
2768 if (cpu
->watchpoint_hit
) {
2769 /* We re-entered the check after replacing the TB. Now raise
2770 * the debug interrupt so that is will trigger after the
2771 * current instruction. */
2772 cpu_interrupt(cpu
, CPU_INTERRUPT_DEBUG
);
2775 vaddr
= (cpu
->mem_io_vaddr
& TARGET_PAGE_MASK
) + offset
;
2776 vaddr
= cc
->adjust_watchpoint_address(cpu
, vaddr
, len
);
2777 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
2778 if (cpu_watchpoint_address_matches(wp
, vaddr
, len
)
2779 && (wp
->flags
& flags
)) {
2780 if (flags
== BP_MEM_READ
) {
2781 wp
->flags
|= BP_WATCHPOINT_HIT_READ
;
2783 wp
->flags
|= BP_WATCHPOINT_HIT_WRITE
;
2785 wp
->hitaddr
= vaddr
;
2786 wp
->hitattrs
= attrs
;
2787 if (!cpu
->watchpoint_hit
) {
2788 if (wp
->flags
& BP_CPU
&&
2789 !cc
->debug_check_watchpoint(cpu
, wp
)) {
2790 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2793 cpu
->watchpoint_hit
= wp
;
2796 tb_check_watchpoint(cpu
);
2797 if (wp
->flags
& BP_STOP_BEFORE_ACCESS
) {
2798 cpu
->exception_index
= EXCP_DEBUG
;
2802 /* Force execution of one insn next time. */
2803 cpu
->cflags_next_tb
= 1 | curr_cflags();
2805 cpu_loop_exit_noexc(cpu
);
2809 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2814 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2815 so these check for a hit then pass through to the normal out-of-line
2817 static MemTxResult
watch_mem_read(void *opaque
, hwaddr addr
, uint64_t *pdata
,
2818 unsigned size
, MemTxAttrs attrs
)
2822 int asidx
= cpu_asidx_from_attrs(current_cpu
, attrs
);
2823 AddressSpace
*as
= current_cpu
->cpu_ases
[asidx
].as
;
2825 check_watchpoint(addr
& ~TARGET_PAGE_MASK
, size
, attrs
, BP_MEM_READ
);
2828 data
= address_space_ldub(as
, addr
, attrs
, &res
);
2831 data
= address_space_lduw(as
, addr
, attrs
, &res
);
2834 data
= address_space_ldl(as
, addr
, attrs
, &res
);
2837 data
= address_space_ldq(as
, addr
, attrs
, &res
);
2845 static MemTxResult
watch_mem_write(void *opaque
, hwaddr addr
,
2846 uint64_t val
, unsigned size
,
2850 int asidx
= cpu_asidx_from_attrs(current_cpu
, attrs
);
2851 AddressSpace
*as
= current_cpu
->cpu_ases
[asidx
].as
;
2853 check_watchpoint(addr
& ~TARGET_PAGE_MASK
, size
, attrs
, BP_MEM_WRITE
);
2856 address_space_stb(as
, addr
, val
, attrs
, &res
);
2859 address_space_stw(as
, addr
, val
, attrs
, &res
);
2862 address_space_stl(as
, addr
, val
, attrs
, &res
);
2865 address_space_stq(as
, addr
, val
, attrs
, &res
);
2872 static const MemoryRegionOps watch_mem_ops
= {
2873 .read_with_attrs
= watch_mem_read
,
2874 .write_with_attrs
= watch_mem_write
,
2875 .endianness
= DEVICE_NATIVE_ENDIAN
,
2877 .min_access_size
= 1,
2878 .max_access_size
= 8,
2882 .min_access_size
= 1,
2883 .max_access_size
= 8,
2888 static MemTxResult
flatview_read(FlatView
*fv
, hwaddr addr
,
2889 MemTxAttrs attrs
, uint8_t *buf
, hwaddr len
);
2890 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
2891 const uint8_t *buf
, hwaddr len
);
2892 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, hwaddr len
,
2893 bool is_write
, MemTxAttrs attrs
);
2895 static MemTxResult
subpage_read(void *opaque
, hwaddr addr
, uint64_t *data
,
2896 unsigned len
, MemTxAttrs attrs
)
2898 subpage_t
*subpage
= opaque
;
2902 #if defined(DEBUG_SUBPAGE)
2903 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
"\n", __func__
,
2904 subpage
, len
, addr
);
2906 res
= flatview_read(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2910 *data
= ldn_p(buf
, len
);
2914 static MemTxResult
subpage_write(void *opaque
, hwaddr addr
,
2915 uint64_t value
, unsigned len
, MemTxAttrs attrs
)
2917 subpage_t
*subpage
= opaque
;
2920 #if defined(DEBUG_SUBPAGE)
2921 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2922 " value %"PRIx64
"\n",
2923 __func__
, subpage
, len
, addr
, value
);
2925 stn_p(buf
, len
, value
);
2926 return flatview_write(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2929 static bool subpage_accepts(void *opaque
, hwaddr addr
,
2930 unsigned len
, bool is_write
,
2933 subpage_t
*subpage
= opaque
;
2934 #if defined(DEBUG_SUBPAGE)
2935 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx
"\n",
2936 __func__
, subpage
, is_write
? 'w' : 'r', len
, addr
);
2939 return flatview_access_valid(subpage
->fv
, addr
+ subpage
->base
,
2940 len
, is_write
, attrs
);
2943 static const MemoryRegionOps subpage_ops
= {
2944 .read_with_attrs
= subpage_read
,
2945 .write_with_attrs
= subpage_write
,
2946 .impl
.min_access_size
= 1,
2947 .impl
.max_access_size
= 8,
2948 .valid
.min_access_size
= 1,
2949 .valid
.max_access_size
= 8,
2950 .valid
.accepts
= subpage_accepts
,
2951 .endianness
= DEVICE_NATIVE_ENDIAN
,
2954 static int subpage_register (subpage_t
*mmio
, uint32_t start
, uint32_t end
,
2959 if (start
>= TARGET_PAGE_SIZE
|| end
>= TARGET_PAGE_SIZE
)
2961 idx
= SUBPAGE_IDX(start
);
2962 eidx
= SUBPAGE_IDX(end
);
2963 #if defined(DEBUG_SUBPAGE)
2964 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2965 __func__
, mmio
, start
, end
, idx
, eidx
, section
);
2967 for (; idx
<= eidx
; idx
++) {
2968 mmio
->sub_section
[idx
] = section
;
2974 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
)
2978 mmio
= g_malloc0(sizeof(subpage_t
) + TARGET_PAGE_SIZE
* sizeof(uint16_t));
2981 memory_region_init_io(&mmio
->iomem
, NULL
, &subpage_ops
, mmio
,
2982 NULL
, TARGET_PAGE_SIZE
);
2983 mmio
->iomem
.subpage
= true;
2984 #if defined(DEBUG_SUBPAGE)
2985 printf("%s: %p base " TARGET_FMT_plx
" len %08x\n", __func__
,
2986 mmio
, base
, TARGET_PAGE_SIZE
);
2988 subpage_register(mmio
, 0, TARGET_PAGE_SIZE
-1, PHYS_SECTION_UNASSIGNED
);
2993 static uint16_t dummy_section(PhysPageMap
*map
, FlatView
*fv
, MemoryRegion
*mr
)
2996 MemoryRegionSection section
= {
2999 .offset_within_address_space
= 0,
3000 .offset_within_region
= 0,
3001 .size
= int128_2_64(),
3004 return phys_section_add(map
, §ion
);
3007 static void readonly_mem_write(void *opaque
, hwaddr addr
,
3008 uint64_t val
, unsigned size
)
3010 /* Ignore any write to ROM. */
3013 static bool readonly_mem_accepts(void *opaque
, hwaddr addr
,
3014 unsigned size
, bool is_write
,
3020 /* This will only be used for writes, because reads are special cased
3021 * to directly access the underlying host ram.
3023 static const MemoryRegionOps readonly_mem_ops
= {
3024 .write
= readonly_mem_write
,
3025 .valid
.accepts
= readonly_mem_accepts
,
3026 .endianness
= DEVICE_NATIVE_ENDIAN
,
3028 .min_access_size
= 1,
3029 .max_access_size
= 8,
3033 .min_access_size
= 1,
3034 .max_access_size
= 8,
3039 MemoryRegionSection
*iotlb_to_section(CPUState
*cpu
,
3040 hwaddr index
, MemTxAttrs attrs
)
3042 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
3043 CPUAddressSpace
*cpuas
= &cpu
->cpu_ases
[asidx
];
3044 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpuas
->memory_dispatch
);
3045 MemoryRegionSection
*sections
= d
->map
.sections
;
3047 return §ions
[index
& ~TARGET_PAGE_MASK
];
3050 static void io_mem_init(void)
3052 memory_region_init_io(&io_mem_rom
, NULL
, &readonly_mem_ops
,
3053 NULL
, NULL
, UINT64_MAX
);
3054 memory_region_init_io(&io_mem_unassigned
, NULL
, &unassigned_mem_ops
, NULL
,
3057 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
3058 * which can be called without the iothread mutex.
3060 memory_region_init_io(&io_mem_notdirty
, NULL
, ¬dirty_mem_ops
, NULL
,
3062 memory_region_clear_global_locking(&io_mem_notdirty
);
3064 memory_region_init_io(&io_mem_watch
, NULL
, &watch_mem_ops
, NULL
,
3068 AddressSpaceDispatch
*address_space_dispatch_new(FlatView
*fv
)
3070 AddressSpaceDispatch
*d
= g_new0(AddressSpaceDispatch
, 1);
3073 n
= dummy_section(&d
->map
, fv
, &io_mem_unassigned
);
3074 assert(n
== PHYS_SECTION_UNASSIGNED
);
3075 n
= dummy_section(&d
->map
, fv
, &io_mem_notdirty
);
3076 assert(n
== PHYS_SECTION_NOTDIRTY
);
3077 n
= dummy_section(&d
->map
, fv
, &io_mem_rom
);
3078 assert(n
== PHYS_SECTION_ROM
);
3079 n
= dummy_section(&d
->map
, fv
, &io_mem_watch
);
3080 assert(n
== PHYS_SECTION_WATCH
);
3082 d
->phys_map
= (PhysPageEntry
) { .ptr
= PHYS_MAP_NODE_NIL
, .skip
= 1 };
3087 void address_space_dispatch_free(AddressSpaceDispatch
*d
)
3089 phys_sections_free(&d
->map
);
3093 static void tcg_commit(MemoryListener
*listener
)
3095 CPUAddressSpace
*cpuas
;
3096 AddressSpaceDispatch
*d
;
3098 assert(tcg_enabled());
3099 /* since each CPU stores ram addresses in its TLB cache, we must
3100 reset the modified entries */
3101 cpuas
= container_of(listener
, CPUAddressSpace
, tcg_as_listener
);
3102 cpu_reloading_memory_map();
3103 /* The CPU and TLB are protected by the iothread lock.
3104 * We reload the dispatch pointer now because cpu_reloading_memory_map()
3105 * may have split the RCU critical section.
3107 d
= address_space_to_dispatch(cpuas
->as
);
3108 atomic_rcu_set(&cpuas
->memory_dispatch
, d
);
3109 tlb_flush(cpuas
->cpu
);
3112 static void memory_map_init(void)
3114 system_memory
= g_malloc(sizeof(*system_memory
));
3116 memory_region_init(system_memory
, NULL
, "system", UINT64_MAX
);
3117 address_space_init(&address_space_memory
, system_memory
, "memory");
3119 system_io
= g_malloc(sizeof(*system_io
));
3120 memory_region_init_io(system_io
, NULL
, &unassigned_io_ops
, NULL
, "io",
3122 address_space_init(&address_space_io
, system_io
, "I/O");
3125 MemoryRegion
*get_system_memory(void)
3127 return system_memory
;
3130 MemoryRegion
*get_system_io(void)
3135 #endif /* !defined(CONFIG_USER_ONLY) */
3137 /* physical memory access (slow version, mainly for debug) */
3138 #if defined(CONFIG_USER_ONLY)
3139 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
3140 uint8_t *buf
, target_ulong len
, int is_write
)
3143 target_ulong l
, page
;
3147 page
= addr
& TARGET_PAGE_MASK
;
3148 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
3151 flags
= page_get_flags(page
);
3152 if (!(flags
& PAGE_VALID
))
3155 if (!(flags
& PAGE_WRITE
))
3157 /* XXX: this code should not depend on lock_user */
3158 if (!(p
= lock_user(VERIFY_WRITE
, addr
, l
, 0)))
3161 unlock_user(p
, addr
, l
);
3163 if (!(flags
& PAGE_READ
))
3165 /* XXX: this code should not depend on lock_user */
3166 if (!(p
= lock_user(VERIFY_READ
, addr
, l
, 1)))
3169 unlock_user(p
, addr
, 0);
3180 static void invalidate_and_set_dirty(MemoryRegion
*mr
, hwaddr addr
,
3183 uint8_t dirty_log_mask
= memory_region_get_dirty_log_mask(mr
);
3184 addr
+= memory_region_get_ram_addr(mr
);
3186 /* No early return if dirty_log_mask is or becomes 0, because
3187 * cpu_physical_memory_set_dirty_range will still call
3188 * xen_modified_memory.
3190 if (dirty_log_mask
) {
3192 cpu_physical_memory_range_includes_clean(addr
, length
, dirty_log_mask
);
3194 if (dirty_log_mask
& (1 << DIRTY_MEMORY_CODE
)) {
3195 assert(tcg_enabled());
3196 tb_invalidate_phys_range(addr
, addr
+ length
);
3197 dirty_log_mask
&= ~(1 << DIRTY_MEMORY_CODE
);
3199 cpu_physical_memory_set_dirty_range(addr
, length
, dirty_log_mask
);
3202 void memory_region_flush_rom_device(MemoryRegion
*mr
, hwaddr addr
, hwaddr size
)
3205 * In principle this function would work on other memory region types too,
3206 * but the ROM device use case is the only one where this operation is
3207 * necessary. Other memory regions should use the
3208 * address_space_read/write() APIs.
3210 assert(memory_region_is_romd(mr
));
3212 invalidate_and_set_dirty(mr
, addr
, size
);
3215 static int memory_access_size(MemoryRegion
*mr
, unsigned l
, hwaddr addr
)
3217 unsigned access_size_max
= mr
->ops
->valid
.max_access_size
;
3219 /* Regions are assumed to support 1-4 byte accesses unless
3220 otherwise specified. */
3221 if (access_size_max
== 0) {
3222 access_size_max
= 4;
3225 /* Bound the maximum access by the alignment of the address. */
3226 if (!mr
->ops
->impl
.unaligned
) {
3227 unsigned align_size_max
= addr
& -addr
;
3228 if (align_size_max
!= 0 && align_size_max
< access_size_max
) {
3229 access_size_max
= align_size_max
;
3233 /* Don't attempt accesses larger than the maximum. */
3234 if (l
> access_size_max
) {
3235 l
= access_size_max
;
3242 static bool prepare_mmio_access(MemoryRegion
*mr
)
3244 bool unlocked
= !qemu_mutex_iothread_locked();
3245 bool release_lock
= false;
3247 if (unlocked
&& mr
->global_locking
) {
3248 qemu_mutex_lock_iothread();
3250 release_lock
= true;
3252 if (mr
->flush_coalesced_mmio
) {
3254 qemu_mutex_lock_iothread();
3256 qemu_flush_coalesced_mmio_buffer();
3258 qemu_mutex_unlock_iothread();
3262 return release_lock
;
3265 /* Called within RCU critical section. */
3266 static MemTxResult
flatview_write_continue(FlatView
*fv
, hwaddr addr
,
3269 hwaddr len
, hwaddr addr1
,
3270 hwaddr l
, MemoryRegion
*mr
)
3274 MemTxResult result
= MEMTX_OK
;
3275 bool release_lock
= false;
3278 if (!memory_access_is_direct(mr
, true)) {
3279 release_lock
|= prepare_mmio_access(mr
);
3280 l
= memory_access_size(mr
, l
, addr1
);
3281 /* XXX: could force current_cpu to NULL to avoid
3283 val
= ldn_p(buf
, l
);
3284 result
|= memory_region_dispatch_write(mr
, addr1
, val
, l
, attrs
);
3287 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
3288 memcpy(ptr
, buf
, l
);
3289 invalidate_and_set_dirty(mr
, addr1
, l
);
3293 qemu_mutex_unlock_iothread();
3294 release_lock
= false;
3306 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true, attrs
);
3312 /* Called from RCU critical section. */
3313 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
3314 const uint8_t *buf
, hwaddr len
)
3319 MemTxResult result
= MEMTX_OK
;
3322 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true, attrs
);
3323 result
= flatview_write_continue(fv
, addr
, attrs
, buf
, len
,
3329 /* Called within RCU critical section. */
3330 MemTxResult
flatview_read_continue(FlatView
*fv
, hwaddr addr
,
3331 MemTxAttrs attrs
, uint8_t *buf
,
3332 hwaddr len
, hwaddr addr1
, hwaddr l
,
3337 MemTxResult result
= MEMTX_OK
;
3338 bool release_lock
= false;
3341 if (!memory_access_is_direct(mr
, false)) {
3343 release_lock
|= prepare_mmio_access(mr
);
3344 l
= memory_access_size(mr
, l
, addr1
);
3345 result
|= memory_region_dispatch_read(mr
, addr1
, &val
, l
, attrs
);
3349 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
3350 memcpy(buf
, ptr
, l
);
3354 qemu_mutex_unlock_iothread();
3355 release_lock
= false;
3367 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false, attrs
);
3373 /* Called from RCU critical section. */
3374 static MemTxResult
flatview_read(FlatView
*fv
, hwaddr addr
,
3375 MemTxAttrs attrs
, uint8_t *buf
, hwaddr len
)
3382 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false, attrs
);
3383 return flatview_read_continue(fv
, addr
, attrs
, buf
, len
,
3387 MemTxResult
address_space_read_full(AddressSpace
*as
, hwaddr addr
,
3388 MemTxAttrs attrs
, uint8_t *buf
, hwaddr len
)
3390 MemTxResult result
= MEMTX_OK
;
3395 fv
= address_space_to_flatview(as
);
3396 result
= flatview_read(fv
, addr
, attrs
, buf
, len
);
3403 MemTxResult
address_space_write(AddressSpace
*as
, hwaddr addr
,
3405 const uint8_t *buf
, hwaddr len
)
3407 MemTxResult result
= MEMTX_OK
;
3412 fv
= address_space_to_flatview(as
);
3413 result
= flatview_write(fv
, addr
, attrs
, buf
, len
);
3420 MemTxResult
address_space_rw(AddressSpace
*as
, hwaddr addr
, MemTxAttrs attrs
,
3421 uint8_t *buf
, hwaddr len
, bool is_write
)
3424 return address_space_write(as
, addr
, attrs
, buf
, len
);
3426 return address_space_read_full(as
, addr
, attrs
, buf
, len
);
3430 void cpu_physical_memory_rw(hwaddr addr
, uint8_t *buf
,
3431 hwaddr len
, int is_write
)
3433 address_space_rw(&address_space_memory
, addr
, MEMTXATTRS_UNSPECIFIED
,
3434 buf
, len
, is_write
);
3437 enum write_rom_type
{
3442 static inline MemTxResult
address_space_write_rom_internal(AddressSpace
*as
,
3447 enum write_rom_type type
)
3457 mr
= address_space_translate(as
, addr
, &addr1
, &l
, true, attrs
);
3459 if (!(memory_region_is_ram(mr
) ||
3460 memory_region_is_romd(mr
))) {
3461 l
= memory_access_size(mr
, l
, addr1
);
3464 ptr
= qemu_map_ram_ptr(mr
->ram_block
, addr1
);
3467 memcpy(ptr
, buf
, l
);
3468 invalidate_and_set_dirty(mr
, addr1
, l
);
3471 flush_icache_range((uintptr_t)ptr
, (uintptr_t)ptr
+ l
);
3483 /* used for ROM loading : can write in RAM and ROM */
3484 MemTxResult
address_space_write_rom(AddressSpace
*as
, hwaddr addr
,
3486 const uint8_t *buf
, hwaddr len
)
3488 return address_space_write_rom_internal(as
, addr
, attrs
,
3489 buf
, len
, WRITE_DATA
);
3492 void cpu_flush_icache_range(hwaddr start
, hwaddr len
)
3495 * This function should do the same thing as an icache flush that was
3496 * triggered from within the guest. For TCG we are always cache coherent,
3497 * so there is no need to flush anything. For KVM / Xen we need to flush
3498 * the host's instruction cache at least.
3500 if (tcg_enabled()) {
3504 address_space_write_rom_internal(&address_space_memory
,
3505 start
, MEMTXATTRS_UNSPECIFIED
,
3506 NULL
, len
, FLUSH_CACHE
);
3517 static BounceBuffer bounce
;
3519 typedef struct MapClient
{
3521 QLIST_ENTRY(MapClient
) link
;
3524 QemuMutex map_client_list_lock
;
3525 static QLIST_HEAD(, MapClient
) map_client_list
3526 = QLIST_HEAD_INITIALIZER(map_client_list
);
3528 static void cpu_unregister_map_client_do(MapClient
*client
)
3530 QLIST_REMOVE(client
, link
);
3534 static void cpu_notify_map_clients_locked(void)
3538 while (!QLIST_EMPTY(&map_client_list
)) {
3539 client
= QLIST_FIRST(&map_client_list
);
3540 qemu_bh_schedule(client
->bh
);
3541 cpu_unregister_map_client_do(client
);
3545 void cpu_register_map_client(QEMUBH
*bh
)
3547 MapClient
*client
= g_malloc(sizeof(*client
));
3549 qemu_mutex_lock(&map_client_list_lock
);
3551 QLIST_INSERT_HEAD(&map_client_list
, client
, link
);
3552 if (!atomic_read(&bounce
.in_use
)) {
3553 cpu_notify_map_clients_locked();
3555 qemu_mutex_unlock(&map_client_list_lock
);
3558 void cpu_exec_init_all(void)
3560 qemu_mutex_init(&ram_list
.mutex
);
3561 /* The data structures we set up here depend on knowing the page size,
3562 * so no more changes can be made after this point.
3563 * In an ideal world, nothing we did before we had finished the
3564 * machine setup would care about the target page size, and we could
3565 * do this much later, rather than requiring board models to state
3566 * up front what their requirements are.
3568 finalize_target_page_bits();
3571 qemu_mutex_init(&map_client_list_lock
);
3574 void cpu_unregister_map_client(QEMUBH
*bh
)
3578 qemu_mutex_lock(&map_client_list_lock
);
3579 QLIST_FOREACH(client
, &map_client_list
, link
) {
3580 if (client
->bh
== bh
) {
3581 cpu_unregister_map_client_do(client
);
3585 qemu_mutex_unlock(&map_client_list_lock
);
3588 static void cpu_notify_map_clients(void)
3590 qemu_mutex_lock(&map_client_list_lock
);
3591 cpu_notify_map_clients_locked();
3592 qemu_mutex_unlock(&map_client_list_lock
);
3595 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, hwaddr len
,
3596 bool is_write
, MemTxAttrs attrs
)
3603 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
, attrs
);
3604 if (!memory_access_is_direct(mr
, is_write
)) {
3605 l
= memory_access_size(mr
, l
, addr
);
3606 if (!memory_region_access_valid(mr
, xlat
, l
, is_write
, attrs
)) {
3617 bool address_space_access_valid(AddressSpace
*as
, hwaddr addr
,
3618 hwaddr len
, bool is_write
,
3625 fv
= address_space_to_flatview(as
);
3626 result
= flatview_access_valid(fv
, addr
, len
, is_write
, attrs
);
3632 flatview_extend_translation(FlatView
*fv
, hwaddr addr
,
3634 MemoryRegion
*mr
, hwaddr base
, hwaddr len
,
3635 bool is_write
, MemTxAttrs attrs
)
3639 MemoryRegion
*this_mr
;
3645 if (target_len
== 0) {
3650 this_mr
= flatview_translate(fv
, addr
, &xlat
,
3651 &len
, is_write
, attrs
);
3652 if (this_mr
!= mr
|| xlat
!= base
+ done
) {
3658 /* Map a physical memory region into a host virtual address.
3659 * May map a subset of the requested range, given by and returned in *plen.
3660 * May return NULL if resources needed to perform the mapping are exhausted.
3661 * Use only for reads OR writes - not for read-modify-write operations.
3662 * Use cpu_register_map_client() to know when retrying the map operation is
3663 * likely to succeed.
3665 void *address_space_map(AddressSpace
*as
,
3683 fv
= address_space_to_flatview(as
);
3684 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
, attrs
);
3686 if (!memory_access_is_direct(mr
, is_write
)) {
3687 if (atomic_xchg(&bounce
.in_use
, true)) {
3691 /* Avoid unbounded allocations */
3692 l
= MIN(l
, TARGET_PAGE_SIZE
);
3693 bounce
.buffer
= qemu_memalign(TARGET_PAGE_SIZE
, l
);
3697 memory_region_ref(mr
);
3700 flatview_read(fv
, addr
, MEMTXATTRS_UNSPECIFIED
,
3706 return bounce
.buffer
;
3710 memory_region_ref(mr
);
3711 *plen
= flatview_extend_translation(fv
, addr
, len
, mr
, xlat
,
3712 l
, is_write
, attrs
);
3713 ptr
= qemu_ram_ptr_length(mr
->ram_block
, xlat
, plen
, true);
3719 /* Unmaps a memory region previously mapped by address_space_map().
3720 * Will also mark the memory as dirty if is_write == 1. access_len gives
3721 * the amount of memory that was actually read or written by the caller.
3723 void address_space_unmap(AddressSpace
*as
, void *buffer
, hwaddr len
,
3724 int is_write
, hwaddr access_len
)
3726 if (buffer
!= bounce
.buffer
) {
3730 mr
= memory_region_from_host(buffer
, &addr1
);
3733 invalidate_and_set_dirty(mr
, addr1
, access_len
);
3735 if (xen_enabled()) {
3736 xen_invalidate_map_cache_entry(buffer
);
3738 memory_region_unref(mr
);
3742 address_space_write(as
, bounce
.addr
, MEMTXATTRS_UNSPECIFIED
,
3743 bounce
.buffer
, access_len
);
3745 qemu_vfree(bounce
.buffer
);
3746 bounce
.buffer
= NULL
;
3747 memory_region_unref(bounce
.mr
);
3748 atomic_mb_set(&bounce
.in_use
, false);
3749 cpu_notify_map_clients();
3752 void *cpu_physical_memory_map(hwaddr addr
,
3756 return address_space_map(&address_space_memory
, addr
, plen
, is_write
,
3757 MEMTXATTRS_UNSPECIFIED
);
3760 void cpu_physical_memory_unmap(void *buffer
, hwaddr len
,
3761 int is_write
, hwaddr access_len
)
3763 return address_space_unmap(&address_space_memory
, buffer
, len
, is_write
, access_len
);
3766 #define ARG1_DECL AddressSpace *as
3769 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3770 #define RCU_READ_LOCK(...) rcu_read_lock()
3771 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3772 #include "memory_ldst.inc.c"
3774 int64_t address_space_cache_init(MemoryRegionCache
*cache
,
3780 AddressSpaceDispatch
*d
;
3787 cache
->fv
= address_space_get_flatview(as
);
3788 d
= flatview_to_dispatch(cache
->fv
);
3789 cache
->mrs
= *address_space_translate_internal(d
, addr
, &cache
->xlat
, &l
, true);
3792 memory_region_ref(mr
);
3793 if (memory_access_is_direct(mr
, is_write
)) {
3794 /* We don't care about the memory attributes here as we're only
3795 * doing this if we found actual RAM, which behaves the same
3796 * regardless of attributes; so UNSPECIFIED is fine.
3798 l
= flatview_extend_translation(cache
->fv
, addr
, len
, mr
,
3799 cache
->xlat
, l
, is_write
,
3800 MEMTXATTRS_UNSPECIFIED
);
3801 cache
->ptr
= qemu_ram_ptr_length(mr
->ram_block
, cache
->xlat
, &l
, true);
3807 cache
->is_write
= is_write
;
3811 void address_space_cache_invalidate(MemoryRegionCache
*cache
,
3815 assert(cache
->is_write
);
3816 if (likely(cache
->ptr
)) {
3817 invalidate_and_set_dirty(cache
->mrs
.mr
, addr
+ cache
->xlat
, access_len
);
3821 void address_space_cache_destroy(MemoryRegionCache
*cache
)
3823 if (!cache
->mrs
.mr
) {
3827 if (xen_enabled()) {
3828 xen_invalidate_map_cache_entry(cache
->ptr
);
3830 memory_region_unref(cache
->mrs
.mr
);
3831 flatview_unref(cache
->fv
);
3832 cache
->mrs
.mr
= NULL
;
3836 /* Called from RCU critical section. This function has the same
3837 * semantics as address_space_translate, but it only works on a
3838 * predefined range of a MemoryRegion that was mapped with
3839 * address_space_cache_init.
3841 static inline MemoryRegion
*address_space_translate_cached(
3842 MemoryRegionCache
*cache
, hwaddr addr
, hwaddr
*xlat
,
3843 hwaddr
*plen
, bool is_write
, MemTxAttrs attrs
)
3845 MemoryRegionSection section
;
3847 IOMMUMemoryRegion
*iommu_mr
;
3848 AddressSpace
*target_as
;
3850 assert(!cache
->ptr
);
3851 *xlat
= addr
+ cache
->xlat
;
3854 iommu_mr
= memory_region_get_iommu(mr
);
3860 section
= address_space_translate_iommu(iommu_mr
, xlat
, plen
,
3861 NULL
, is_write
, true,
3866 /* Called from RCU critical section. address_space_read_cached uses this
3867 * out of line function when the target is an MMIO or IOMMU region.
3870 address_space_read_cached_slow(MemoryRegionCache
*cache
, hwaddr addr
,
3871 void *buf
, hwaddr len
)
3877 mr
= address_space_translate_cached(cache
, addr
, &addr1
, &l
, false,
3878 MEMTXATTRS_UNSPECIFIED
);
3879 flatview_read_continue(cache
->fv
,
3880 addr
, MEMTXATTRS_UNSPECIFIED
, buf
, len
,
3884 /* Called from RCU critical section. address_space_write_cached uses this
3885 * out of line function when the target is an MMIO or IOMMU region.
3888 address_space_write_cached_slow(MemoryRegionCache
*cache
, hwaddr addr
,
3889 const void *buf
, hwaddr len
)
3895 mr
= address_space_translate_cached(cache
, addr
, &addr1
, &l
, true,
3896 MEMTXATTRS_UNSPECIFIED
);
3897 flatview_write_continue(cache
->fv
,
3898 addr
, MEMTXATTRS_UNSPECIFIED
, buf
, len
,
3902 #define ARG1_DECL MemoryRegionCache *cache
3904 #define SUFFIX _cached_slow
3905 #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__)
3906 #define RCU_READ_LOCK() ((void)0)
3907 #define RCU_READ_UNLOCK() ((void)0)
3908 #include "memory_ldst.inc.c"
3910 /* virtual memory access for debug (includes writing to ROM) */
3911 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
3912 uint8_t *buf
, target_ulong len
, int is_write
)
3915 target_ulong l
, page
;
3917 cpu_synchronize_state(cpu
);
3922 page
= addr
& TARGET_PAGE_MASK
;
3923 phys_addr
= cpu_get_phys_page_attrs_debug(cpu
, page
, &attrs
);
3924 asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
3925 /* if no physical page mapped, return an error */
3926 if (phys_addr
== -1)
3928 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
3931 phys_addr
+= (addr
& ~TARGET_PAGE_MASK
);
3933 address_space_write_rom(cpu
->cpu_ases
[asidx
].as
, phys_addr
,
3936 address_space_rw(cpu
->cpu_ases
[asidx
].as
, phys_addr
,
3947 * Allows code that needs to deal with migration bitmaps etc to still be built
3948 * target independent.
3950 size_t qemu_target_page_size(void)
3952 return TARGET_PAGE_SIZE
;
3955 int qemu_target_page_bits(void)
3957 return TARGET_PAGE_BITS
;
3960 int qemu_target_page_bits_min(void)
3962 return TARGET_PAGE_BITS_MIN
;
3966 bool target_words_bigendian(void)
3968 #if defined(TARGET_WORDS_BIGENDIAN)
3975 #ifndef CONFIG_USER_ONLY
3976 bool cpu_physical_memory_is_io(hwaddr phys_addr
)
3983 mr
= address_space_translate(&address_space_memory
,
3984 phys_addr
, &phys_addr
, &l
, false,
3985 MEMTXATTRS_UNSPECIFIED
);
3987 res
= !(memory_region_is_ram(mr
) || memory_region_is_romd(mr
));
3992 int qemu_ram_foreach_block(RAMBlockIterFunc func
, void *opaque
)
3998 RAMBLOCK_FOREACH(block
) {
3999 ret
= func(block
, opaque
);
4009 * Unmap pages of memory from start to start+length such that
4010 * they a) read as 0, b) Trigger whatever fault mechanism
4011 * the OS provides for postcopy.
4012 * The pages must be unmapped by the end of the function.
4013 * Returns: 0 on success, none-0 on failure
4016 int ram_block_discard_range(RAMBlock
*rb
, uint64_t start
, size_t length
)
4020 uint8_t *host_startaddr
= rb
->host
+ start
;
4022 if ((uintptr_t)host_startaddr
& (rb
->page_size
- 1)) {
4023 error_report("ram_block_discard_range: Unaligned start address: %p",
4028 if ((start
+ length
) <= rb
->used_length
) {
4029 bool need_madvise
, need_fallocate
;
4030 uint8_t *host_endaddr
= host_startaddr
+ length
;
4031 if ((uintptr_t)host_endaddr
& (rb
->page_size
- 1)) {
4032 error_report("ram_block_discard_range: Unaligned end address: %p",
4037 errno
= ENOTSUP
; /* If we are missing MADVISE etc */
4039 /* The logic here is messy;
4040 * madvise DONTNEED fails for hugepages
4041 * fallocate works on hugepages and shmem
4043 need_madvise
= (rb
->page_size
== qemu_host_page_size
);
4044 need_fallocate
= rb
->fd
!= -1;
4045 if (need_fallocate
) {
4046 /* For a file, this causes the area of the file to be zero'd
4047 * if read, and for hugetlbfs also causes it to be unmapped
4048 * so a userfault will trigger.
4050 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
4051 ret
= fallocate(rb
->fd
, FALLOC_FL_PUNCH_HOLE
| FALLOC_FL_KEEP_SIZE
,
4055 error_report("ram_block_discard_range: Failed to fallocate "
4056 "%s:%" PRIx64
" +%zx (%d)",
4057 rb
->idstr
, start
, length
, ret
);
4062 error_report("ram_block_discard_range: fallocate not available/file"
4063 "%s:%" PRIx64
" +%zx (%d)",
4064 rb
->idstr
, start
, length
, ret
);
4069 /* For normal RAM this causes it to be unmapped,
4070 * for shared memory it causes the local mapping to disappear
4071 * and to fall back on the file contents (which we just
4072 * fallocate'd away).
4074 #if defined(CONFIG_MADVISE)
4075 ret
= madvise(host_startaddr
, length
, MADV_DONTNEED
);
4078 error_report("ram_block_discard_range: Failed to discard range "
4079 "%s:%" PRIx64
" +%zx (%d)",
4080 rb
->idstr
, start
, length
, ret
);
4085 error_report("ram_block_discard_range: MADVISE not available"
4086 "%s:%" PRIx64
" +%zx (%d)",
4087 rb
->idstr
, start
, length
, ret
);
4091 trace_ram_block_discard_range(rb
->idstr
, host_startaddr
, length
,
4092 need_madvise
, need_fallocate
, ret
);
4094 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
4095 "/%zx/" RAM_ADDR_FMT
")",
4096 rb
->idstr
, start
, length
, rb
->used_length
);
4103 bool ramblock_is_pmem(RAMBlock
*rb
)
4105 return rb
->flags
& RAM_PMEM
;
4110 void page_size_init(void)
4112 /* NOTE: we can always suppose that qemu_host_page_size >=
4114 if (qemu_host_page_size
== 0) {
4115 qemu_host_page_size
= qemu_real_host_page_size
;
4117 if (qemu_host_page_size
< TARGET_PAGE_SIZE
) {
4118 qemu_host_page_size
= TARGET_PAGE_SIZE
;
4120 qemu_host_page_mask
= -(intptr_t)qemu_host_page_size
;
4123 #if !defined(CONFIG_USER_ONLY)
4125 static void mtree_print_phys_entries(int start
, int end
, int skip
, int ptr
)
4127 if (start
== end
- 1) {
4128 qemu_printf("\t%3d ", start
);
4130 qemu_printf("\t%3d..%-3d ", start
, end
- 1);
4132 qemu_printf(" skip=%d ", skip
);
4133 if (ptr
== PHYS_MAP_NODE_NIL
) {
4134 qemu_printf(" ptr=NIL");
4136 qemu_printf(" ptr=#%d", ptr
);
4138 qemu_printf(" ptr=[%d]", ptr
);
4143 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
4144 int128_sub((size), int128_one())) : 0)
4146 void mtree_print_dispatch(AddressSpaceDispatch
*d
, MemoryRegion
*root
)
4150 qemu_printf(" Dispatch\n");
4151 qemu_printf(" Physical sections\n");
4153 for (i
= 0; i
< d
->map
.sections_nb
; ++i
) {
4154 MemoryRegionSection
*s
= d
->map
.sections
+ i
;
4155 const char *names
[] = { " [unassigned]", " [not dirty]",
4156 " [ROM]", " [watch]" };
4158 qemu_printf(" #%d @" TARGET_FMT_plx
".." TARGET_FMT_plx
4161 s
->offset_within_address_space
,
4162 s
->offset_within_address_space
+ MR_SIZE(s
->mr
->size
),
4163 s
->mr
->name
? s
->mr
->name
: "(noname)",
4164 i
< ARRAY_SIZE(names
) ? names
[i
] : "",
4165 s
->mr
== root
? " [ROOT]" : "",
4166 s
== d
->mru_section
? " [MRU]" : "",
4167 s
->mr
->is_iommu
? " [iommu]" : "");
4170 qemu_printf(" alias=%s", s
->mr
->alias
->name
?
4171 s
->mr
->alias
->name
: "noname");
4176 qemu_printf(" Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n",
4177 P_L2_BITS
, P_L2_LEVELS
, d
->phys_map
.ptr
, d
->phys_map
.skip
);
4178 for (i
= 0; i
< d
->map
.nodes_nb
; ++i
) {
4181 Node
*n
= d
->map
.nodes
+ i
;
4183 qemu_printf(" [%d]\n", i
);
4185 for (j
= 0, jprev
= 0, prev
= *n
[0]; j
< ARRAY_SIZE(*n
); ++j
) {
4186 PhysPageEntry
*pe
= *n
+ j
;
4188 if (pe
->ptr
== prev
.ptr
&& pe
->skip
== prev
.skip
) {
4192 mtree_print_phys_entries(jprev
, j
, prev
.skip
, prev
.ptr
);
4198 if (jprev
!= ARRAY_SIZE(*n
)) {
4199 mtree_print_phys_entries(jprev
, j
, prev
.skip
, prev
.ptr
);