4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qapi/error.h"
24 #include "qemu/cutils.h"
26 #include "exec/exec-all.h"
27 #include "exec/target_page.h"
29 #include "hw/qdev-core.h"
30 #include "hw/qdev-properties.h"
31 #if !defined(CONFIG_USER_ONLY)
32 #include "hw/boards.h"
33 #include "hw/xen/xen.h"
35 #include "sysemu/kvm.h"
36 #include "sysemu/sysemu.h"
37 #include "sysemu/tcg.h"
38 #include "qemu/timer.h"
39 #include "qemu/config-file.h"
40 #include "qemu/error-report.h"
41 #include "qemu/qemu-print.h"
42 #if defined(CONFIG_USER_ONLY)
44 #else /* !CONFIG_USER_ONLY */
45 #include "exec/memory.h"
46 #include "exec/ioport.h"
47 #include "sysemu/dma.h"
48 #include "sysemu/hostmem.h"
49 #include "sysemu/hw_accel.h"
50 #include "exec/address-spaces.h"
51 #include "sysemu/xen-mapcache.h"
52 #include "trace-root.h"
54 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
55 #include <linux/falloc.h>
59 #include "qemu/rcu_queue.h"
60 #include "qemu/main-loop.h"
61 #include "translate-all.h"
62 #include "sysemu/replay.h"
64 #include "exec/memory-internal.h"
65 #include "exec/ram_addr.h"
68 #include "migration/vmstate.h"
70 #include "qemu/range.h"
72 #include "qemu/mmap-alloc.h"
75 #include "monitor/monitor.h"
77 //#define DEBUG_SUBPAGE
79 #if !defined(CONFIG_USER_ONLY)
80 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
81 * are protected by the ramlist lock.
83 RAMList ram_list
= { .blocks
= QLIST_HEAD_INITIALIZER(ram_list
.blocks
) };
85 static MemoryRegion
*system_memory
;
86 static MemoryRegion
*system_io
;
88 AddressSpace address_space_io
;
89 AddressSpace address_space_memory
;
91 MemoryRegion io_mem_rom
, io_mem_notdirty
;
92 static MemoryRegion io_mem_unassigned
;
95 #ifdef TARGET_PAGE_BITS_VARY
97 bool target_page_bits_decided
;
100 CPUTailQ cpus
= QTAILQ_HEAD_INITIALIZER(cpus
);
102 /* current CPU in the current thread. It is only valid inside
104 __thread CPUState
*current_cpu
;
105 /* 0 = Do not count executed instructions.
106 1 = Precise instruction counting.
107 2 = Adaptive rate instruction counting. */
110 uintptr_t qemu_host_page_size
;
111 intptr_t qemu_host_page_mask
;
113 bool set_preferred_target_page_bits(int bits
)
115 /* The target page size is the lowest common denominator for all
116 * the CPUs in the system, so we can only make it smaller, never
117 * larger. And we can't make it smaller once we've committed to
120 #ifdef TARGET_PAGE_BITS_VARY
121 assert(bits
>= TARGET_PAGE_BITS_MIN
);
122 if (target_page_bits
== 0 || target_page_bits
> bits
) {
123 if (target_page_bits_decided
) {
126 target_page_bits
= bits
;
132 #if !defined(CONFIG_USER_ONLY)
134 static void finalize_target_page_bits(void)
136 #ifdef TARGET_PAGE_BITS_VARY
137 if (target_page_bits
== 0) {
138 target_page_bits
= TARGET_PAGE_BITS_MIN
;
140 target_page_bits_decided
= true;
144 typedef struct PhysPageEntry PhysPageEntry
;
146 struct PhysPageEntry
{
147 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
149 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
153 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
155 /* Size of the L2 (and L3, etc) page tables. */
156 #define ADDR_SPACE_BITS 64
159 #define P_L2_SIZE (1 << P_L2_BITS)
161 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
163 typedef PhysPageEntry Node
[P_L2_SIZE
];
165 typedef struct PhysPageMap
{
168 unsigned sections_nb
;
169 unsigned sections_nb_alloc
;
171 unsigned nodes_nb_alloc
;
173 MemoryRegionSection
*sections
;
176 struct AddressSpaceDispatch
{
177 MemoryRegionSection
*mru_section
;
178 /* This is a multi-level map on the physical address space.
179 * The bottom level has pointers to MemoryRegionSections.
181 PhysPageEntry phys_map
;
185 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
186 typedef struct subpage_t
{
190 uint16_t sub_section
[];
193 #define PHYS_SECTION_UNASSIGNED 0
194 #define PHYS_SECTION_NOTDIRTY 1
195 #define PHYS_SECTION_ROM 2
197 static void io_mem_init(void);
198 static void memory_map_init(void);
199 static void tcg_log_global_after_sync(MemoryListener
*listener
);
200 static void tcg_commit(MemoryListener
*listener
);
203 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
204 * @cpu: the CPU whose AddressSpace this is
205 * @as: the AddressSpace itself
206 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
207 * @tcg_as_listener: listener for tracking changes to the AddressSpace
209 struct CPUAddressSpace
{
212 struct AddressSpaceDispatch
*memory_dispatch
;
213 MemoryListener tcg_as_listener
;
216 struct DirtyBitmapSnapshot
{
219 unsigned long dirty
[];
224 #if !defined(CONFIG_USER_ONLY)
226 static void phys_map_node_reserve(PhysPageMap
*map
, unsigned nodes
)
228 static unsigned alloc_hint
= 16;
229 if (map
->nodes_nb
+ nodes
> map
->nodes_nb_alloc
) {
230 map
->nodes_nb_alloc
= MAX(alloc_hint
, map
->nodes_nb
+ nodes
);
231 map
->nodes
= g_renew(Node
, map
->nodes
, map
->nodes_nb_alloc
);
232 alloc_hint
= map
->nodes_nb_alloc
;
236 static uint32_t phys_map_node_alloc(PhysPageMap
*map
, bool leaf
)
243 ret
= map
->nodes_nb
++;
245 assert(ret
!= PHYS_MAP_NODE_NIL
);
246 assert(ret
!= map
->nodes_nb_alloc
);
248 e
.skip
= leaf
? 0 : 1;
249 e
.ptr
= leaf
? PHYS_SECTION_UNASSIGNED
: PHYS_MAP_NODE_NIL
;
250 for (i
= 0; i
< P_L2_SIZE
; ++i
) {
251 memcpy(&p
[i
], &e
, sizeof(e
));
256 static void phys_page_set_level(PhysPageMap
*map
, PhysPageEntry
*lp
,
257 hwaddr
*index
, uint64_t *nb
, uint16_t leaf
,
261 hwaddr step
= (hwaddr
)1 << (level
* P_L2_BITS
);
263 if (lp
->skip
&& lp
->ptr
== PHYS_MAP_NODE_NIL
) {
264 lp
->ptr
= phys_map_node_alloc(map
, level
== 0);
266 p
= map
->nodes
[lp
->ptr
];
267 lp
= &p
[(*index
>> (level
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
269 while (*nb
&& lp
< &p
[P_L2_SIZE
]) {
270 if ((*index
& (step
- 1)) == 0 && *nb
>= step
) {
276 phys_page_set_level(map
, lp
, index
, nb
, leaf
, level
- 1);
282 static void phys_page_set(AddressSpaceDispatch
*d
,
283 hwaddr index
, uint64_t nb
,
286 /* Wildly overreserve - it doesn't matter much. */
287 phys_map_node_reserve(&d
->map
, 3 * P_L2_LEVELS
);
289 phys_page_set_level(&d
->map
, &d
->phys_map
, &index
, &nb
, leaf
, P_L2_LEVELS
- 1);
292 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
293 * and update our entry so we can skip it and go directly to the destination.
295 static void phys_page_compact(PhysPageEntry
*lp
, Node
*nodes
)
297 unsigned valid_ptr
= P_L2_SIZE
;
302 if (lp
->ptr
== PHYS_MAP_NODE_NIL
) {
307 for (i
= 0; i
< P_L2_SIZE
; i
++) {
308 if (p
[i
].ptr
== PHYS_MAP_NODE_NIL
) {
315 phys_page_compact(&p
[i
], nodes
);
319 /* We can only compress if there's only one child. */
324 assert(valid_ptr
< P_L2_SIZE
);
326 /* Don't compress if it won't fit in the # of bits we have. */
327 if (P_L2_LEVELS
>= (1 << 6) &&
328 lp
->skip
+ p
[valid_ptr
].skip
>= (1 << 6)) {
332 lp
->ptr
= p
[valid_ptr
].ptr
;
333 if (!p
[valid_ptr
].skip
) {
334 /* If our only child is a leaf, make this a leaf. */
335 /* By design, we should have made this node a leaf to begin with so we
336 * should never reach here.
337 * But since it's so simple to handle this, let's do it just in case we
342 lp
->skip
+= p
[valid_ptr
].skip
;
346 void address_space_dispatch_compact(AddressSpaceDispatch
*d
)
348 if (d
->phys_map
.skip
) {
349 phys_page_compact(&d
->phys_map
, d
->map
.nodes
);
353 static inline bool section_covers_addr(const MemoryRegionSection
*section
,
356 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
357 * the section must cover the entire address space.
359 return int128_gethi(section
->size
) ||
360 range_covers_byte(section
->offset_within_address_space
,
361 int128_getlo(section
->size
), addr
);
364 static MemoryRegionSection
*phys_page_find(AddressSpaceDispatch
*d
, hwaddr addr
)
366 PhysPageEntry lp
= d
->phys_map
, *p
;
367 Node
*nodes
= d
->map
.nodes
;
368 MemoryRegionSection
*sections
= d
->map
.sections
;
369 hwaddr index
= addr
>> TARGET_PAGE_BITS
;
372 for (i
= P_L2_LEVELS
; lp
.skip
&& (i
-= lp
.skip
) >= 0;) {
373 if (lp
.ptr
== PHYS_MAP_NODE_NIL
) {
374 return §ions
[PHYS_SECTION_UNASSIGNED
];
377 lp
= p
[(index
>> (i
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
380 if (section_covers_addr(§ions
[lp
.ptr
], addr
)) {
381 return §ions
[lp
.ptr
];
383 return §ions
[PHYS_SECTION_UNASSIGNED
];
387 /* Called from RCU critical section */
388 static MemoryRegionSection
*address_space_lookup_region(AddressSpaceDispatch
*d
,
390 bool resolve_subpage
)
392 MemoryRegionSection
*section
= atomic_read(&d
->mru_section
);
395 if (!section
|| section
== &d
->map
.sections
[PHYS_SECTION_UNASSIGNED
] ||
396 !section_covers_addr(section
, addr
)) {
397 section
= phys_page_find(d
, addr
);
398 atomic_set(&d
->mru_section
, section
);
400 if (resolve_subpage
&& section
->mr
->subpage
) {
401 subpage
= container_of(section
->mr
, subpage_t
, iomem
);
402 section
= &d
->map
.sections
[subpage
->sub_section
[SUBPAGE_IDX(addr
)]];
407 /* Called from RCU critical section */
408 static MemoryRegionSection
*
409 address_space_translate_internal(AddressSpaceDispatch
*d
, hwaddr addr
, hwaddr
*xlat
,
410 hwaddr
*plen
, bool resolve_subpage
)
412 MemoryRegionSection
*section
;
416 section
= address_space_lookup_region(d
, addr
, resolve_subpage
);
417 /* Compute offset within MemoryRegionSection */
418 addr
-= section
->offset_within_address_space
;
420 /* Compute offset within MemoryRegion */
421 *xlat
= addr
+ section
->offset_within_region
;
425 /* MMIO registers can be expected to perform full-width accesses based only
426 * on their address, without considering adjacent registers that could
427 * decode to completely different MemoryRegions. When such registers
428 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
429 * regions overlap wildly. For this reason we cannot clamp the accesses
432 * If the length is small (as is the case for address_space_ldl/stl),
433 * everything works fine. If the incoming length is large, however,
434 * the caller really has to do the clamping through memory_access_size.
436 if (memory_region_is_ram(mr
)) {
437 diff
= int128_sub(section
->size
, int128_make64(addr
));
438 *plen
= int128_get64(int128_min(diff
, int128_make64(*plen
)));
444 * address_space_translate_iommu - translate an address through an IOMMU
445 * memory region and then through the target address space.
447 * @iommu_mr: the IOMMU memory region that we start the translation from
448 * @addr: the address to be translated through the MMU
449 * @xlat: the translated address offset within the destination memory region.
450 * It cannot be %NULL.
451 * @plen_out: valid read/write length of the translated address. It
453 * @page_mask_out: page mask for the translated address. This
454 * should only be meaningful for IOMMU translated
455 * addresses, since there may be huge pages that this bit
456 * would tell. It can be %NULL if we don't care about it.
457 * @is_write: whether the translation operation is for write
458 * @is_mmio: whether this can be MMIO, set true if it can
459 * @target_as: the address space targeted by the IOMMU
460 * @attrs: transaction attributes
462 * This function is called from RCU critical section. It is the common
463 * part of flatview_do_translate and address_space_translate_cached.
465 static MemoryRegionSection
address_space_translate_iommu(IOMMUMemoryRegion
*iommu_mr
,
468 hwaddr
*page_mask_out
,
471 AddressSpace
**target_as
,
474 MemoryRegionSection
*section
;
475 hwaddr page_mask
= (hwaddr
)-1;
479 IOMMUMemoryRegionClass
*imrc
= memory_region_get_iommu_class_nocheck(iommu_mr
);
483 if (imrc
->attrs_to_index
) {
484 iommu_idx
= imrc
->attrs_to_index(iommu_mr
, attrs
);
487 iotlb
= imrc
->translate(iommu_mr
, addr
, is_write
?
488 IOMMU_WO
: IOMMU_RO
, iommu_idx
);
490 if (!(iotlb
.perm
& (1 << is_write
))) {
494 addr
= ((iotlb
.translated_addr
& ~iotlb
.addr_mask
)
495 | (addr
& iotlb
.addr_mask
));
496 page_mask
&= iotlb
.addr_mask
;
497 *plen_out
= MIN(*plen_out
, (addr
| iotlb
.addr_mask
) - addr
+ 1);
498 *target_as
= iotlb
.target_as
;
500 section
= address_space_translate_internal(
501 address_space_to_dispatch(iotlb
.target_as
), addr
, xlat
,
504 iommu_mr
= memory_region_get_iommu(section
->mr
);
505 } while (unlikely(iommu_mr
));
508 *page_mask_out
= page_mask
;
513 return (MemoryRegionSection
) { .mr
= &io_mem_unassigned
};
517 * flatview_do_translate - translate an address in FlatView
519 * @fv: the flat view that we want to translate on
520 * @addr: the address to be translated in above address space
521 * @xlat: the translated address offset within memory region. It
523 * @plen_out: valid read/write length of the translated address. It
524 * can be @NULL when we don't care about it.
525 * @page_mask_out: page mask for the translated address. This
526 * should only be meaningful for IOMMU translated
527 * addresses, since there may be huge pages that this bit
528 * would tell. It can be @NULL if we don't care about it.
529 * @is_write: whether the translation operation is for write
530 * @is_mmio: whether this can be MMIO, set true if it can
531 * @target_as: the address space targeted by the IOMMU
532 * @attrs: memory transaction attributes
534 * This function is called from RCU critical section
536 static MemoryRegionSection
flatview_do_translate(FlatView
*fv
,
540 hwaddr
*page_mask_out
,
543 AddressSpace
**target_as
,
546 MemoryRegionSection
*section
;
547 IOMMUMemoryRegion
*iommu_mr
;
548 hwaddr plen
= (hwaddr
)(-1);
554 section
= address_space_translate_internal(
555 flatview_to_dispatch(fv
), addr
, xlat
,
558 iommu_mr
= memory_region_get_iommu(section
->mr
);
559 if (unlikely(iommu_mr
)) {
560 return address_space_translate_iommu(iommu_mr
, xlat
,
561 plen_out
, page_mask_out
,
566 /* Not behind an IOMMU, use default page size. */
567 *page_mask_out
= ~TARGET_PAGE_MASK
;
573 /* Called from RCU critical section */
574 IOMMUTLBEntry
address_space_get_iotlb_entry(AddressSpace
*as
, hwaddr addr
,
575 bool is_write
, MemTxAttrs attrs
)
577 MemoryRegionSection section
;
578 hwaddr xlat
, page_mask
;
581 * This can never be MMIO, and we don't really care about plen,
584 section
= flatview_do_translate(address_space_to_flatview(as
), addr
, &xlat
,
585 NULL
, &page_mask
, is_write
, false, &as
,
588 /* Illegal translation */
589 if (section
.mr
== &io_mem_unassigned
) {
593 /* Convert memory region offset into address space offset */
594 xlat
+= section
.offset_within_address_space
-
595 section
.offset_within_region
;
597 return (IOMMUTLBEntry
) {
599 .iova
= addr
& ~page_mask
,
600 .translated_addr
= xlat
& ~page_mask
,
601 .addr_mask
= page_mask
,
602 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
607 return (IOMMUTLBEntry
) {0};
610 /* Called from RCU critical section */
611 MemoryRegion
*flatview_translate(FlatView
*fv
, hwaddr addr
, hwaddr
*xlat
,
612 hwaddr
*plen
, bool is_write
,
616 MemoryRegionSection section
;
617 AddressSpace
*as
= NULL
;
619 /* This can be MMIO, so setup MMIO bit. */
620 section
= flatview_do_translate(fv
, addr
, xlat
, plen
, NULL
,
621 is_write
, true, &as
, attrs
);
624 if (xen_enabled() && memory_access_is_direct(mr
, is_write
)) {
625 hwaddr page
= ((addr
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
) - addr
;
626 *plen
= MIN(page
, *plen
);
632 typedef struct TCGIOMMUNotifier
{
640 static void tcg_iommu_unmap_notify(IOMMUNotifier
*n
, IOMMUTLBEntry
*iotlb
)
642 TCGIOMMUNotifier
*notifier
= container_of(n
, TCGIOMMUNotifier
, n
);
644 if (!notifier
->active
) {
647 tlb_flush(notifier
->cpu
);
648 notifier
->active
= false;
649 /* We leave the notifier struct on the list to avoid reallocating it later.
650 * Generally the number of IOMMUs a CPU deals with will be small.
651 * In any case we can't unregister the iommu notifier from a notify
656 static void tcg_register_iommu_notifier(CPUState
*cpu
,
657 IOMMUMemoryRegion
*iommu_mr
,
660 /* Make sure this CPU has an IOMMU notifier registered for this
661 * IOMMU/IOMMU index combination, so that we can flush its TLB
662 * when the IOMMU tells us the mappings we've cached have changed.
664 MemoryRegion
*mr
= MEMORY_REGION(iommu_mr
);
665 TCGIOMMUNotifier
*notifier
;
668 for (i
= 0; i
< cpu
->iommu_notifiers
->len
; i
++) {
669 notifier
= g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
*, i
);
670 if (notifier
->mr
== mr
&& notifier
->iommu_idx
== iommu_idx
) {
674 if (i
== cpu
->iommu_notifiers
->len
) {
675 /* Not found, add a new entry at the end of the array */
676 cpu
->iommu_notifiers
= g_array_set_size(cpu
->iommu_notifiers
, i
+ 1);
677 notifier
= g_new0(TCGIOMMUNotifier
, 1);
678 g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
*, i
) = notifier
;
681 notifier
->iommu_idx
= iommu_idx
;
683 /* Rather than trying to register interest in the specific part
684 * of the iommu's address space that we've accessed and then
685 * expand it later as subsequent accesses touch more of it, we
686 * just register interest in the whole thing, on the assumption
687 * that iommu reconfiguration will be rare.
689 iommu_notifier_init(¬ifier
->n
,
690 tcg_iommu_unmap_notify
,
691 IOMMU_NOTIFIER_UNMAP
,
695 memory_region_register_iommu_notifier(notifier
->mr
, ¬ifier
->n
);
698 if (!notifier
->active
) {
699 notifier
->active
= true;
703 static void tcg_iommu_free_notifier_list(CPUState
*cpu
)
705 /* Destroy the CPU's notifier list */
707 TCGIOMMUNotifier
*notifier
;
709 for (i
= 0; i
< cpu
->iommu_notifiers
->len
; i
++) {
710 notifier
= g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
*, i
);
711 memory_region_unregister_iommu_notifier(notifier
->mr
, ¬ifier
->n
);
714 g_array_free(cpu
->iommu_notifiers
, true);
717 /* Called from RCU critical section */
718 MemoryRegionSection
*
719 address_space_translate_for_iotlb(CPUState
*cpu
, int asidx
, hwaddr addr
,
720 hwaddr
*xlat
, hwaddr
*plen
,
721 MemTxAttrs attrs
, int *prot
)
723 MemoryRegionSection
*section
;
724 IOMMUMemoryRegion
*iommu_mr
;
725 IOMMUMemoryRegionClass
*imrc
;
728 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpu
->cpu_ases
[asidx
].memory_dispatch
);
731 section
= address_space_translate_internal(d
, addr
, &addr
, plen
, false);
733 iommu_mr
= memory_region_get_iommu(section
->mr
);
738 imrc
= memory_region_get_iommu_class_nocheck(iommu_mr
);
740 iommu_idx
= imrc
->attrs_to_index(iommu_mr
, attrs
);
741 tcg_register_iommu_notifier(cpu
, iommu_mr
, iommu_idx
);
742 /* We need all the permissions, so pass IOMMU_NONE so the IOMMU
743 * doesn't short-cut its translation table walk.
745 iotlb
= imrc
->translate(iommu_mr
, addr
, IOMMU_NONE
, iommu_idx
);
746 addr
= ((iotlb
.translated_addr
& ~iotlb
.addr_mask
)
747 | (addr
& iotlb
.addr_mask
));
748 /* Update the caller's prot bits to remove permissions the IOMMU
749 * is giving us a failure response for. If we get down to no
750 * permissions left at all we can give up now.
752 if (!(iotlb
.perm
& IOMMU_RO
)) {
753 *prot
&= ~(PAGE_READ
| PAGE_EXEC
);
755 if (!(iotlb
.perm
& IOMMU_WO
)) {
756 *prot
&= ~PAGE_WRITE
;
763 d
= flatview_to_dispatch(address_space_to_flatview(iotlb
.target_as
));
766 assert(!memory_region_is_iommu(section
->mr
));
771 return &d
->map
.sections
[PHYS_SECTION_UNASSIGNED
];
775 #if !defined(CONFIG_USER_ONLY)
777 static int cpu_common_post_load(void *opaque
, int version_id
)
779 CPUState
*cpu
= opaque
;
781 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
782 version_id is increased. */
783 cpu
->interrupt_request
&= ~0x01;
786 /* loadvm has just updated the content of RAM, bypassing the
787 * usual mechanisms that ensure we flush TBs for writes to
788 * memory we've translated code from. So we must flush all TBs,
789 * which will now be stale.
796 static int cpu_common_pre_load(void *opaque
)
798 CPUState
*cpu
= opaque
;
800 cpu
->exception_index
= -1;
805 static bool cpu_common_exception_index_needed(void *opaque
)
807 CPUState
*cpu
= opaque
;
809 return tcg_enabled() && cpu
->exception_index
!= -1;
812 static const VMStateDescription vmstate_cpu_common_exception_index
= {
813 .name
= "cpu_common/exception_index",
815 .minimum_version_id
= 1,
816 .needed
= cpu_common_exception_index_needed
,
817 .fields
= (VMStateField
[]) {
818 VMSTATE_INT32(exception_index
, CPUState
),
819 VMSTATE_END_OF_LIST()
823 static bool cpu_common_crash_occurred_needed(void *opaque
)
825 CPUState
*cpu
= opaque
;
827 return cpu
->crash_occurred
;
830 static const VMStateDescription vmstate_cpu_common_crash_occurred
= {
831 .name
= "cpu_common/crash_occurred",
833 .minimum_version_id
= 1,
834 .needed
= cpu_common_crash_occurred_needed
,
835 .fields
= (VMStateField
[]) {
836 VMSTATE_BOOL(crash_occurred
, CPUState
),
837 VMSTATE_END_OF_LIST()
841 const VMStateDescription vmstate_cpu_common
= {
842 .name
= "cpu_common",
844 .minimum_version_id
= 1,
845 .pre_load
= cpu_common_pre_load
,
846 .post_load
= cpu_common_post_load
,
847 .fields
= (VMStateField
[]) {
848 VMSTATE_UINT32(halted
, CPUState
),
849 VMSTATE_UINT32(interrupt_request
, CPUState
),
850 VMSTATE_END_OF_LIST()
852 .subsections
= (const VMStateDescription
*[]) {
853 &vmstate_cpu_common_exception_index
,
854 &vmstate_cpu_common_crash_occurred
,
861 CPUState
*qemu_get_cpu(int index
)
866 if (cpu
->cpu_index
== index
) {
874 #if !defined(CONFIG_USER_ONLY)
875 void cpu_address_space_init(CPUState
*cpu
, int asidx
,
876 const char *prefix
, MemoryRegion
*mr
)
878 CPUAddressSpace
*newas
;
879 AddressSpace
*as
= g_new0(AddressSpace
, 1);
883 as_name
= g_strdup_printf("%s-%d", prefix
, cpu
->cpu_index
);
884 address_space_init(as
, mr
, as_name
);
887 /* Target code should have set num_ases before calling us */
888 assert(asidx
< cpu
->num_ases
);
891 /* address space 0 gets the convenience alias */
895 /* KVM cannot currently support multiple address spaces. */
896 assert(asidx
== 0 || !kvm_enabled());
898 if (!cpu
->cpu_ases
) {
899 cpu
->cpu_ases
= g_new0(CPUAddressSpace
, cpu
->num_ases
);
902 newas
= &cpu
->cpu_ases
[asidx
];
906 newas
->tcg_as_listener
.log_global_after_sync
= tcg_log_global_after_sync
;
907 newas
->tcg_as_listener
.commit
= tcg_commit
;
908 memory_listener_register(&newas
->tcg_as_listener
, as
);
912 AddressSpace
*cpu_get_address_space(CPUState
*cpu
, int asidx
)
914 /* Return the AddressSpace corresponding to the specified index */
915 return cpu
->cpu_ases
[asidx
].as
;
919 void cpu_exec_unrealizefn(CPUState
*cpu
)
921 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
923 cpu_list_remove(cpu
);
925 if (cc
->vmsd
!= NULL
) {
926 vmstate_unregister(NULL
, cc
->vmsd
, cpu
);
928 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
929 vmstate_unregister(NULL
, &vmstate_cpu_common
, cpu
);
931 #ifndef CONFIG_USER_ONLY
932 tcg_iommu_free_notifier_list(cpu
);
936 Property cpu_common_props
[] = {
937 #ifndef CONFIG_USER_ONLY
938 /* Create a memory property for softmmu CPU object,
939 * so users can wire up its memory. (This can't go in hw/core/cpu.c
940 * because that file is compiled only once for both user-mode
941 * and system builds.) The default if no link is set up is to use
942 * the system address space.
944 DEFINE_PROP_LINK("memory", CPUState
, memory
, TYPE_MEMORY_REGION
,
947 DEFINE_PROP_END_OF_LIST(),
950 void cpu_exec_initfn(CPUState
*cpu
)
955 #ifndef CONFIG_USER_ONLY
956 cpu
->thread_id
= qemu_get_thread_id();
957 cpu
->memory
= system_memory
;
958 object_ref(OBJECT(cpu
->memory
));
962 void cpu_exec_realizefn(CPUState
*cpu
, Error
**errp
)
964 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
965 static bool tcg_target_initialized
;
969 if (tcg_enabled() && !tcg_target_initialized
) {
970 tcg_target_initialized
= true;
971 cc
->tcg_initialize();
975 #ifndef CONFIG_USER_ONLY
976 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
977 vmstate_register(NULL
, cpu
->cpu_index
, &vmstate_cpu_common
, cpu
);
979 if (cc
->vmsd
!= NULL
) {
980 vmstate_register(NULL
, cpu
->cpu_index
, cc
->vmsd
, cpu
);
983 cpu
->iommu_notifiers
= g_array_new(false, true, sizeof(TCGIOMMUNotifier
*));
987 const char *parse_cpu_option(const char *cpu_option
)
991 gchar
**model_pieces
;
992 const char *cpu_type
;
994 model_pieces
= g_strsplit(cpu_option
, ",", 2);
995 if (!model_pieces
[0]) {
996 error_report("-cpu option cannot be empty");
1000 oc
= cpu_class_by_name(CPU_RESOLVING_TYPE
, model_pieces
[0]);
1002 error_report("unable to find CPU model '%s'", model_pieces
[0]);
1003 g_strfreev(model_pieces
);
1007 cpu_type
= object_class_get_name(oc
);
1009 cc
->parse_features(cpu_type
, model_pieces
[1], &error_fatal
);
1010 g_strfreev(model_pieces
);
1014 #if defined(CONFIG_USER_ONLY)
1015 void tb_invalidate_phys_addr(target_ulong addr
)
1018 tb_invalidate_phys_page_range(addr
, addr
+ 1, 0);
1022 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
1024 tb_invalidate_phys_addr(pc
);
1027 void tb_invalidate_phys_addr(AddressSpace
*as
, hwaddr addr
, MemTxAttrs attrs
)
1029 ram_addr_t ram_addr
;
1033 if (!tcg_enabled()) {
1038 mr
= address_space_translate(as
, addr
, &addr
, &l
, false, attrs
);
1039 if (!(memory_region_is_ram(mr
)
1040 || memory_region_is_romd(mr
))) {
1044 ram_addr
= memory_region_get_ram_addr(mr
) + addr
;
1045 tb_invalidate_phys_page_range(ram_addr
, ram_addr
+ 1, 0);
1049 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
1052 hwaddr phys
= cpu_get_phys_page_attrs_debug(cpu
, pc
, &attrs
);
1053 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
1055 /* Locks grabbed by tb_invalidate_phys_addr */
1056 tb_invalidate_phys_addr(cpu
->cpu_ases
[asidx
].as
,
1057 phys
| (pc
& ~TARGET_PAGE_MASK
), attrs
);
1062 #ifndef CONFIG_USER_ONLY
1063 /* Add a watchpoint. */
1064 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
1065 int flags
, CPUWatchpoint
**watchpoint
)
1069 /* forbid ranges which are empty or run off the end of the address space */
1070 if (len
== 0 || (addr
+ len
- 1) < addr
) {
1071 error_report("tried to set invalid watchpoint at %"
1072 VADDR_PRIx
", len=%" VADDR_PRIu
, addr
, len
);
1075 wp
= g_malloc(sizeof(*wp
));
1081 /* keep all GDB-injected watchpoints in front */
1082 if (flags
& BP_GDB
) {
1083 QTAILQ_INSERT_HEAD(&cpu
->watchpoints
, wp
, entry
);
1085 QTAILQ_INSERT_TAIL(&cpu
->watchpoints
, wp
, entry
);
1088 tlb_flush_page(cpu
, addr
);
1095 /* Remove a specific watchpoint. */
1096 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
, vaddr len
,
1101 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
1102 if (addr
== wp
->vaddr
&& len
== wp
->len
1103 && flags
== (wp
->flags
& ~BP_WATCHPOINT_HIT
)) {
1104 cpu_watchpoint_remove_by_ref(cpu
, wp
);
1111 /* Remove a specific watchpoint by reference. */
1112 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
)
1114 QTAILQ_REMOVE(&cpu
->watchpoints
, watchpoint
, entry
);
1116 tlb_flush_page(cpu
, watchpoint
->vaddr
);
1121 /* Remove all matching watchpoints. */
1122 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
1124 CPUWatchpoint
*wp
, *next
;
1126 QTAILQ_FOREACH_SAFE(wp
, &cpu
->watchpoints
, entry
, next
) {
1127 if (wp
->flags
& mask
) {
1128 cpu_watchpoint_remove_by_ref(cpu
, wp
);
1133 /* Return true if this watchpoint address matches the specified
1134 * access (ie the address range covered by the watchpoint overlaps
1135 * partially or completely with the address range covered by the
1138 static inline bool watchpoint_address_matches(CPUWatchpoint
*wp
,
1139 vaddr addr
, vaddr len
)
1141 /* We know the lengths are non-zero, but a little caution is
1142 * required to avoid errors in the case where the range ends
1143 * exactly at the top of the address space and so addr + len
1144 * wraps round to zero.
1146 vaddr wpend
= wp
->vaddr
+ wp
->len
- 1;
1147 vaddr addrend
= addr
+ len
- 1;
1149 return !(addr
> wpend
|| wp
->vaddr
> addrend
);
1152 /* Return flags for watchpoints that match addr + prot. */
1153 int cpu_watchpoint_address_matches(CPUState
*cpu
, vaddr addr
, vaddr len
)
1158 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
1159 if (watchpoint_address_matches(wp
, addr
, TARGET_PAGE_SIZE
)) {
1165 #endif /* !CONFIG_USER_ONLY */
1167 /* Add a breakpoint. */
1168 int cpu_breakpoint_insert(CPUState
*cpu
, vaddr pc
, int flags
,
1169 CPUBreakpoint
**breakpoint
)
1173 bp
= g_malloc(sizeof(*bp
));
1178 /* keep all GDB-injected breakpoints in front */
1179 if (flags
& BP_GDB
) {
1180 QTAILQ_INSERT_HEAD(&cpu
->breakpoints
, bp
, entry
);
1182 QTAILQ_INSERT_TAIL(&cpu
->breakpoints
, bp
, entry
);
1185 breakpoint_invalidate(cpu
, pc
);
1193 /* Remove a specific breakpoint. */
1194 int cpu_breakpoint_remove(CPUState
*cpu
, vaddr pc
, int flags
)
1198 QTAILQ_FOREACH(bp
, &cpu
->breakpoints
, entry
) {
1199 if (bp
->pc
== pc
&& bp
->flags
== flags
) {
1200 cpu_breakpoint_remove_by_ref(cpu
, bp
);
1207 /* Remove a specific breakpoint by reference. */
1208 void cpu_breakpoint_remove_by_ref(CPUState
*cpu
, CPUBreakpoint
*breakpoint
)
1210 QTAILQ_REMOVE(&cpu
->breakpoints
, breakpoint
, entry
);
1212 breakpoint_invalidate(cpu
, breakpoint
->pc
);
1217 /* Remove all matching breakpoints. */
1218 void cpu_breakpoint_remove_all(CPUState
*cpu
, int mask
)
1220 CPUBreakpoint
*bp
, *next
;
1222 QTAILQ_FOREACH_SAFE(bp
, &cpu
->breakpoints
, entry
, next
) {
1223 if (bp
->flags
& mask
) {
1224 cpu_breakpoint_remove_by_ref(cpu
, bp
);
1229 /* enable or disable single step mode. EXCP_DEBUG is returned by the
1230 CPU loop after each instruction */
1231 void cpu_single_step(CPUState
*cpu
, int enabled
)
1233 if (cpu
->singlestep_enabled
!= enabled
) {
1234 cpu
->singlestep_enabled
= enabled
;
1235 if (kvm_enabled()) {
1236 kvm_update_guest_debug(cpu
, 0);
1238 /* must flush all the translated code to avoid inconsistencies */
1239 /* XXX: only flush what is necessary */
1245 void cpu_abort(CPUState
*cpu
, const char *fmt
, ...)
1252 fprintf(stderr
, "qemu: fatal: ");
1253 vfprintf(stderr
, fmt
, ap
);
1254 fprintf(stderr
, "\n");
1255 cpu_dump_state(cpu
, stderr
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1256 if (qemu_log_separate()) {
1258 qemu_log("qemu: fatal: ");
1259 qemu_log_vprintf(fmt
, ap2
);
1261 log_cpu_state(cpu
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1269 #if defined(CONFIG_USER_ONLY)
1271 struct sigaction act
;
1272 sigfillset(&act
.sa_mask
);
1273 act
.sa_handler
= SIG_DFL
;
1275 sigaction(SIGABRT
, &act
, NULL
);
1281 #if !defined(CONFIG_USER_ONLY)
1282 /* Called from RCU critical section */
1283 static RAMBlock
*qemu_get_ram_block(ram_addr_t addr
)
1287 block
= atomic_rcu_read(&ram_list
.mru_block
);
1288 if (block
&& addr
- block
->offset
< block
->max_length
) {
1291 RAMBLOCK_FOREACH(block
) {
1292 if (addr
- block
->offset
< block
->max_length
) {
1297 fprintf(stderr
, "Bad ram offset %" PRIx64
"\n", (uint64_t)addr
);
1301 /* It is safe to write mru_block outside the iothread lock. This
1306 * xxx removed from list
1310 * call_rcu(reclaim_ramblock, xxx);
1313 * atomic_rcu_set is not needed here. The block was already published
1314 * when it was placed into the list. Here we're just making an extra
1315 * copy of the pointer.
1317 ram_list
.mru_block
= block
;
1321 static void tlb_reset_dirty_range_all(ram_addr_t start
, ram_addr_t length
)
1328 assert(tcg_enabled());
1329 end
= TARGET_PAGE_ALIGN(start
+ length
);
1330 start
&= TARGET_PAGE_MASK
;
1333 block
= qemu_get_ram_block(start
);
1334 assert(block
== qemu_get_ram_block(end
- 1));
1335 start1
= (uintptr_t)ramblock_ptr(block
, start
- block
->offset
);
1337 tlb_reset_dirty(cpu
, start1
, length
);
1342 /* Note: start and end must be within the same ram block. */
1343 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start
,
1347 DirtyMemoryBlocks
*blocks
;
1348 unsigned long end
, page
;
1351 uint64_t mr_offset
, mr_size
;
1357 end
= TARGET_PAGE_ALIGN(start
+ length
) >> TARGET_PAGE_BITS
;
1358 page
= start
>> TARGET_PAGE_BITS
;
1362 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1363 ramblock
= qemu_get_ram_block(start
);
1364 /* Range sanity check on the ramblock */
1365 assert(start
>= ramblock
->offset
&&
1366 start
+ length
<= ramblock
->offset
+ ramblock
->used_length
);
1368 while (page
< end
) {
1369 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1370 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1371 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1373 dirty
|= bitmap_test_and_clear_atomic(blocks
->blocks
[idx
],
1378 mr_offset
= (ram_addr_t
)(page
<< TARGET_PAGE_BITS
) - ramblock
->offset
;
1379 mr_size
= (end
- page
) << TARGET_PAGE_BITS
;
1380 memory_region_clear_dirty_bitmap(ramblock
->mr
, mr_offset
, mr_size
);
1384 if (dirty
&& tcg_enabled()) {
1385 tlb_reset_dirty_range_all(start
, length
);
1391 DirtyBitmapSnapshot
*cpu_physical_memory_snapshot_and_clear_dirty
1392 (MemoryRegion
*mr
, hwaddr offset
, hwaddr length
, unsigned client
)
1394 DirtyMemoryBlocks
*blocks
;
1395 ram_addr_t start
= memory_region_get_ram_addr(mr
) + offset
;
1396 unsigned long align
= 1UL << (TARGET_PAGE_BITS
+ BITS_PER_LEVEL
);
1397 ram_addr_t first
= QEMU_ALIGN_DOWN(start
, align
);
1398 ram_addr_t last
= QEMU_ALIGN_UP(start
+ length
, align
);
1399 DirtyBitmapSnapshot
*snap
;
1400 unsigned long page
, end
, dest
;
1402 snap
= g_malloc0(sizeof(*snap
) +
1403 ((last
- first
) >> (TARGET_PAGE_BITS
+ 3)));
1404 snap
->start
= first
;
1407 page
= first
>> TARGET_PAGE_BITS
;
1408 end
= last
>> TARGET_PAGE_BITS
;
1413 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1415 while (page
< end
) {
1416 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1417 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1418 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1420 assert(QEMU_IS_ALIGNED(offset
, (1 << BITS_PER_LEVEL
)));
1421 assert(QEMU_IS_ALIGNED(num
, (1 << BITS_PER_LEVEL
)));
1422 offset
>>= BITS_PER_LEVEL
;
1424 bitmap_copy_and_clear_atomic(snap
->dirty
+ dest
,
1425 blocks
->blocks
[idx
] + offset
,
1428 dest
+= num
>> BITS_PER_LEVEL
;
1433 if (tcg_enabled()) {
1434 tlb_reset_dirty_range_all(start
, length
);
1437 memory_region_clear_dirty_bitmap(mr
, offset
, length
);
1442 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot
*snap
,
1446 unsigned long page
, end
;
1448 assert(start
>= snap
->start
);
1449 assert(start
+ length
<= snap
->end
);
1451 end
= TARGET_PAGE_ALIGN(start
+ length
- snap
->start
) >> TARGET_PAGE_BITS
;
1452 page
= (start
- snap
->start
) >> TARGET_PAGE_BITS
;
1454 while (page
< end
) {
1455 if (test_bit(page
, snap
->dirty
)) {
1463 /* Called from RCU critical section */
1464 hwaddr
memory_region_section_get_iotlb(CPUState
*cpu
,
1465 MemoryRegionSection
*section
,
1467 hwaddr paddr
, hwaddr xlat
,
1469 target_ulong
*address
)
1473 if (memory_region_is_ram(section
->mr
)) {
1475 iotlb
= memory_region_get_ram_addr(section
->mr
) + xlat
;
1476 if (!section
->readonly
) {
1477 iotlb
|= PHYS_SECTION_NOTDIRTY
;
1479 iotlb
|= PHYS_SECTION_ROM
;
1482 AddressSpaceDispatch
*d
;
1484 d
= flatview_to_dispatch(section
->fv
);
1485 iotlb
= section
- d
->map
.sections
;
1491 #endif /* defined(CONFIG_USER_ONLY) */
1493 #if !defined(CONFIG_USER_ONLY)
1495 static int subpage_register(subpage_t
*mmio
, uint32_t start
, uint32_t end
,
1497 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
);
1499 static void *(*phys_mem_alloc
)(size_t size
, uint64_t *align
, bool shared
) =
1500 qemu_anon_ram_alloc
;
1503 * Set a custom physical guest memory alloator.
1504 * Accelerators with unusual needs may need this. Hopefully, we can
1505 * get rid of it eventually.
1507 void phys_mem_set_alloc(void *(*alloc
)(size_t, uint64_t *align
, bool shared
))
1509 phys_mem_alloc
= alloc
;
1512 static uint16_t phys_section_add(PhysPageMap
*map
,
1513 MemoryRegionSection
*section
)
1515 /* The physical section number is ORed with a page-aligned
1516 * pointer to produce the iotlb entries. Thus it should
1517 * never overflow into the page-aligned value.
1519 assert(map
->sections_nb
< TARGET_PAGE_SIZE
);
1521 if (map
->sections_nb
== map
->sections_nb_alloc
) {
1522 map
->sections_nb_alloc
= MAX(map
->sections_nb_alloc
* 2, 16);
1523 map
->sections
= g_renew(MemoryRegionSection
, map
->sections
,
1524 map
->sections_nb_alloc
);
1526 map
->sections
[map
->sections_nb
] = *section
;
1527 memory_region_ref(section
->mr
);
1528 return map
->sections_nb
++;
1531 static void phys_section_destroy(MemoryRegion
*mr
)
1533 bool have_sub_page
= mr
->subpage
;
1535 memory_region_unref(mr
);
1537 if (have_sub_page
) {
1538 subpage_t
*subpage
= container_of(mr
, subpage_t
, iomem
);
1539 object_unref(OBJECT(&subpage
->iomem
));
1544 static void phys_sections_free(PhysPageMap
*map
)
1546 while (map
->sections_nb
> 0) {
1547 MemoryRegionSection
*section
= &map
->sections
[--map
->sections_nb
];
1548 phys_section_destroy(section
->mr
);
1550 g_free(map
->sections
);
1554 static void register_subpage(FlatView
*fv
, MemoryRegionSection
*section
)
1556 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1558 hwaddr base
= section
->offset_within_address_space
1560 MemoryRegionSection
*existing
= phys_page_find(d
, base
);
1561 MemoryRegionSection subsection
= {
1562 .offset_within_address_space
= base
,
1563 .size
= int128_make64(TARGET_PAGE_SIZE
),
1567 assert(existing
->mr
->subpage
|| existing
->mr
== &io_mem_unassigned
);
1569 if (!(existing
->mr
->subpage
)) {
1570 subpage
= subpage_init(fv
, base
);
1572 subsection
.mr
= &subpage
->iomem
;
1573 phys_page_set(d
, base
>> TARGET_PAGE_BITS
, 1,
1574 phys_section_add(&d
->map
, &subsection
));
1576 subpage
= container_of(existing
->mr
, subpage_t
, iomem
);
1578 start
= section
->offset_within_address_space
& ~TARGET_PAGE_MASK
;
1579 end
= start
+ int128_get64(section
->size
) - 1;
1580 subpage_register(subpage
, start
, end
,
1581 phys_section_add(&d
->map
, section
));
1585 static void register_multipage(FlatView
*fv
,
1586 MemoryRegionSection
*section
)
1588 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1589 hwaddr start_addr
= section
->offset_within_address_space
;
1590 uint16_t section_index
= phys_section_add(&d
->map
, section
);
1591 uint64_t num_pages
= int128_get64(int128_rshift(section
->size
,
1595 phys_page_set(d
, start_addr
>> TARGET_PAGE_BITS
, num_pages
, section_index
);
1599 * The range in *section* may look like this:
1603 * where s stands for subpage and P for page.
1605 void flatview_add_to_dispatch(FlatView
*fv
, MemoryRegionSection
*section
)
1607 MemoryRegionSection remain
= *section
;
1608 Int128 page_size
= int128_make64(TARGET_PAGE_SIZE
);
1610 /* register first subpage */
1611 if (remain
.offset_within_address_space
& ~TARGET_PAGE_MASK
) {
1612 uint64_t left
= TARGET_PAGE_ALIGN(remain
.offset_within_address_space
)
1613 - remain
.offset_within_address_space
;
1615 MemoryRegionSection now
= remain
;
1616 now
.size
= int128_min(int128_make64(left
), now
.size
);
1617 register_subpage(fv
, &now
);
1618 if (int128_eq(remain
.size
, now
.size
)) {
1621 remain
.size
= int128_sub(remain
.size
, now
.size
);
1622 remain
.offset_within_address_space
+= int128_get64(now
.size
);
1623 remain
.offset_within_region
+= int128_get64(now
.size
);
1626 /* register whole pages */
1627 if (int128_ge(remain
.size
, page_size
)) {
1628 MemoryRegionSection now
= remain
;
1629 now
.size
= int128_and(now
.size
, int128_neg(page_size
));
1630 register_multipage(fv
, &now
);
1631 if (int128_eq(remain
.size
, now
.size
)) {
1634 remain
.size
= int128_sub(remain
.size
, now
.size
);
1635 remain
.offset_within_address_space
+= int128_get64(now
.size
);
1636 remain
.offset_within_region
+= int128_get64(now
.size
);
1639 /* register last subpage */
1640 register_subpage(fv
, &remain
);
1643 void qemu_flush_coalesced_mmio_buffer(void)
1646 kvm_flush_coalesced_mmio_buffer();
1649 void qemu_mutex_lock_ramlist(void)
1651 qemu_mutex_lock(&ram_list
.mutex
);
1654 void qemu_mutex_unlock_ramlist(void)
1656 qemu_mutex_unlock(&ram_list
.mutex
);
1659 void ram_block_dump(Monitor
*mon
)
1665 monitor_printf(mon
, "%24s %8s %18s %18s %18s\n",
1666 "Block Name", "PSize", "Offset", "Used", "Total");
1667 RAMBLOCK_FOREACH(block
) {
1668 psize
= size_to_str(block
->page_size
);
1669 monitor_printf(mon
, "%24s %8s 0x%016" PRIx64
" 0x%016" PRIx64
1670 " 0x%016" PRIx64
"\n", block
->idstr
, psize
,
1671 (uint64_t)block
->offset
,
1672 (uint64_t)block
->used_length
,
1673 (uint64_t)block
->max_length
);
1681 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1682 * may or may not name the same files / on the same filesystem now as
1683 * when we actually open and map them. Iterate over the file
1684 * descriptors instead, and use qemu_fd_getpagesize().
1686 static int find_min_backend_pagesize(Object
*obj
, void *opaque
)
1688 long *hpsize_min
= opaque
;
1690 if (object_dynamic_cast(obj
, TYPE_MEMORY_BACKEND
)) {
1691 HostMemoryBackend
*backend
= MEMORY_BACKEND(obj
);
1692 long hpsize
= host_memory_backend_pagesize(backend
);
1694 if (host_memory_backend_is_mapped(backend
) && (hpsize
< *hpsize_min
)) {
1695 *hpsize_min
= hpsize
;
1702 static int find_max_backend_pagesize(Object
*obj
, void *opaque
)
1704 long *hpsize_max
= opaque
;
1706 if (object_dynamic_cast(obj
, TYPE_MEMORY_BACKEND
)) {
1707 HostMemoryBackend
*backend
= MEMORY_BACKEND(obj
);
1708 long hpsize
= host_memory_backend_pagesize(backend
);
1710 if (host_memory_backend_is_mapped(backend
) && (hpsize
> *hpsize_max
)) {
1711 *hpsize_max
= hpsize
;
1719 * TODO: We assume right now that all mapped host memory backends are
1720 * used as RAM, however some might be used for different purposes.
1722 long qemu_minrampagesize(void)
1724 long hpsize
= LONG_MAX
;
1725 long mainrampagesize
;
1726 Object
*memdev_root
;
1727 MachineState
*ms
= MACHINE(qdev_get_machine());
1729 mainrampagesize
= qemu_mempath_getpagesize(mem_path
);
1731 /* it's possible we have memory-backend objects with
1732 * hugepage-backed RAM. these may get mapped into system
1733 * address space via -numa parameters or memory hotplug
1734 * hooks. we want to take these into account, but we
1735 * also want to make sure these supported hugepage
1736 * sizes are applicable across the entire range of memory
1737 * we may boot from, so we take the min across all
1738 * backends, and assume normal pages in cases where a
1739 * backend isn't backed by hugepages.
1741 memdev_root
= object_resolve_path("/objects", NULL
);
1743 object_child_foreach(memdev_root
, find_min_backend_pagesize
, &hpsize
);
1745 if (hpsize
== LONG_MAX
) {
1746 /* No additional memory regions found ==> Report main RAM page size */
1747 return mainrampagesize
;
1750 /* If NUMA is disabled or the NUMA nodes are not backed with a
1751 * memory-backend, then there is at least one node using "normal" RAM,
1752 * so if its page size is smaller we have got to report that size instead.
1754 if (hpsize
> mainrampagesize
&&
1755 (ms
->numa_state
== NULL
||
1756 ms
->numa_state
->num_nodes
== 0 ||
1757 ms
->numa_state
->nodes
[0].node_memdev
== NULL
)) {
1760 error_report("Huge page support disabled (n/a for main memory).");
1763 return mainrampagesize
;
1769 long qemu_maxrampagesize(void)
1771 long pagesize
= qemu_mempath_getpagesize(mem_path
);
1772 Object
*memdev_root
= object_resolve_path("/objects", NULL
);
1775 object_child_foreach(memdev_root
, find_max_backend_pagesize
,
1781 long qemu_minrampagesize(void)
1783 return getpagesize();
1785 long qemu_maxrampagesize(void)
1787 return getpagesize();
1792 static int64_t get_file_size(int fd
)
1795 #if defined(__linux__)
1798 if (fstat(fd
, &st
) < 0) {
1802 /* Special handling for devdax character devices */
1803 if (S_ISCHR(st
.st_mode
)) {
1804 g_autofree
char *subsystem_path
= NULL
;
1805 g_autofree
char *subsystem
= NULL
;
1807 subsystem_path
= g_strdup_printf("/sys/dev/char/%d:%d/subsystem",
1808 major(st
.st_rdev
), minor(st
.st_rdev
));
1809 subsystem
= g_file_read_link(subsystem_path
, NULL
);
1811 if (subsystem
&& g_str_has_suffix(subsystem
, "/dax")) {
1812 g_autofree
char *size_path
= NULL
;
1813 g_autofree
char *size_str
= NULL
;
1815 size_path
= g_strdup_printf("/sys/dev/char/%d:%d/size",
1816 major(st
.st_rdev
), minor(st
.st_rdev
));
1818 if (g_file_get_contents(size_path
, &size_str
, NULL
, NULL
)) {
1819 return g_ascii_strtoll(size_str
, NULL
, 0);
1823 #endif /* defined(__linux__) */
1825 /* st.st_size may be zero for special files yet lseek(2) works */
1826 size
= lseek(fd
, 0, SEEK_END
);
1833 static int file_ram_open(const char *path
,
1834 const char *region_name
,
1839 char *sanitized_name
;
1845 fd
= open(path
, O_RDWR
);
1847 /* @path names an existing file, use it */
1850 if (errno
== ENOENT
) {
1851 /* @path names a file that doesn't exist, create it */
1852 fd
= open(path
, O_RDWR
| O_CREAT
| O_EXCL
, 0644);
1857 } else if (errno
== EISDIR
) {
1858 /* @path names a directory, create a file there */
1859 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1860 sanitized_name
= g_strdup(region_name
);
1861 for (c
= sanitized_name
; *c
!= '\0'; c
++) {
1867 filename
= g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path
,
1869 g_free(sanitized_name
);
1871 fd
= mkstemp(filename
);
1879 if (errno
!= EEXIST
&& errno
!= EINTR
) {
1880 error_setg_errno(errp
, errno
,
1881 "can't open backing store %s for guest RAM",
1886 * Try again on EINTR and EEXIST. The latter happens when
1887 * something else creates the file between our two open().
1894 static void *file_ram_alloc(RAMBlock
*block
,
1900 MachineState
*ms
= MACHINE(qdev_get_machine());
1903 block
->page_size
= qemu_fd_getpagesize(fd
);
1904 if (block
->mr
->align
% block
->page_size
) {
1905 error_setg(errp
, "alignment 0x%" PRIx64
1906 " must be multiples of page size 0x%zx",
1907 block
->mr
->align
, block
->page_size
);
1909 } else if (block
->mr
->align
&& !is_power_of_2(block
->mr
->align
)) {
1910 error_setg(errp
, "alignment 0x%" PRIx64
1911 " must be a power of two", block
->mr
->align
);
1914 block
->mr
->align
= MAX(block
->page_size
, block
->mr
->align
);
1915 #if defined(__s390x__)
1916 if (kvm_enabled()) {
1917 block
->mr
->align
= MAX(block
->mr
->align
, QEMU_VMALLOC_ALIGN
);
1921 if (memory
< block
->page_size
) {
1922 error_setg(errp
, "memory size 0x" RAM_ADDR_FMT
" must be equal to "
1923 "or larger than page size 0x%zx",
1924 memory
, block
->page_size
);
1928 memory
= ROUND_UP(memory
, block
->page_size
);
1931 * ftruncate is not supported by hugetlbfs in older
1932 * hosts, so don't bother bailing out on errors.
1933 * If anything goes wrong with it under other filesystems,
1936 * Do not truncate the non-empty backend file to avoid corrupting
1937 * the existing data in the file. Disabling shrinking is not
1938 * enough. For example, the current vNVDIMM implementation stores
1939 * the guest NVDIMM labels at the end of the backend file. If the
1940 * backend file is later extended, QEMU will not be able to find
1941 * those labels. Therefore, extending the non-empty backend file
1942 * is disabled as well.
1944 if (truncate
&& ftruncate(fd
, memory
)) {
1945 perror("ftruncate");
1948 area
= qemu_ram_mmap(fd
, memory
, block
->mr
->align
,
1949 block
->flags
& RAM_SHARED
, block
->flags
& RAM_PMEM
);
1950 if (area
== MAP_FAILED
) {
1951 error_setg_errno(errp
, errno
,
1952 "unable to map backing store for guest RAM");
1957 os_mem_prealloc(fd
, area
, memory
, ms
->smp
.cpus
, errp
);
1958 if (errp
&& *errp
) {
1959 qemu_ram_munmap(fd
, area
, memory
);
1969 /* Allocate space within the ram_addr_t space that governs the
1971 * Called with the ramlist lock held.
1973 static ram_addr_t
find_ram_offset(ram_addr_t size
)
1975 RAMBlock
*block
, *next_block
;
1976 ram_addr_t offset
= RAM_ADDR_MAX
, mingap
= RAM_ADDR_MAX
;
1978 assert(size
!= 0); /* it would hand out same offset multiple times */
1980 if (QLIST_EMPTY_RCU(&ram_list
.blocks
)) {
1984 RAMBLOCK_FOREACH(block
) {
1985 ram_addr_t candidate
, next
= RAM_ADDR_MAX
;
1987 /* Align blocks to start on a 'long' in the bitmap
1988 * which makes the bitmap sync'ing take the fast path.
1990 candidate
= block
->offset
+ block
->max_length
;
1991 candidate
= ROUND_UP(candidate
, BITS_PER_LONG
<< TARGET_PAGE_BITS
);
1993 /* Search for the closest following block
1996 RAMBLOCK_FOREACH(next_block
) {
1997 if (next_block
->offset
>= candidate
) {
1998 next
= MIN(next
, next_block
->offset
);
2002 /* If it fits remember our place and remember the size
2003 * of gap, but keep going so that we might find a smaller
2004 * gap to fill so avoiding fragmentation.
2006 if (next
- candidate
>= size
&& next
- candidate
< mingap
) {
2008 mingap
= next
- candidate
;
2011 trace_find_ram_offset_loop(size
, candidate
, offset
, next
, mingap
);
2014 if (offset
== RAM_ADDR_MAX
) {
2015 fprintf(stderr
, "Failed to find gap of requested size: %" PRIu64
"\n",
2020 trace_find_ram_offset(size
, offset
);
2025 static unsigned long last_ram_page(void)
2028 ram_addr_t last
= 0;
2031 RAMBLOCK_FOREACH(block
) {
2032 last
= MAX(last
, block
->offset
+ block
->max_length
);
2035 return last
>> TARGET_PAGE_BITS
;
2038 static void qemu_ram_setup_dump(void *addr
, ram_addr_t size
)
2042 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
2043 if (!machine_dump_guest_core(current_machine
)) {
2044 ret
= qemu_madvise(addr
, size
, QEMU_MADV_DONTDUMP
);
2046 perror("qemu_madvise");
2047 fprintf(stderr
, "madvise doesn't support MADV_DONTDUMP, "
2048 "but dump_guest_core=off specified\n");
2053 const char *qemu_ram_get_idstr(RAMBlock
*rb
)
2058 void *qemu_ram_get_host_addr(RAMBlock
*rb
)
2063 ram_addr_t
qemu_ram_get_offset(RAMBlock
*rb
)
2068 ram_addr_t
qemu_ram_get_used_length(RAMBlock
*rb
)
2070 return rb
->used_length
;
2073 bool qemu_ram_is_shared(RAMBlock
*rb
)
2075 return rb
->flags
& RAM_SHARED
;
2078 /* Note: Only set at the start of postcopy */
2079 bool qemu_ram_is_uf_zeroable(RAMBlock
*rb
)
2081 return rb
->flags
& RAM_UF_ZEROPAGE
;
2084 void qemu_ram_set_uf_zeroable(RAMBlock
*rb
)
2086 rb
->flags
|= RAM_UF_ZEROPAGE
;
2089 bool qemu_ram_is_migratable(RAMBlock
*rb
)
2091 return rb
->flags
& RAM_MIGRATABLE
;
2094 void qemu_ram_set_migratable(RAMBlock
*rb
)
2096 rb
->flags
|= RAM_MIGRATABLE
;
2099 void qemu_ram_unset_migratable(RAMBlock
*rb
)
2101 rb
->flags
&= ~RAM_MIGRATABLE
;
2104 /* Called with iothread lock held. */
2105 void qemu_ram_set_idstr(RAMBlock
*new_block
, const char *name
, DeviceState
*dev
)
2110 assert(!new_block
->idstr
[0]);
2113 char *id
= qdev_get_dev_path(dev
);
2115 snprintf(new_block
->idstr
, sizeof(new_block
->idstr
), "%s/", id
);
2119 pstrcat(new_block
->idstr
, sizeof(new_block
->idstr
), name
);
2122 RAMBLOCK_FOREACH(block
) {
2123 if (block
!= new_block
&&
2124 !strcmp(block
->idstr
, new_block
->idstr
)) {
2125 fprintf(stderr
, "RAMBlock \"%s\" already registered, abort!\n",
2133 /* Called with iothread lock held. */
2134 void qemu_ram_unset_idstr(RAMBlock
*block
)
2136 /* FIXME: arch_init.c assumes that this is not called throughout
2137 * migration. Ignore the problem since hot-unplug during migration
2138 * does not work anyway.
2141 memset(block
->idstr
, 0, sizeof(block
->idstr
));
2145 size_t qemu_ram_pagesize(RAMBlock
*rb
)
2147 return rb
->page_size
;
2150 /* Returns the largest size of page in use */
2151 size_t qemu_ram_pagesize_largest(void)
2156 RAMBLOCK_FOREACH(block
) {
2157 largest
= MAX(largest
, qemu_ram_pagesize(block
));
2163 static int memory_try_enable_merging(void *addr
, size_t len
)
2165 if (!machine_mem_merge(current_machine
)) {
2166 /* disabled by the user */
2170 return qemu_madvise(addr
, len
, QEMU_MADV_MERGEABLE
);
2173 /* Only legal before guest might have detected the memory size: e.g. on
2174 * incoming migration, or right after reset.
2176 * As memory core doesn't know how is memory accessed, it is up to
2177 * resize callback to update device state and/or add assertions to detect
2178 * misuse, if necessary.
2180 int qemu_ram_resize(RAMBlock
*block
, ram_addr_t newsize
, Error
**errp
)
2184 newsize
= HOST_PAGE_ALIGN(newsize
);
2186 if (block
->used_length
== newsize
) {
2190 if (!(block
->flags
& RAM_RESIZEABLE
)) {
2191 error_setg_errno(errp
, EINVAL
,
2192 "Length mismatch: %s: 0x" RAM_ADDR_FMT
2193 " in != 0x" RAM_ADDR_FMT
, block
->idstr
,
2194 newsize
, block
->used_length
);
2198 if (block
->max_length
< newsize
) {
2199 error_setg_errno(errp
, EINVAL
,
2200 "Length too large: %s: 0x" RAM_ADDR_FMT
2201 " > 0x" RAM_ADDR_FMT
, block
->idstr
,
2202 newsize
, block
->max_length
);
2206 cpu_physical_memory_clear_dirty_range(block
->offset
, block
->used_length
);
2207 block
->used_length
= newsize
;
2208 cpu_physical_memory_set_dirty_range(block
->offset
, block
->used_length
,
2210 memory_region_set_size(block
->mr
, newsize
);
2211 if (block
->resized
) {
2212 block
->resized(block
->idstr
, newsize
, block
->host
);
2217 /* Called with ram_list.mutex held */
2218 static void dirty_memory_extend(ram_addr_t old_ram_size
,
2219 ram_addr_t new_ram_size
)
2221 ram_addr_t old_num_blocks
= DIV_ROUND_UP(old_ram_size
,
2222 DIRTY_MEMORY_BLOCK_SIZE
);
2223 ram_addr_t new_num_blocks
= DIV_ROUND_UP(new_ram_size
,
2224 DIRTY_MEMORY_BLOCK_SIZE
);
2227 /* Only need to extend if block count increased */
2228 if (new_num_blocks
<= old_num_blocks
) {
2232 for (i
= 0; i
< DIRTY_MEMORY_NUM
; i
++) {
2233 DirtyMemoryBlocks
*old_blocks
;
2234 DirtyMemoryBlocks
*new_blocks
;
2237 old_blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[i
]);
2238 new_blocks
= g_malloc(sizeof(*new_blocks
) +
2239 sizeof(new_blocks
->blocks
[0]) * new_num_blocks
);
2241 if (old_num_blocks
) {
2242 memcpy(new_blocks
->blocks
, old_blocks
->blocks
,
2243 old_num_blocks
* sizeof(old_blocks
->blocks
[0]));
2246 for (j
= old_num_blocks
; j
< new_num_blocks
; j
++) {
2247 new_blocks
->blocks
[j
] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE
);
2250 atomic_rcu_set(&ram_list
.dirty_memory
[i
], new_blocks
);
2253 g_free_rcu(old_blocks
, rcu
);
2258 static void ram_block_add(RAMBlock
*new_block
, Error
**errp
, bool shared
)
2261 RAMBlock
*last_block
= NULL
;
2262 ram_addr_t old_ram_size
, new_ram_size
;
2265 old_ram_size
= last_ram_page();
2267 qemu_mutex_lock_ramlist();
2268 new_block
->offset
= find_ram_offset(new_block
->max_length
);
2270 if (!new_block
->host
) {
2271 if (xen_enabled()) {
2272 xen_ram_alloc(new_block
->offset
, new_block
->max_length
,
2273 new_block
->mr
, &err
);
2275 error_propagate(errp
, err
);
2276 qemu_mutex_unlock_ramlist();
2280 new_block
->host
= phys_mem_alloc(new_block
->max_length
,
2281 &new_block
->mr
->align
, shared
);
2282 if (!new_block
->host
) {
2283 error_setg_errno(errp
, errno
,
2284 "cannot set up guest memory '%s'",
2285 memory_region_name(new_block
->mr
));
2286 qemu_mutex_unlock_ramlist();
2289 memory_try_enable_merging(new_block
->host
, new_block
->max_length
);
2293 new_ram_size
= MAX(old_ram_size
,
2294 (new_block
->offset
+ new_block
->max_length
) >> TARGET_PAGE_BITS
);
2295 if (new_ram_size
> old_ram_size
) {
2296 dirty_memory_extend(old_ram_size
, new_ram_size
);
2298 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
2299 * QLIST (which has an RCU-friendly variant) does not have insertion at
2300 * tail, so save the last element in last_block.
2302 RAMBLOCK_FOREACH(block
) {
2304 if (block
->max_length
< new_block
->max_length
) {
2309 QLIST_INSERT_BEFORE_RCU(block
, new_block
, next
);
2310 } else if (last_block
) {
2311 QLIST_INSERT_AFTER_RCU(last_block
, new_block
, next
);
2312 } else { /* list is empty */
2313 QLIST_INSERT_HEAD_RCU(&ram_list
.blocks
, new_block
, next
);
2315 ram_list
.mru_block
= NULL
;
2317 /* Write list before version */
2320 qemu_mutex_unlock_ramlist();
2322 cpu_physical_memory_set_dirty_range(new_block
->offset
,
2323 new_block
->used_length
,
2326 if (new_block
->host
) {
2327 qemu_ram_setup_dump(new_block
->host
, new_block
->max_length
);
2328 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_HUGEPAGE
);
2329 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
2330 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_DONTFORK
);
2331 ram_block_notify_add(new_block
->host
, new_block
->max_length
);
2336 RAMBlock
*qemu_ram_alloc_from_fd(ram_addr_t size
, MemoryRegion
*mr
,
2337 uint32_t ram_flags
, int fd
,
2340 RAMBlock
*new_block
;
2341 Error
*local_err
= NULL
;
2344 /* Just support these ram flags by now. */
2345 assert((ram_flags
& ~(RAM_SHARED
| RAM_PMEM
)) == 0);
2347 if (xen_enabled()) {
2348 error_setg(errp
, "-mem-path not supported with Xen");
2352 if (kvm_enabled() && !kvm_has_sync_mmu()) {
2354 "host lacks kvm mmu notifiers, -mem-path unsupported");
2358 if (phys_mem_alloc
!= qemu_anon_ram_alloc
) {
2360 * file_ram_alloc() needs to allocate just like
2361 * phys_mem_alloc, but we haven't bothered to provide
2365 "-mem-path not supported with this accelerator");
2369 size
= HOST_PAGE_ALIGN(size
);
2370 file_size
= get_file_size(fd
);
2371 if (file_size
> 0 && file_size
< size
) {
2372 error_setg(errp
, "backing store %s size 0x%" PRIx64
2373 " does not match 'size' option 0x" RAM_ADDR_FMT
,
2374 mem_path
, file_size
, size
);
2378 new_block
= g_malloc0(sizeof(*new_block
));
2380 new_block
->used_length
= size
;
2381 new_block
->max_length
= size
;
2382 new_block
->flags
= ram_flags
;
2383 new_block
->host
= file_ram_alloc(new_block
, size
, fd
, !file_size
, errp
);
2384 if (!new_block
->host
) {
2389 ram_block_add(new_block
, &local_err
, ram_flags
& RAM_SHARED
);
2392 error_propagate(errp
, local_err
);
2400 RAMBlock
*qemu_ram_alloc_from_file(ram_addr_t size
, MemoryRegion
*mr
,
2401 uint32_t ram_flags
, const char *mem_path
,
2408 fd
= file_ram_open(mem_path
, memory_region_name(mr
), &created
, errp
);
2413 block
= qemu_ram_alloc_from_fd(size
, mr
, ram_flags
, fd
, errp
);
2427 RAMBlock
*qemu_ram_alloc_internal(ram_addr_t size
, ram_addr_t max_size
,
2428 void (*resized
)(const char*,
2431 void *host
, bool resizeable
, bool share
,
2432 MemoryRegion
*mr
, Error
**errp
)
2434 RAMBlock
*new_block
;
2435 Error
*local_err
= NULL
;
2437 size
= HOST_PAGE_ALIGN(size
);
2438 max_size
= HOST_PAGE_ALIGN(max_size
);
2439 new_block
= g_malloc0(sizeof(*new_block
));
2441 new_block
->resized
= resized
;
2442 new_block
->used_length
= size
;
2443 new_block
->max_length
= max_size
;
2444 assert(max_size
>= size
);
2446 new_block
->page_size
= getpagesize();
2447 new_block
->host
= host
;
2449 new_block
->flags
|= RAM_PREALLOC
;
2452 new_block
->flags
|= RAM_RESIZEABLE
;
2454 ram_block_add(new_block
, &local_err
, share
);
2457 error_propagate(errp
, local_err
);
2463 RAMBlock
*qemu_ram_alloc_from_ptr(ram_addr_t size
, void *host
,
2464 MemoryRegion
*mr
, Error
**errp
)
2466 return qemu_ram_alloc_internal(size
, size
, NULL
, host
, false,
2470 RAMBlock
*qemu_ram_alloc(ram_addr_t size
, bool share
,
2471 MemoryRegion
*mr
, Error
**errp
)
2473 return qemu_ram_alloc_internal(size
, size
, NULL
, NULL
, false,
2477 RAMBlock
*qemu_ram_alloc_resizeable(ram_addr_t size
, ram_addr_t maxsz
,
2478 void (*resized
)(const char*,
2481 MemoryRegion
*mr
, Error
**errp
)
2483 return qemu_ram_alloc_internal(size
, maxsz
, resized
, NULL
, true,
2487 static void reclaim_ramblock(RAMBlock
*block
)
2489 if (block
->flags
& RAM_PREALLOC
) {
2491 } else if (xen_enabled()) {
2492 xen_invalidate_map_cache_entry(block
->host
);
2494 } else if (block
->fd
>= 0) {
2495 qemu_ram_munmap(block
->fd
, block
->host
, block
->max_length
);
2499 qemu_anon_ram_free(block
->host
, block
->max_length
);
2504 void qemu_ram_free(RAMBlock
*block
)
2511 ram_block_notify_remove(block
->host
, block
->max_length
);
2514 qemu_mutex_lock_ramlist();
2515 QLIST_REMOVE_RCU(block
, next
);
2516 ram_list
.mru_block
= NULL
;
2517 /* Write list before version */
2520 call_rcu(block
, reclaim_ramblock
, rcu
);
2521 qemu_mutex_unlock_ramlist();
2525 void qemu_ram_remap(ram_addr_t addr
, ram_addr_t length
)
2532 RAMBLOCK_FOREACH(block
) {
2533 offset
= addr
- block
->offset
;
2534 if (offset
< block
->max_length
) {
2535 vaddr
= ramblock_ptr(block
, offset
);
2536 if (block
->flags
& RAM_PREALLOC
) {
2538 } else if (xen_enabled()) {
2542 if (block
->fd
>= 0) {
2543 flags
|= (block
->flags
& RAM_SHARED
?
2544 MAP_SHARED
: MAP_PRIVATE
);
2545 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2546 flags
, block
->fd
, offset
);
2549 * Remap needs to match alloc. Accelerators that
2550 * set phys_mem_alloc never remap. If they did,
2551 * we'd need a remap hook here.
2553 assert(phys_mem_alloc
== qemu_anon_ram_alloc
);
2555 flags
|= MAP_PRIVATE
| MAP_ANONYMOUS
;
2556 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2559 if (area
!= vaddr
) {
2560 error_report("Could not remap addr: "
2561 RAM_ADDR_FMT
"@" RAM_ADDR_FMT
"",
2565 memory_try_enable_merging(vaddr
, length
);
2566 qemu_ram_setup_dump(vaddr
, length
);
2571 #endif /* !_WIN32 */
2573 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2574 * This should not be used for general purpose DMA. Use address_space_map
2575 * or address_space_rw instead. For local memory (e.g. video ram) that the
2576 * device owns, use memory_region_get_ram_ptr.
2578 * Called within RCU critical section.
2580 void *qemu_map_ram_ptr(RAMBlock
*ram_block
, ram_addr_t addr
)
2582 RAMBlock
*block
= ram_block
;
2584 if (block
== NULL
) {
2585 block
= qemu_get_ram_block(addr
);
2586 addr
-= block
->offset
;
2589 if (xen_enabled() && block
->host
== NULL
) {
2590 /* We need to check if the requested address is in the RAM
2591 * because we don't want to map the entire memory in QEMU.
2592 * In that case just map until the end of the page.
2594 if (block
->offset
== 0) {
2595 return xen_map_cache(addr
, 0, 0, false);
2598 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, false);
2600 return ramblock_ptr(block
, addr
);
2603 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2604 * but takes a size argument.
2606 * Called within RCU critical section.
2608 static void *qemu_ram_ptr_length(RAMBlock
*ram_block
, ram_addr_t addr
,
2609 hwaddr
*size
, bool lock
)
2611 RAMBlock
*block
= ram_block
;
2616 if (block
== NULL
) {
2617 block
= qemu_get_ram_block(addr
);
2618 addr
-= block
->offset
;
2620 *size
= MIN(*size
, block
->max_length
- addr
);
2622 if (xen_enabled() && block
->host
== NULL
) {
2623 /* We need to check if the requested address is in the RAM
2624 * because we don't want to map the entire memory in QEMU.
2625 * In that case just map the requested area.
2627 if (block
->offset
== 0) {
2628 return xen_map_cache(addr
, *size
, lock
, lock
);
2631 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, lock
);
2634 return ramblock_ptr(block
, addr
);
2637 /* Return the offset of a hostpointer within a ramblock */
2638 ram_addr_t
qemu_ram_block_host_offset(RAMBlock
*rb
, void *host
)
2640 ram_addr_t res
= (uint8_t *)host
- (uint8_t *)rb
->host
;
2641 assert((uintptr_t)host
>= (uintptr_t)rb
->host
);
2642 assert(res
< rb
->max_length
);
2648 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2651 * ptr: Host pointer to look up
2652 * round_offset: If true round the result offset down to a page boundary
2653 * *ram_addr: set to result ram_addr
2654 * *offset: set to result offset within the RAMBlock
2656 * Returns: RAMBlock (or NULL if not found)
2658 * By the time this function returns, the returned pointer is not protected
2659 * by RCU anymore. If the caller is not within an RCU critical section and
2660 * does not hold the iothread lock, it must have other means of protecting the
2661 * pointer, such as a reference to the region that includes the incoming
2664 RAMBlock
*qemu_ram_block_from_host(void *ptr
, bool round_offset
,
2668 uint8_t *host
= ptr
;
2670 if (xen_enabled()) {
2671 ram_addr_t ram_addr
;
2673 ram_addr
= xen_ram_addr_from_mapcache(ptr
);
2674 block
= qemu_get_ram_block(ram_addr
);
2676 *offset
= ram_addr
- block
->offset
;
2683 block
= atomic_rcu_read(&ram_list
.mru_block
);
2684 if (block
&& block
->host
&& host
- block
->host
< block
->max_length
) {
2688 RAMBLOCK_FOREACH(block
) {
2689 /* This case append when the block is not mapped. */
2690 if (block
->host
== NULL
) {
2693 if (host
- block
->host
< block
->max_length
) {
2702 *offset
= (host
- block
->host
);
2704 *offset
&= TARGET_PAGE_MASK
;
2711 * Finds the named RAMBlock
2713 * name: The name of RAMBlock to find
2715 * Returns: RAMBlock (or NULL if not found)
2717 RAMBlock
*qemu_ram_block_by_name(const char *name
)
2721 RAMBLOCK_FOREACH(block
) {
2722 if (!strcmp(name
, block
->idstr
)) {
2730 /* Some of the softmmu routines need to translate from a host pointer
2731 (typically a TLB entry) back to a ram offset. */
2732 ram_addr_t
qemu_ram_addr_from_host(void *ptr
)
2737 block
= qemu_ram_block_from_host(ptr
, false, &offset
);
2739 return RAM_ADDR_INVALID
;
2742 return block
->offset
+ offset
;
2745 /* Called within RCU critical section. */
2746 void memory_notdirty_write_prepare(NotDirtyInfo
*ndi
,
2749 ram_addr_t ram_addr
,
2753 ndi
->ram_addr
= ram_addr
;
2754 ndi
->mem_vaddr
= mem_vaddr
;
2758 trace_memory_notdirty_write_access(mem_vaddr
, ram_addr
, size
);
2760 assert(tcg_enabled());
2761 if (!cpu_physical_memory_get_dirty_flag(ram_addr
, DIRTY_MEMORY_CODE
)) {
2762 ndi
->pages
= page_collection_lock(ram_addr
, ram_addr
+ size
);
2763 tb_invalidate_phys_page_fast(ndi
->pages
, ram_addr
, size
);
2767 /* Called within RCU critical section. */
2768 void memory_notdirty_write_complete(NotDirtyInfo
*ndi
)
2771 assert(tcg_enabled());
2772 page_collection_unlock(ndi
->pages
);
2776 /* Set both VGA and migration bits for simplicity and to remove
2777 * the notdirty callback faster.
2779 cpu_physical_memory_set_dirty_range(ndi
->ram_addr
, ndi
->size
,
2780 DIRTY_CLIENTS_NOCODE
);
2781 /* we remove the notdirty callback only if the code has been
2783 if (!cpu_physical_memory_is_clean(ndi
->ram_addr
)) {
2784 trace_memory_notdirty_set_dirty(ndi
->mem_vaddr
);
2785 tlb_set_dirty(ndi
->cpu
, ndi
->mem_vaddr
);
2789 /* Called within RCU critical section. */
2790 static void notdirty_mem_write(void *opaque
, hwaddr ram_addr
,
2791 uint64_t val
, unsigned size
)
2795 memory_notdirty_write_prepare(&ndi
, current_cpu
, current_cpu
->mem_io_vaddr
,
2798 stn_p(qemu_map_ram_ptr(NULL
, ram_addr
), size
, val
);
2799 memory_notdirty_write_complete(&ndi
);
2802 static bool notdirty_mem_accepts(void *opaque
, hwaddr addr
,
2803 unsigned size
, bool is_write
,
2809 static const MemoryRegionOps notdirty_mem_ops
= {
2810 .write
= notdirty_mem_write
,
2811 .valid
.accepts
= notdirty_mem_accepts
,
2812 .endianness
= DEVICE_NATIVE_ENDIAN
,
2814 .min_access_size
= 1,
2815 .max_access_size
= 8,
2819 .min_access_size
= 1,
2820 .max_access_size
= 8,
2825 /* Generate a debug exception if a watchpoint has been hit. */
2826 void cpu_check_watchpoint(CPUState
*cpu
, vaddr addr
, vaddr len
,
2827 MemTxAttrs attrs
, int flags
, uintptr_t ra
)
2829 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
2832 assert(tcg_enabled());
2833 if (cpu
->watchpoint_hit
) {
2835 * We re-entered the check after replacing the TB.
2836 * Now raise the debug interrupt so that it will
2837 * trigger after the current instruction.
2839 qemu_mutex_lock_iothread();
2840 cpu_interrupt(cpu
, CPU_INTERRUPT_DEBUG
);
2841 qemu_mutex_unlock_iothread();
2845 addr
= cc
->adjust_watchpoint_address(cpu
, addr
, len
);
2846 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
2847 if (watchpoint_address_matches(wp
, addr
, len
)
2848 && (wp
->flags
& flags
)) {
2849 if (flags
== BP_MEM_READ
) {
2850 wp
->flags
|= BP_WATCHPOINT_HIT_READ
;
2852 wp
->flags
|= BP_WATCHPOINT_HIT_WRITE
;
2854 wp
->hitaddr
= MAX(addr
, wp
->vaddr
);
2855 wp
->hitattrs
= attrs
;
2856 if (!cpu
->watchpoint_hit
) {
2857 if (wp
->flags
& BP_CPU
&&
2858 !cc
->debug_check_watchpoint(cpu
, wp
)) {
2859 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2862 cpu
->watchpoint_hit
= wp
;
2865 tb_check_watchpoint(cpu
);
2866 if (wp
->flags
& BP_STOP_BEFORE_ACCESS
) {
2867 cpu
->exception_index
= EXCP_DEBUG
;
2869 cpu_loop_exit_restore(cpu
, ra
);
2871 /* Force execution of one insn next time. */
2872 cpu
->cflags_next_tb
= 1 | curr_cflags();
2875 cpu_restore_state(cpu
, ra
, true);
2877 cpu_loop_exit_noexc(cpu
);
2881 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2886 static MemTxResult
flatview_read(FlatView
*fv
, hwaddr addr
,
2887 MemTxAttrs attrs
, uint8_t *buf
, hwaddr len
);
2888 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
2889 const uint8_t *buf
, hwaddr len
);
2890 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, hwaddr len
,
2891 bool is_write
, MemTxAttrs attrs
);
2893 static MemTxResult
subpage_read(void *opaque
, hwaddr addr
, uint64_t *data
,
2894 unsigned len
, MemTxAttrs attrs
)
2896 subpage_t
*subpage
= opaque
;
2900 #if defined(DEBUG_SUBPAGE)
2901 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
"\n", __func__
,
2902 subpage
, len
, addr
);
2904 res
= flatview_read(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2908 *data
= ldn_p(buf
, len
);
2912 static MemTxResult
subpage_write(void *opaque
, hwaddr addr
,
2913 uint64_t value
, unsigned len
, MemTxAttrs attrs
)
2915 subpage_t
*subpage
= opaque
;
2918 #if defined(DEBUG_SUBPAGE)
2919 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2920 " value %"PRIx64
"\n",
2921 __func__
, subpage
, len
, addr
, value
);
2923 stn_p(buf
, len
, value
);
2924 return flatview_write(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2927 static bool subpage_accepts(void *opaque
, hwaddr addr
,
2928 unsigned len
, bool is_write
,
2931 subpage_t
*subpage
= opaque
;
2932 #if defined(DEBUG_SUBPAGE)
2933 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx
"\n",
2934 __func__
, subpage
, is_write
? 'w' : 'r', len
, addr
);
2937 return flatview_access_valid(subpage
->fv
, addr
+ subpage
->base
,
2938 len
, is_write
, attrs
);
2941 static const MemoryRegionOps subpage_ops
= {
2942 .read_with_attrs
= subpage_read
,
2943 .write_with_attrs
= subpage_write
,
2944 .impl
.min_access_size
= 1,
2945 .impl
.max_access_size
= 8,
2946 .valid
.min_access_size
= 1,
2947 .valid
.max_access_size
= 8,
2948 .valid
.accepts
= subpage_accepts
,
2949 .endianness
= DEVICE_NATIVE_ENDIAN
,
2952 static int subpage_register(subpage_t
*mmio
, uint32_t start
, uint32_t end
,
2957 if (start
>= TARGET_PAGE_SIZE
|| end
>= TARGET_PAGE_SIZE
)
2959 idx
= SUBPAGE_IDX(start
);
2960 eidx
= SUBPAGE_IDX(end
);
2961 #if defined(DEBUG_SUBPAGE)
2962 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2963 __func__
, mmio
, start
, end
, idx
, eidx
, section
);
2965 for (; idx
<= eidx
; idx
++) {
2966 mmio
->sub_section
[idx
] = section
;
2972 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
)
2976 /* mmio->sub_section is set to PHYS_SECTION_UNASSIGNED with g_malloc0 */
2977 mmio
= g_malloc0(sizeof(subpage_t
) + TARGET_PAGE_SIZE
* sizeof(uint16_t));
2980 memory_region_init_io(&mmio
->iomem
, NULL
, &subpage_ops
, mmio
,
2981 NULL
, TARGET_PAGE_SIZE
);
2982 mmio
->iomem
.subpage
= true;
2983 #if defined(DEBUG_SUBPAGE)
2984 printf("%s: %p base " TARGET_FMT_plx
" len %08x\n", __func__
,
2985 mmio
, base
, TARGET_PAGE_SIZE
);
2991 static uint16_t dummy_section(PhysPageMap
*map
, FlatView
*fv
, MemoryRegion
*mr
)
2994 MemoryRegionSection section
= {
2997 .offset_within_address_space
= 0,
2998 .offset_within_region
= 0,
2999 .size
= int128_2_64(),
3002 return phys_section_add(map
, §ion
);
3005 static void readonly_mem_write(void *opaque
, hwaddr addr
,
3006 uint64_t val
, unsigned size
)
3008 /* Ignore any write to ROM. */
3011 static bool readonly_mem_accepts(void *opaque
, hwaddr addr
,
3012 unsigned size
, bool is_write
,
3018 /* This will only be used for writes, because reads are special cased
3019 * to directly access the underlying host ram.
3021 static const MemoryRegionOps readonly_mem_ops
= {
3022 .write
= readonly_mem_write
,
3023 .valid
.accepts
= readonly_mem_accepts
,
3024 .endianness
= DEVICE_NATIVE_ENDIAN
,
3026 .min_access_size
= 1,
3027 .max_access_size
= 8,
3031 .min_access_size
= 1,
3032 .max_access_size
= 8,
3037 MemoryRegionSection
*iotlb_to_section(CPUState
*cpu
,
3038 hwaddr index
, MemTxAttrs attrs
)
3040 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
3041 CPUAddressSpace
*cpuas
= &cpu
->cpu_ases
[asidx
];
3042 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpuas
->memory_dispatch
);
3043 MemoryRegionSection
*sections
= d
->map
.sections
;
3045 return §ions
[index
& ~TARGET_PAGE_MASK
];
3048 static void io_mem_init(void)
3050 memory_region_init_io(&io_mem_rom
, NULL
, &readonly_mem_ops
,
3051 NULL
, NULL
, UINT64_MAX
);
3052 memory_region_init_io(&io_mem_unassigned
, NULL
, &unassigned_mem_ops
, NULL
,
3055 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
3056 * which can be called without the iothread mutex.
3058 memory_region_init_io(&io_mem_notdirty
, NULL
, ¬dirty_mem_ops
, NULL
,
3060 memory_region_clear_global_locking(&io_mem_notdirty
);
3063 AddressSpaceDispatch
*address_space_dispatch_new(FlatView
*fv
)
3065 AddressSpaceDispatch
*d
= g_new0(AddressSpaceDispatch
, 1);
3068 n
= dummy_section(&d
->map
, fv
, &io_mem_unassigned
);
3069 assert(n
== PHYS_SECTION_UNASSIGNED
);
3070 n
= dummy_section(&d
->map
, fv
, &io_mem_notdirty
);
3071 assert(n
== PHYS_SECTION_NOTDIRTY
);
3072 n
= dummy_section(&d
->map
, fv
, &io_mem_rom
);
3073 assert(n
== PHYS_SECTION_ROM
);
3075 d
->phys_map
= (PhysPageEntry
) { .ptr
= PHYS_MAP_NODE_NIL
, .skip
= 1 };
3080 void address_space_dispatch_free(AddressSpaceDispatch
*d
)
3082 phys_sections_free(&d
->map
);
3086 static void do_nothing(CPUState
*cpu
, run_on_cpu_data d
)
3090 static void tcg_log_global_after_sync(MemoryListener
*listener
)
3092 CPUAddressSpace
*cpuas
;
3094 /* Wait for the CPU to end the current TB. This avoids the following
3098 * ---------------------- -------------------------
3099 * TLB check -> slow path
3100 * notdirty_mem_write
3104 * TLB check -> fast path
3108 * by pushing the migration thread's memory read after the vCPU thread has
3109 * written the memory.
3111 cpuas
= container_of(listener
, CPUAddressSpace
, tcg_as_listener
);
3112 run_on_cpu(cpuas
->cpu
, do_nothing
, RUN_ON_CPU_NULL
);
3115 static void tcg_commit(MemoryListener
*listener
)
3117 CPUAddressSpace
*cpuas
;
3118 AddressSpaceDispatch
*d
;
3120 assert(tcg_enabled());
3121 /* since each CPU stores ram addresses in its TLB cache, we must
3122 reset the modified entries */
3123 cpuas
= container_of(listener
, CPUAddressSpace
, tcg_as_listener
);
3124 cpu_reloading_memory_map();
3125 /* The CPU and TLB are protected by the iothread lock.
3126 * We reload the dispatch pointer now because cpu_reloading_memory_map()
3127 * may have split the RCU critical section.
3129 d
= address_space_to_dispatch(cpuas
->as
);
3130 atomic_rcu_set(&cpuas
->memory_dispatch
, d
);
3131 tlb_flush(cpuas
->cpu
);
3134 static void memory_map_init(void)
3136 system_memory
= g_malloc(sizeof(*system_memory
));
3138 memory_region_init(system_memory
, NULL
, "system", UINT64_MAX
);
3139 address_space_init(&address_space_memory
, system_memory
, "memory");
3141 system_io
= g_malloc(sizeof(*system_io
));
3142 memory_region_init_io(system_io
, NULL
, &unassigned_io_ops
, NULL
, "io",
3144 address_space_init(&address_space_io
, system_io
, "I/O");
3147 MemoryRegion
*get_system_memory(void)
3149 return system_memory
;
3152 MemoryRegion
*get_system_io(void)
3157 #endif /* !defined(CONFIG_USER_ONLY) */
3159 /* physical memory access (slow version, mainly for debug) */
3160 #if defined(CONFIG_USER_ONLY)
3161 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
3162 uint8_t *buf
, target_ulong len
, int is_write
)
3165 target_ulong l
, page
;
3169 page
= addr
& TARGET_PAGE_MASK
;
3170 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
3173 flags
= page_get_flags(page
);
3174 if (!(flags
& PAGE_VALID
))
3177 if (!(flags
& PAGE_WRITE
))
3179 /* XXX: this code should not depend on lock_user */
3180 if (!(p
= lock_user(VERIFY_WRITE
, addr
, l
, 0)))
3183 unlock_user(p
, addr
, l
);
3185 if (!(flags
& PAGE_READ
))
3187 /* XXX: this code should not depend on lock_user */
3188 if (!(p
= lock_user(VERIFY_READ
, addr
, l
, 1)))
3191 unlock_user(p
, addr
, 0);
3202 static void invalidate_and_set_dirty(MemoryRegion
*mr
, hwaddr addr
,
3205 uint8_t dirty_log_mask
= memory_region_get_dirty_log_mask(mr
);
3206 addr
+= memory_region_get_ram_addr(mr
);
3208 /* No early return if dirty_log_mask is or becomes 0, because
3209 * cpu_physical_memory_set_dirty_range will still call
3210 * xen_modified_memory.
3212 if (dirty_log_mask
) {
3214 cpu_physical_memory_range_includes_clean(addr
, length
, dirty_log_mask
);
3216 if (dirty_log_mask
& (1 << DIRTY_MEMORY_CODE
)) {
3217 assert(tcg_enabled());
3218 tb_invalidate_phys_range(addr
, addr
+ length
);
3219 dirty_log_mask
&= ~(1 << DIRTY_MEMORY_CODE
);
3221 cpu_physical_memory_set_dirty_range(addr
, length
, dirty_log_mask
);
3224 void memory_region_flush_rom_device(MemoryRegion
*mr
, hwaddr addr
, hwaddr size
)
3227 * In principle this function would work on other memory region types too,
3228 * but the ROM device use case is the only one where this operation is
3229 * necessary. Other memory regions should use the
3230 * address_space_read/write() APIs.
3232 assert(memory_region_is_romd(mr
));
3234 invalidate_and_set_dirty(mr
, addr
, size
);
3237 static int memory_access_size(MemoryRegion
*mr
, unsigned l
, hwaddr addr
)
3239 unsigned access_size_max
= mr
->ops
->valid
.max_access_size
;
3241 /* Regions are assumed to support 1-4 byte accesses unless
3242 otherwise specified. */
3243 if (access_size_max
== 0) {
3244 access_size_max
= 4;
3247 /* Bound the maximum access by the alignment of the address. */
3248 if (!mr
->ops
->impl
.unaligned
) {
3249 unsigned align_size_max
= addr
& -addr
;
3250 if (align_size_max
!= 0 && align_size_max
< access_size_max
) {
3251 access_size_max
= align_size_max
;
3255 /* Don't attempt accesses larger than the maximum. */
3256 if (l
> access_size_max
) {
3257 l
= access_size_max
;
3264 static bool prepare_mmio_access(MemoryRegion
*mr
)
3266 bool unlocked
= !qemu_mutex_iothread_locked();
3267 bool release_lock
= false;
3269 if (unlocked
&& mr
->global_locking
) {
3270 qemu_mutex_lock_iothread();
3272 release_lock
= true;
3274 if (mr
->flush_coalesced_mmio
) {
3276 qemu_mutex_lock_iothread();
3278 qemu_flush_coalesced_mmio_buffer();
3280 qemu_mutex_unlock_iothread();
3284 return release_lock
;
3287 /* Called within RCU critical section. */
3288 static MemTxResult
flatview_write_continue(FlatView
*fv
, hwaddr addr
,
3291 hwaddr len
, hwaddr addr1
,
3292 hwaddr l
, MemoryRegion
*mr
)
3296 MemTxResult result
= MEMTX_OK
;
3297 bool release_lock
= false;
3300 if (!memory_access_is_direct(mr
, true)) {
3301 release_lock
|= prepare_mmio_access(mr
);
3302 l
= memory_access_size(mr
, l
, addr1
);
3303 /* XXX: could force current_cpu to NULL to avoid
3305 val
= ldn_he_p(buf
, l
);
3306 result
|= memory_region_dispatch_write(mr
, addr1
, val
,
3307 size_memop(l
), attrs
);
3310 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
3311 memcpy(ptr
, buf
, l
);
3312 invalidate_and_set_dirty(mr
, addr1
, l
);
3316 qemu_mutex_unlock_iothread();
3317 release_lock
= false;
3329 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true, attrs
);
3335 /* Called from RCU critical section. */
3336 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
3337 const uint8_t *buf
, hwaddr len
)
3342 MemTxResult result
= MEMTX_OK
;
3345 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true, attrs
);
3346 result
= flatview_write_continue(fv
, addr
, attrs
, buf
, len
,
3352 /* Called within RCU critical section. */
3353 MemTxResult
flatview_read_continue(FlatView
*fv
, hwaddr addr
,
3354 MemTxAttrs attrs
, uint8_t *buf
,
3355 hwaddr len
, hwaddr addr1
, hwaddr l
,
3360 MemTxResult result
= MEMTX_OK
;
3361 bool release_lock
= false;
3364 if (!memory_access_is_direct(mr
, false)) {
3366 release_lock
|= prepare_mmio_access(mr
);
3367 l
= memory_access_size(mr
, l
, addr1
);
3368 result
|= memory_region_dispatch_read(mr
, addr1
, &val
,
3369 size_memop(l
), attrs
);
3370 stn_he_p(buf
, l
, val
);
3373 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
3374 memcpy(buf
, ptr
, l
);
3378 qemu_mutex_unlock_iothread();
3379 release_lock
= false;
3391 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false, attrs
);
3397 /* Called from RCU critical section. */
3398 static MemTxResult
flatview_read(FlatView
*fv
, hwaddr addr
,
3399 MemTxAttrs attrs
, uint8_t *buf
, hwaddr len
)
3406 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false, attrs
);
3407 return flatview_read_continue(fv
, addr
, attrs
, buf
, len
,
3411 MemTxResult
address_space_read_full(AddressSpace
*as
, hwaddr addr
,
3412 MemTxAttrs attrs
, uint8_t *buf
, hwaddr len
)
3414 MemTxResult result
= MEMTX_OK
;
3419 fv
= address_space_to_flatview(as
);
3420 result
= flatview_read(fv
, addr
, attrs
, buf
, len
);
3427 MemTxResult
address_space_write(AddressSpace
*as
, hwaddr addr
,
3429 const uint8_t *buf
, hwaddr len
)
3431 MemTxResult result
= MEMTX_OK
;
3436 fv
= address_space_to_flatview(as
);
3437 result
= flatview_write(fv
, addr
, attrs
, buf
, len
);
3444 MemTxResult
address_space_rw(AddressSpace
*as
, hwaddr addr
, MemTxAttrs attrs
,
3445 uint8_t *buf
, hwaddr len
, bool is_write
)
3448 return address_space_write(as
, addr
, attrs
, buf
, len
);
3450 return address_space_read_full(as
, addr
, attrs
, buf
, len
);
3454 void cpu_physical_memory_rw(hwaddr addr
, uint8_t *buf
,
3455 hwaddr len
, int is_write
)
3457 address_space_rw(&address_space_memory
, addr
, MEMTXATTRS_UNSPECIFIED
,
3458 buf
, len
, is_write
);
3461 enum write_rom_type
{
3466 static inline MemTxResult
address_space_write_rom_internal(AddressSpace
*as
,
3471 enum write_rom_type type
)
3481 mr
= address_space_translate(as
, addr
, &addr1
, &l
, true, attrs
);
3483 if (!(memory_region_is_ram(mr
) ||
3484 memory_region_is_romd(mr
))) {
3485 l
= memory_access_size(mr
, l
, addr1
);
3488 ptr
= qemu_map_ram_ptr(mr
->ram_block
, addr1
);
3491 memcpy(ptr
, buf
, l
);
3492 invalidate_and_set_dirty(mr
, addr1
, l
);
3495 flush_icache_range((uintptr_t)ptr
, (uintptr_t)ptr
+ l
);
3507 /* used for ROM loading : can write in RAM and ROM */
3508 MemTxResult
address_space_write_rom(AddressSpace
*as
, hwaddr addr
,
3510 const uint8_t *buf
, hwaddr len
)
3512 return address_space_write_rom_internal(as
, addr
, attrs
,
3513 buf
, len
, WRITE_DATA
);
3516 void cpu_flush_icache_range(hwaddr start
, hwaddr len
)
3519 * This function should do the same thing as an icache flush that was
3520 * triggered from within the guest. For TCG we are always cache coherent,
3521 * so there is no need to flush anything. For KVM / Xen we need to flush
3522 * the host's instruction cache at least.
3524 if (tcg_enabled()) {
3528 address_space_write_rom_internal(&address_space_memory
,
3529 start
, MEMTXATTRS_UNSPECIFIED
,
3530 NULL
, len
, FLUSH_CACHE
);
3541 static BounceBuffer bounce
;
3543 typedef struct MapClient
{
3545 QLIST_ENTRY(MapClient
) link
;
3548 QemuMutex map_client_list_lock
;
3549 static QLIST_HEAD(, MapClient
) map_client_list
3550 = QLIST_HEAD_INITIALIZER(map_client_list
);
3552 static void cpu_unregister_map_client_do(MapClient
*client
)
3554 QLIST_REMOVE(client
, link
);
3558 static void cpu_notify_map_clients_locked(void)
3562 while (!QLIST_EMPTY(&map_client_list
)) {
3563 client
= QLIST_FIRST(&map_client_list
);
3564 qemu_bh_schedule(client
->bh
);
3565 cpu_unregister_map_client_do(client
);
3569 void cpu_register_map_client(QEMUBH
*bh
)
3571 MapClient
*client
= g_malloc(sizeof(*client
));
3573 qemu_mutex_lock(&map_client_list_lock
);
3575 QLIST_INSERT_HEAD(&map_client_list
, client
, link
);
3576 if (!atomic_read(&bounce
.in_use
)) {
3577 cpu_notify_map_clients_locked();
3579 qemu_mutex_unlock(&map_client_list_lock
);
3582 void cpu_exec_init_all(void)
3584 qemu_mutex_init(&ram_list
.mutex
);
3585 /* The data structures we set up here depend on knowing the page size,
3586 * so no more changes can be made after this point.
3587 * In an ideal world, nothing we did before we had finished the
3588 * machine setup would care about the target page size, and we could
3589 * do this much later, rather than requiring board models to state
3590 * up front what their requirements are.
3592 finalize_target_page_bits();
3595 qemu_mutex_init(&map_client_list_lock
);
3598 void cpu_unregister_map_client(QEMUBH
*bh
)
3602 qemu_mutex_lock(&map_client_list_lock
);
3603 QLIST_FOREACH(client
, &map_client_list
, link
) {
3604 if (client
->bh
== bh
) {
3605 cpu_unregister_map_client_do(client
);
3609 qemu_mutex_unlock(&map_client_list_lock
);
3612 static void cpu_notify_map_clients(void)
3614 qemu_mutex_lock(&map_client_list_lock
);
3615 cpu_notify_map_clients_locked();
3616 qemu_mutex_unlock(&map_client_list_lock
);
3619 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, hwaddr len
,
3620 bool is_write
, MemTxAttrs attrs
)
3627 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
, attrs
);
3628 if (!memory_access_is_direct(mr
, is_write
)) {
3629 l
= memory_access_size(mr
, l
, addr
);
3630 if (!memory_region_access_valid(mr
, xlat
, l
, is_write
, attrs
)) {
3641 bool address_space_access_valid(AddressSpace
*as
, hwaddr addr
,
3642 hwaddr len
, bool is_write
,
3649 fv
= address_space_to_flatview(as
);
3650 result
= flatview_access_valid(fv
, addr
, len
, is_write
, attrs
);
3656 flatview_extend_translation(FlatView
*fv
, hwaddr addr
,
3658 MemoryRegion
*mr
, hwaddr base
, hwaddr len
,
3659 bool is_write
, MemTxAttrs attrs
)
3663 MemoryRegion
*this_mr
;
3669 if (target_len
== 0) {
3674 this_mr
= flatview_translate(fv
, addr
, &xlat
,
3675 &len
, is_write
, attrs
);
3676 if (this_mr
!= mr
|| xlat
!= base
+ done
) {
3682 /* Map a physical memory region into a host virtual address.
3683 * May map a subset of the requested range, given by and returned in *plen.
3684 * May return NULL if resources needed to perform the mapping are exhausted.
3685 * Use only for reads OR writes - not for read-modify-write operations.
3686 * Use cpu_register_map_client() to know when retrying the map operation is
3687 * likely to succeed.
3689 void *address_space_map(AddressSpace
*as
,
3707 fv
= address_space_to_flatview(as
);
3708 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
, attrs
);
3710 if (!memory_access_is_direct(mr
, is_write
)) {
3711 if (atomic_xchg(&bounce
.in_use
, true)) {
3715 /* Avoid unbounded allocations */
3716 l
= MIN(l
, TARGET_PAGE_SIZE
);
3717 bounce
.buffer
= qemu_memalign(TARGET_PAGE_SIZE
, l
);
3721 memory_region_ref(mr
);
3724 flatview_read(fv
, addr
, MEMTXATTRS_UNSPECIFIED
,
3730 return bounce
.buffer
;
3734 memory_region_ref(mr
);
3735 *plen
= flatview_extend_translation(fv
, addr
, len
, mr
, xlat
,
3736 l
, is_write
, attrs
);
3737 ptr
= qemu_ram_ptr_length(mr
->ram_block
, xlat
, plen
, true);
3743 /* Unmaps a memory region previously mapped by address_space_map().
3744 * Will also mark the memory as dirty if is_write == 1. access_len gives
3745 * the amount of memory that was actually read or written by the caller.
3747 void address_space_unmap(AddressSpace
*as
, void *buffer
, hwaddr len
,
3748 int is_write
, hwaddr access_len
)
3750 if (buffer
!= bounce
.buffer
) {
3754 mr
= memory_region_from_host(buffer
, &addr1
);
3757 invalidate_and_set_dirty(mr
, addr1
, access_len
);
3759 if (xen_enabled()) {
3760 xen_invalidate_map_cache_entry(buffer
);
3762 memory_region_unref(mr
);
3766 address_space_write(as
, bounce
.addr
, MEMTXATTRS_UNSPECIFIED
,
3767 bounce
.buffer
, access_len
);
3769 qemu_vfree(bounce
.buffer
);
3770 bounce
.buffer
= NULL
;
3771 memory_region_unref(bounce
.mr
);
3772 atomic_mb_set(&bounce
.in_use
, false);
3773 cpu_notify_map_clients();
3776 void *cpu_physical_memory_map(hwaddr addr
,
3780 return address_space_map(&address_space_memory
, addr
, plen
, is_write
,
3781 MEMTXATTRS_UNSPECIFIED
);
3784 void cpu_physical_memory_unmap(void *buffer
, hwaddr len
,
3785 int is_write
, hwaddr access_len
)
3787 return address_space_unmap(&address_space_memory
, buffer
, len
, is_write
, access_len
);
3790 #define ARG1_DECL AddressSpace *as
3793 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3794 #define RCU_READ_LOCK(...) rcu_read_lock()
3795 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3796 #include "memory_ldst.inc.c"
3798 int64_t address_space_cache_init(MemoryRegionCache
*cache
,
3804 AddressSpaceDispatch
*d
;
3811 cache
->fv
= address_space_get_flatview(as
);
3812 d
= flatview_to_dispatch(cache
->fv
);
3813 cache
->mrs
= *address_space_translate_internal(d
, addr
, &cache
->xlat
, &l
, true);
3816 memory_region_ref(mr
);
3817 if (memory_access_is_direct(mr
, is_write
)) {
3818 /* We don't care about the memory attributes here as we're only
3819 * doing this if we found actual RAM, which behaves the same
3820 * regardless of attributes; so UNSPECIFIED is fine.
3822 l
= flatview_extend_translation(cache
->fv
, addr
, len
, mr
,
3823 cache
->xlat
, l
, is_write
,
3824 MEMTXATTRS_UNSPECIFIED
);
3825 cache
->ptr
= qemu_ram_ptr_length(mr
->ram_block
, cache
->xlat
, &l
, true);
3831 cache
->is_write
= is_write
;
3835 void address_space_cache_invalidate(MemoryRegionCache
*cache
,
3839 assert(cache
->is_write
);
3840 if (likely(cache
->ptr
)) {
3841 invalidate_and_set_dirty(cache
->mrs
.mr
, addr
+ cache
->xlat
, access_len
);
3845 void address_space_cache_destroy(MemoryRegionCache
*cache
)
3847 if (!cache
->mrs
.mr
) {
3851 if (xen_enabled()) {
3852 xen_invalidate_map_cache_entry(cache
->ptr
);
3854 memory_region_unref(cache
->mrs
.mr
);
3855 flatview_unref(cache
->fv
);
3856 cache
->mrs
.mr
= NULL
;
3860 /* Called from RCU critical section. This function has the same
3861 * semantics as address_space_translate, but it only works on a
3862 * predefined range of a MemoryRegion that was mapped with
3863 * address_space_cache_init.
3865 static inline MemoryRegion
*address_space_translate_cached(
3866 MemoryRegionCache
*cache
, hwaddr addr
, hwaddr
*xlat
,
3867 hwaddr
*plen
, bool is_write
, MemTxAttrs attrs
)
3869 MemoryRegionSection section
;
3871 IOMMUMemoryRegion
*iommu_mr
;
3872 AddressSpace
*target_as
;
3874 assert(!cache
->ptr
);
3875 *xlat
= addr
+ cache
->xlat
;
3878 iommu_mr
= memory_region_get_iommu(mr
);
3884 section
= address_space_translate_iommu(iommu_mr
, xlat
, plen
,
3885 NULL
, is_write
, true,
3890 /* Called from RCU critical section. address_space_read_cached uses this
3891 * out of line function when the target is an MMIO or IOMMU region.
3894 address_space_read_cached_slow(MemoryRegionCache
*cache
, hwaddr addr
,
3895 void *buf
, hwaddr len
)
3901 mr
= address_space_translate_cached(cache
, addr
, &addr1
, &l
, false,
3902 MEMTXATTRS_UNSPECIFIED
);
3903 flatview_read_continue(cache
->fv
,
3904 addr
, MEMTXATTRS_UNSPECIFIED
, buf
, len
,
3908 /* Called from RCU critical section. address_space_write_cached uses this
3909 * out of line function when the target is an MMIO or IOMMU region.
3912 address_space_write_cached_slow(MemoryRegionCache
*cache
, hwaddr addr
,
3913 const void *buf
, hwaddr len
)
3919 mr
= address_space_translate_cached(cache
, addr
, &addr1
, &l
, true,
3920 MEMTXATTRS_UNSPECIFIED
);
3921 flatview_write_continue(cache
->fv
,
3922 addr
, MEMTXATTRS_UNSPECIFIED
, buf
, len
,
3926 #define ARG1_DECL MemoryRegionCache *cache
3928 #define SUFFIX _cached_slow
3929 #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__)
3930 #define RCU_READ_LOCK() ((void)0)
3931 #define RCU_READ_UNLOCK() ((void)0)
3932 #include "memory_ldst.inc.c"
3934 /* virtual memory access for debug (includes writing to ROM) */
3935 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
3936 uint8_t *buf
, target_ulong len
, int is_write
)
3939 target_ulong l
, page
;
3941 cpu_synchronize_state(cpu
);
3946 page
= addr
& TARGET_PAGE_MASK
;
3947 phys_addr
= cpu_get_phys_page_attrs_debug(cpu
, page
, &attrs
);
3948 asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
3949 /* if no physical page mapped, return an error */
3950 if (phys_addr
== -1)
3952 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
3955 phys_addr
+= (addr
& ~TARGET_PAGE_MASK
);
3957 address_space_write_rom(cpu
->cpu_ases
[asidx
].as
, phys_addr
,
3960 address_space_rw(cpu
->cpu_ases
[asidx
].as
, phys_addr
,
3971 * Allows code that needs to deal with migration bitmaps etc to still be built
3972 * target independent.
3974 size_t qemu_target_page_size(void)
3976 return TARGET_PAGE_SIZE
;
3979 int qemu_target_page_bits(void)
3981 return TARGET_PAGE_BITS
;
3984 int qemu_target_page_bits_min(void)
3986 return TARGET_PAGE_BITS_MIN
;
3990 bool target_words_bigendian(void)
3992 #if defined(TARGET_WORDS_BIGENDIAN)
3999 #ifndef CONFIG_USER_ONLY
4000 bool cpu_physical_memory_is_io(hwaddr phys_addr
)
4007 mr
= address_space_translate(&address_space_memory
,
4008 phys_addr
, &phys_addr
, &l
, false,
4009 MEMTXATTRS_UNSPECIFIED
);
4011 res
= !(memory_region_is_ram(mr
) || memory_region_is_romd(mr
));
4016 int qemu_ram_foreach_block(RAMBlockIterFunc func
, void *opaque
)
4022 RAMBLOCK_FOREACH(block
) {
4023 ret
= func(block
, opaque
);
4033 * Unmap pages of memory from start to start+length such that
4034 * they a) read as 0, b) Trigger whatever fault mechanism
4035 * the OS provides for postcopy.
4036 * The pages must be unmapped by the end of the function.
4037 * Returns: 0 on success, none-0 on failure
4040 int ram_block_discard_range(RAMBlock
*rb
, uint64_t start
, size_t length
)
4044 uint8_t *host_startaddr
= rb
->host
+ start
;
4046 if ((uintptr_t)host_startaddr
& (rb
->page_size
- 1)) {
4047 error_report("ram_block_discard_range: Unaligned start address: %p",
4052 if ((start
+ length
) <= rb
->used_length
) {
4053 bool need_madvise
, need_fallocate
;
4054 uint8_t *host_endaddr
= host_startaddr
+ length
;
4055 if ((uintptr_t)host_endaddr
& (rb
->page_size
- 1)) {
4056 error_report("ram_block_discard_range: Unaligned end address: %p",
4061 errno
= ENOTSUP
; /* If we are missing MADVISE etc */
4063 /* The logic here is messy;
4064 * madvise DONTNEED fails for hugepages
4065 * fallocate works on hugepages and shmem
4067 need_madvise
= (rb
->page_size
== qemu_host_page_size
);
4068 need_fallocate
= rb
->fd
!= -1;
4069 if (need_fallocate
) {
4070 /* For a file, this causes the area of the file to be zero'd
4071 * if read, and for hugetlbfs also causes it to be unmapped
4072 * so a userfault will trigger.
4074 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
4075 ret
= fallocate(rb
->fd
, FALLOC_FL_PUNCH_HOLE
| FALLOC_FL_KEEP_SIZE
,
4079 error_report("ram_block_discard_range: Failed to fallocate "
4080 "%s:%" PRIx64
" +%zx (%d)",
4081 rb
->idstr
, start
, length
, ret
);
4086 error_report("ram_block_discard_range: fallocate not available/file"
4087 "%s:%" PRIx64
" +%zx (%d)",
4088 rb
->idstr
, start
, length
, ret
);
4093 /* For normal RAM this causes it to be unmapped,
4094 * for shared memory it causes the local mapping to disappear
4095 * and to fall back on the file contents (which we just
4096 * fallocate'd away).
4098 #if defined(CONFIG_MADVISE)
4099 ret
= madvise(host_startaddr
, length
, MADV_DONTNEED
);
4102 error_report("ram_block_discard_range: Failed to discard range "
4103 "%s:%" PRIx64
" +%zx (%d)",
4104 rb
->idstr
, start
, length
, ret
);
4109 error_report("ram_block_discard_range: MADVISE not available"
4110 "%s:%" PRIx64
" +%zx (%d)",
4111 rb
->idstr
, start
, length
, ret
);
4115 trace_ram_block_discard_range(rb
->idstr
, host_startaddr
, length
,
4116 need_madvise
, need_fallocate
, ret
);
4118 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
4119 "/%zx/" RAM_ADDR_FMT
")",
4120 rb
->idstr
, start
, length
, rb
->used_length
);
4127 bool ramblock_is_pmem(RAMBlock
*rb
)
4129 return rb
->flags
& RAM_PMEM
;
4134 void page_size_init(void)
4136 /* NOTE: we can always suppose that qemu_host_page_size >=
4138 if (qemu_host_page_size
== 0) {
4139 qemu_host_page_size
= qemu_real_host_page_size
;
4141 if (qemu_host_page_size
< TARGET_PAGE_SIZE
) {
4142 qemu_host_page_size
= TARGET_PAGE_SIZE
;
4144 qemu_host_page_mask
= -(intptr_t)qemu_host_page_size
;
4147 #if !defined(CONFIG_USER_ONLY)
4149 static void mtree_print_phys_entries(int start
, int end
, int skip
, int ptr
)
4151 if (start
== end
- 1) {
4152 qemu_printf("\t%3d ", start
);
4154 qemu_printf("\t%3d..%-3d ", start
, end
- 1);
4156 qemu_printf(" skip=%d ", skip
);
4157 if (ptr
== PHYS_MAP_NODE_NIL
) {
4158 qemu_printf(" ptr=NIL");
4160 qemu_printf(" ptr=#%d", ptr
);
4162 qemu_printf(" ptr=[%d]", ptr
);
4167 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
4168 int128_sub((size), int128_one())) : 0)
4170 void mtree_print_dispatch(AddressSpaceDispatch
*d
, MemoryRegion
*root
)
4174 qemu_printf(" Dispatch\n");
4175 qemu_printf(" Physical sections\n");
4177 for (i
= 0; i
< d
->map
.sections_nb
; ++i
) {
4178 MemoryRegionSection
*s
= d
->map
.sections
+ i
;
4179 const char *names
[] = { " [unassigned]", " [not dirty]",
4180 " [ROM]", " [watch]" };
4182 qemu_printf(" #%d @" TARGET_FMT_plx
".." TARGET_FMT_plx
4185 s
->offset_within_address_space
,
4186 s
->offset_within_address_space
+ MR_SIZE(s
->mr
->size
),
4187 s
->mr
->name
? s
->mr
->name
: "(noname)",
4188 i
< ARRAY_SIZE(names
) ? names
[i
] : "",
4189 s
->mr
== root
? " [ROOT]" : "",
4190 s
== d
->mru_section
? " [MRU]" : "",
4191 s
->mr
->is_iommu
? " [iommu]" : "");
4194 qemu_printf(" alias=%s", s
->mr
->alias
->name
?
4195 s
->mr
->alias
->name
: "noname");
4200 qemu_printf(" Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n",
4201 P_L2_BITS
, P_L2_LEVELS
, d
->phys_map
.ptr
, d
->phys_map
.skip
);
4202 for (i
= 0; i
< d
->map
.nodes_nb
; ++i
) {
4205 Node
*n
= d
->map
.nodes
+ i
;
4207 qemu_printf(" [%d]\n", i
);
4209 for (j
= 0, jprev
= 0, prev
= *n
[0]; j
< ARRAY_SIZE(*n
); ++j
) {
4210 PhysPageEntry
*pe
= *n
+ j
;
4212 if (pe
->ptr
== prev
.ptr
&& pe
->skip
== prev
.skip
) {
4216 mtree_print_phys_entries(jprev
, j
, prev
.skip
, prev
.ptr
);
4222 if (jprev
!= ARRAY_SIZE(*n
)) {
4223 mtree_print_phys_entries(jprev
, j
, prev
.skip
, prev
.ptr
);