fpu/softfloat-specialize.c.inc

   1 /*
   2  * QEMU float support
   3  *
   4  * The code in this source file is derived from release 2a of the SoftFloat
   5  * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and
   6  * some later contributions) are provided under that license, as detailed below.
   7  * It has subsequently been modified by contributors to the QEMU Project,
   8  * so some portions are provided under:
   9  *  the SoftFloat-2a license
  10  *  the BSD license
  11  *  GPL-v2-or-later
  12  *
  13  * Any future contributions to this file after December 1st 2014 will be
  14  * taken to be licensed under the Softfloat-2a license unless specifically
  15  * indicated otherwise.
  16  */
  17
  18 /*
  19 ===============================================================================
  20 This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
  21 Arithmetic Package, Release 2a.
  22
  23 Written by John R. Hauser.  This work was made possible in part by the
  24 International Computer Science Institute, located at Suite 600, 1947 Center
  25 Street, Berkeley, California 94704.  Funding was partially provided by the
  26 National Science Foundation under grant MIP-9311980.  The original version
  27 of this code was written as part of a project to build a fixed-point vector
  28 processor in collaboration with the University of California at Berkeley,
  29 overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
  30 is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
  31 arithmetic/SoftFloat.html'.
  32
  33 THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort
  34 has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
  35 TIMES RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO
  36 PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
  37 AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
  38
  39 Derivative works are acceptable, even for commercial purposes, so long as
  40 (1) they include prominent notice that the work is derivative, and (2) they
  41 include prominent notice akin to these four paragraphs for those parts of
  42 this code that are retained.
  43
  44 ===============================================================================
  45 */
  46
  47 /* BSD licensing:
  48  * Copyright (c) 2006, Fabrice Bellard
  49  * All rights reserved.
  50  *
  51  * Redistribution and use in source and binary forms, with or without
  52  * modification, are permitted provided that the following conditions are met:
  53  *
  54  * 1. Redistributions of source code must retain the above copyright notice,
  55  * this list of conditions and the following disclaimer.
  56  *
  57  * 2. Redistributions in binary form must reproduce the above copyright notice,
  58  * this list of conditions and the following disclaimer in the documentation
  59  * and/or other materials provided with the distribution.
  60  *
  61  * 3. Neither the name of the copyright holder nor the names of its contributors
  62  * may be used to endorse or promote products derived from this software without
  63  * specific prior written permission.
  64  *
  65  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  66  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  67  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  68  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  69  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  70  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  71  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  72  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  73  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  74  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  75  * THE POSSIBILITY OF SUCH DAMAGE.
  76  */
  77
  78 /* Portions of this work are licensed under the terms of the GNU GPL,
  79  * version 2 or later. See the COPYING file in the top-level directory.
  80  */
  81
  82 /*
  83  * Define whether architecture deviates from IEEE in not supporting
  84  * signaling NaNs (so all NaNs are treated as quiet).
  85  */
  86 static inline bool no_signaling_nans(float_status *status)
  87 {
  88 #if defined(TARGET_XTENSA)
  89     return status->no_signaling_nans;
  90 #else
  91     return false;
  92 #endif
  93 }
  94
  95 /* Define how the architecture discriminates signaling NaNs.
  96  * This done with the most significant bit of the fraction.
  97  * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008
  98  * the msb must be zero.  MIPS is (so far) unique in supporting both the
  99  * 2008 revision and backward compatibility with their original choice.
 100  * Thus for MIPS we must make the choice at runtime.
 101  */
 102 static inline bool snan_bit_is_one(float_status *status)
 103 {
 104 #if defined(TARGET_MIPS)
 105     return status->snan_bit_is_one;
 106 #elif defined(TARGET_HPPA) || defined(TARGET_SH4)
 107     return 1;
 108 #else
 109     return 0;
 110 #endif
 111 }
 112
 113 /*----------------------------------------------------------------------------
 114 | For the deconstructed floating-point with fraction FRAC, return true
 115 | if the fraction represents a signalling NaN; otherwise false.
 116 *----------------------------------------------------------------------------*/
 117
 118 static bool parts_is_snan_frac(uint64_t frac, float_status *status)
 119 {
 120     if (no_signaling_nans(status)) {
 121         return false;
 122     } else {
 123         bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);
 124         return msb == snan_bit_is_one(status);
 125     }
 126 }
 127
 128 /*----------------------------------------------------------------------------
 129 | The pattern for a default generated deconstructed floating-point NaN.
 130 *----------------------------------------------------------------------------*/
 131
 132 static void parts64_default_nan(FloatParts64 *p, float_status *status)
 133 {
 134     bool sign = 0;
 135     uint64_t frac;
 136
 137 #if defined(TARGET_SPARC) || defined(TARGET_M68K)
 138     /* !snan_bit_is_one, set all bits */
 139     frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
 140 #elif defined(TARGET_I386) || defined(TARGET_X86_64) \
 141     || defined(TARGET_MICROBLAZE)
 142     /* !snan_bit_is_one, set sign and msb */
 143     frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
 144     sign = 1;
 145 #elif defined(TARGET_HPPA)
 146     /* snan_bit_is_one, set msb-1.  */
 147     frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
 148 #elif defined(TARGET_HEXAGON)
 149     sign = 1;
 150     frac = ~0ULL;
 151 #else
 152     /*
 153      * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
 154      * S390, SH4, TriCore, and Xtensa.  Our other supported targets,
 155      * CRIS, Nios2, and Tile, do not have floating-point.
 156      */
 157     if (snan_bit_is_one(status)) {
 158         /* set all bits other than msb */
 159         frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
 160     } else {
 161         /* set msb */
 162         frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
 163     }
 164 #endif
 165
 166     *p = (FloatParts64) {
 167         .cls = float_class_qnan,
 168         .sign = sign,
 169         .exp = INT_MAX,
 170         .frac = frac
 171     };
 172 }
 173
 174 static void parts128_default_nan(FloatParts128 *p, float_status *status)
 175 {
 176     /*
 177      * Extrapolate from the choices made by parts64_default_nan to fill
 178      * in the quad-floating format.  If the low bit is set, assume we
 179      * want to set all non-snan bits.
 180      */
 181     FloatParts64 p64;
 182     parts64_default_nan(&p64, status);
 183
 184     *p = (FloatParts128) {
 185         .cls = float_class_qnan,
 186         .sign = p64.sign,
 187         .exp = INT_MAX,
 188         .frac_hi = p64.frac,
 189         .frac_lo = -(p64.frac & 1)
 190     };
 191 }
 192
 193 /*----------------------------------------------------------------------------
 194 | Returns a quiet NaN from a signalling NaN for the deconstructed
 195 | floating-point parts.
 196 *----------------------------------------------------------------------------*/
 197
 198 static uint64_t parts_silence_nan_frac(uint64_t frac, float_status *status)
 199 {
 200     g_assert(!no_signaling_nans(status));
 201
 202     /* The only snan_bit_is_one target without default_nan_mode is HPPA. */
 203     if (snan_bit_is_one(status)) {
 204         frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1));
 205         frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2);
 206     } else {
 207         frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1);
 208     }
 209     return frac;
 210 }
 211
 212 static void parts64_silence_nan(FloatParts64 *p, float_status *status)
 213 {
 214     p->frac = parts_silence_nan_frac(p->frac, status);
 215     p->cls = float_class_qnan;
 216 }
 217
 218 static void parts128_silence_nan(FloatParts128 *p, float_status *status)
 219 {
 220     p->frac_hi = parts_silence_nan_frac(p->frac_hi, status);
 221     p->cls = float_class_qnan;
 222 }
 223
 224 /*----------------------------------------------------------------------------
 225 | The pattern for a default generated extended double-precision NaN.
 226 *----------------------------------------------------------------------------*/
 227 floatx80 floatx80_default_nan(float_status *status)
 228 {
 229     floatx80 r;
 230
 231     /* None of the targets that have snan_bit_is_one use floatx80.  */
 232     assert(!snan_bit_is_one(status));
 233 #if defined(TARGET_M68K)
 234     r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
 235     r.high = 0x7FFF;
 236 #else
 237     /* X86 */
 238     r.low = UINT64_C(0xC000000000000000);
 239     r.high = 0xFFFF;
 240 #endif
 241     return r;
 242 }
 243
 244 /*----------------------------------------------------------------------------
 245 | The pattern for a default generated extended double-precision inf.
 246 *----------------------------------------------------------------------------*/
 247
 248 #define floatx80_infinity_high 0x7FFF
 249 #if defined(TARGET_M68K)
 250 #define floatx80_infinity_low  UINT64_C(0x0000000000000000)
 251 #else
 252 #define floatx80_infinity_low  UINT64_C(0x8000000000000000)
 253 #endif
 254
 255 const floatx80 floatx80_infinity
 256     = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low);
 257
 258 /*----------------------------------------------------------------------------
 259 | Returns 1 if the half-precision floating-point value `a' is a quiet
 260 | NaN; otherwise returns 0.
 261 *----------------------------------------------------------------------------*/
 262
 263 bool float16_is_quiet_nan(float16 a_, float_status *status)
 264 {
 265     if (no_signaling_nans(status)) {
 266         return float16_is_any_nan(a_);
 267     } else {
 268         uint16_t a = float16_val(a_);
 269         if (snan_bit_is_one(status)) {
 270             return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
 271         } else {
 272
 273             return ((a >> 9) & 0x3F) == 0x3F;
 274         }
 275     }
 276 }
 277
 278 /*----------------------------------------------------------------------------
 279 | Returns 1 if the bfloat16 value `a' is a quiet
 280 | NaN; otherwise returns 0.
 281 *----------------------------------------------------------------------------*/
 282
 283 bool bfloat16_is_quiet_nan(bfloat16 a_, float_status *status)
 284 {
 285     if (no_signaling_nans(status)) {
 286         return bfloat16_is_any_nan(a_);
 287     } else {
 288         uint16_t a = a_;
 289         if (snan_bit_is_one(status)) {
 290             return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F);
 291         } else {
 292             return ((a >> 6) & 0x1FF) == 0x1FF;
 293         }
 294     }
 295 }
 296
 297 /*----------------------------------------------------------------------------
 298 | Returns 1 if the half-precision floating-point value `a' is a signaling
 299 | NaN; otherwise returns 0.
 300 *----------------------------------------------------------------------------*/
 301
 302 bool float16_is_signaling_nan(float16 a_, float_status *status)
 303 {
 304     if (no_signaling_nans(status)) {
 305         return 0;
 306     } else {
 307         uint16_t a = float16_val(a_);
 308         if (snan_bit_is_one(status)) {
 309             return ((a >> 9) & 0x3F) == 0x3F;
 310         } else {
 311             return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
 312         }
 313     }
 314 }
 315
 316 /*----------------------------------------------------------------------------
 317 | Returns 1 if the bfloat16 value `a' is a signaling
 318 | NaN; otherwise returns 0.
 319 *----------------------------------------------------------------------------*/
 320
 321 bool bfloat16_is_signaling_nan(bfloat16 a_, float_status *status)
 322 {
 323     if (no_signaling_nans(status)) {
 324         return 0;
 325     } else {
 326         uint16_t a = a_;
 327         if (snan_bit_is_one(status)) {
 328             return ((a >> 6) & 0x1FF) == 0x1FF;
 329         } else {
 330             return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F);
 331         }
 332     }
 333 }
 334
 335 /*----------------------------------------------------------------------------
 336 | Returns 1 if the single-precision floating-point value `a' is a quiet
 337 | NaN; otherwise returns 0.
 338 *----------------------------------------------------------------------------*/
 339
 340 bool float32_is_quiet_nan(float32 a_, float_status *status)
 341 {
 342     if (no_signaling_nans(status)) {
 343         return float32_is_any_nan(a_);
 344     } else {
 345         uint32_t a = float32_val(a_);
 346         if (snan_bit_is_one(status)) {
 347             return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
 348         } else {
 349             return ((uint32_t)(a << 1) >= 0xFF800000);
 350         }
 351     }
 352 }
 353
 354 /*----------------------------------------------------------------------------
 355 | Returns 1 if the single-precision floating-point value `a' is a signaling
 356 | NaN; otherwise returns 0.
 357 *----------------------------------------------------------------------------*/
 358
 359 bool float32_is_signaling_nan(float32 a_, float_status *status)
 360 {
 361     if (no_signaling_nans(status)) {
 362         return 0;
 363     } else {
 364         uint32_t a = float32_val(a_);
 365         if (snan_bit_is_one(status)) {
 366             return ((uint32_t)(a << 1) >= 0xFF800000);
 367         } else {
 368             return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
 369         }
 370     }
 371 }
 372
 373 /*----------------------------------------------------------------------------
 374 | Select which NaN to propagate for a two-input operation.
 375 | IEEE754 doesn't specify all the details of this, so the
 376 | algorithm is target-specific.
 377 | The routine is passed various bits of information about the
 378 | two NaNs and should return 0 to select NaN a and 1 for NaN b.
 379 | Note that signalling NaNs are always squashed to quiet NaNs
 380 | by the caller, by calling floatXX_silence_nan() before
 381 | returning them.
 382 |
 383 | aIsLargerSignificand is only valid if both a and b are NaNs
 384 | of some kind, and is true if a has the larger significand,
 385 | or if both a and b have the same significand but a is
 386 | positive but b is negative. It is only needed for the x87
 387 | tie-break rule.
 388 *----------------------------------------------------------------------------*/
 389
 390 static int pickNaN(FloatClass a_cls, FloatClass b_cls,
 391                    bool aIsLargerSignificand, float_status *status)
 392 {
 393 #if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA)
 394     /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take
 395      * the first of:
 396      *  1. A if it is signaling
 397      *  2. B if it is signaling
 398      *  3. A (quiet)
 399      *  4. B (quiet)
 400      * A signaling NaN is always quietened before returning it.
 401      */
 402     /* According to MIPS specifications, if one of the two operands is
 403      * a sNaN, a new qNaN has to be generated. This is done in
 404      * floatXX_silence_nan(). For qNaN inputs the specifications
 405      * says: "When possible, this QNaN result is one of the operand QNaN
 406      * values." In practice it seems that most implementations choose
 407      * the first operand if both operands are qNaN. In short this gives
 408      * the following rules:
 409      *  1. A if it is signaling
 410      *  2. B if it is signaling
 411      *  3. A (quiet)
 412      *  4. B (quiet)
 413      * A signaling NaN is always silenced before returning it.
 414      */
 415     if (is_snan(a_cls)) {
 416         return 0;
 417     } else if (is_snan(b_cls)) {
 418         return 1;
 419     } else if (is_qnan(a_cls)) {
 420         return 0;
 421     } else {
 422         return 1;
 423     }
 424 #elif defined(TARGET_PPC) || defined(TARGET_M68K)
 425     /* PowerPC propagation rules:
 426      *  1. A if it sNaN or qNaN
 427      *  2. B if it sNaN or qNaN
 428      * A signaling NaN is always silenced before returning it.
 429      */
 430     /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
 431      * 3.4 FLOATING-POINT INSTRUCTION DETAILS
 432      * If either operand, but not both operands, of an operation is a
 433      * nonsignaling NaN, then that NaN is returned as the result. If both
 434      * operands are nonsignaling NaNs, then the destination operand
 435      * nonsignaling NaN is returned as the result.
 436      * If either operand to an operation is a signaling NaN (SNaN), then the
 437      * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit
 438      * is set in the FPCR ENABLE byte, then the exception is taken and the
 439      * destination is not modified. If the SNaN exception enable bit is not
 440      * set, setting the SNaN bit in the operand to a one converts the SNaN to
 441      * a nonsignaling NaN. The operation then continues as described in the
 442      * preceding paragraph for nonsignaling NaNs.
 443      */
 444     if (is_nan(a_cls)) {
 445         return 0;
 446     } else {
 447         return 1;
 448     }
 449 #elif defined(TARGET_XTENSA)
 450     /*
 451      * Xtensa has two NaN propagation modes.
 452      * Which one is active is controlled by float_status::use_first_nan.
 453      */
 454     if (status->use_first_nan) {
 455         if (is_nan(a_cls)) {
 456             return 0;
 457         } else {
 458             return 1;
 459         }
 460     } else {
 461         if (is_nan(b_cls)) {
 462             return 1;
 463         } else {
 464             return 0;
 465         }
 466     }
 467 #else
 468     /* This implements x87 NaN propagation rules:
 469      * SNaN + QNaN => return the QNaN
 470      * two SNaNs => return the one with the larger significand, silenced
 471      * two QNaNs => return the one with the larger significand
 472      * SNaN and a non-NaN => return the SNaN, silenced
 473      * QNaN and a non-NaN => return the QNaN
 474      *
 475      * If we get down to comparing significands and they are the same,
 476      * return the NaN with the positive sign bit (if any).
 477      */
 478     if (is_snan(a_cls)) {
 479         if (is_snan(b_cls)) {
 480             return aIsLargerSignificand ? 0 : 1;
 481         }
 482         return is_qnan(b_cls) ? 1 : 0;
 483     } else if (is_qnan(a_cls)) {
 484         if (is_snan(b_cls) || !is_qnan(b_cls)) {
 485             return 0;
 486         } else {
 487             return aIsLargerSignificand ? 0 : 1;
 488         }
 489     } else {
 490         return 1;
 491     }
 492 #endif
 493 }
 494
 495 /*----------------------------------------------------------------------------
 496 | Select which NaN to propagate for a three-input operation.
 497 | For the moment we assume that no CPU needs the 'larger significand'
 498 | information.
 499 | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
 500 *----------------------------------------------------------------------------*/
 501 static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
 502                          bool infzero, float_status *status)
 503 {
 504 #if defined(TARGET_ARM)
 505     /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
 506      * the default NaN
 507      */
 508     if (infzero && is_qnan(c_cls)) {
 509         float_raise(float_flag_invalid | float_flag_invalid_imz, status);
 510         return 3;
 511     }
 512
 513     /* This looks different from the ARM ARM pseudocode, because the ARM ARM
 514      * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
 515      */
 516     if (is_snan(c_cls)) {
 517         return 2;
 518     } else if (is_snan(a_cls)) {
 519         return 0;
 520     } else if (is_snan(b_cls)) {
 521         return 1;
 522     } else if (is_qnan(c_cls)) {
 523         return 2;
 524     } else if (is_qnan(a_cls)) {
 525         return 0;
 526     } else {
 527         return 1;
 528     }
 529 #elif defined(TARGET_MIPS)
 530     if (snan_bit_is_one(status)) {
 531         /*
 532          * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
 533          * case sets InvalidOp and returns the default NaN
 534          */
 535         if (infzero) {
 536             float_raise(float_flag_invalid | float_flag_invalid_imz, status);
 537             return 3;
 538         }
 539         /* Prefer sNaN over qNaN, in the a, b, c order. */
 540         if (is_snan(a_cls)) {
 541             return 0;
 542         } else if (is_snan(b_cls)) {
 543             return 1;
 544         } else if (is_snan(c_cls)) {
 545             return 2;
 546         } else if (is_qnan(a_cls)) {
 547             return 0;
 548         } else if (is_qnan(b_cls)) {
 549             return 1;
 550         } else {
 551             return 2;
 552         }
 553     } else {
 554         /*
 555          * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
 556          * case sets InvalidOp and returns the input value 'c'
 557          */
 558         if (infzero) {
 559             float_raise(float_flag_invalid | float_flag_invalid_imz, status);
 560             return 2;
 561         }
 562         /* Prefer sNaN over qNaN, in the c, a, b order. */
 563         if (is_snan(c_cls)) {
 564             return 2;
 565         } else if (is_snan(a_cls)) {
 566             return 0;
 567         } else if (is_snan(b_cls)) {
 568             return 1;
 569         } else if (is_qnan(c_cls)) {
 570             return 2;
 571         } else if (is_qnan(a_cls)) {
 572             return 0;
 573         } else {
 574             return 1;
 575         }
 576     }
 577 #elif defined(TARGET_PPC)
 578     /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
 579      * to return an input NaN if we have one (ie c) rather than generating
 580      * a default NaN
 581      */
 582     if (infzero) {
 583         float_raise(float_flag_invalid | float_flag_invalid_imz, status);
 584         return 2;
 585     }
 586
 587     /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
 588      * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
 589      */
 590     if (is_nan(a_cls)) {
 591         return 0;
 592     } else if (is_nan(c_cls)) {
 593         return 2;
 594     } else {
 595         return 1;
 596     }
 597 #elif defined(TARGET_RISCV)
 598     /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
 599     if (infzero) {
 600         float_raise(float_flag_invalid | float_flag_invalid_imz, status);
 601     }
 602     return 3; /* default NaN */
 603 #elif defined(TARGET_XTENSA)
 604     /*
 605      * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
 606      * an input NaN if we have one (ie c).
 607      */
 608     if (infzero) {
 609         float_raise(float_flag_invalid | float_flag_invalid_imz, status);
 610         return 2;
 611     }
 612     if (status->use_first_nan) {
 613         if (is_nan(a_cls)) {
 614             return 0;
 615         } else if (is_nan(b_cls)) {
 616             return 1;
 617         } else {
 618             return 2;
 619         }
 620     } else {
 621         if (is_nan(c_cls)) {
 622             return 2;
 623         } else if (is_nan(b_cls)) {
 624             return 1;
 625         } else {
 626             return 0;
 627         }
 628     }
 629 #else
 630     /* A default implementation: prefer a to b to c.
 631      * This is unlikely to actually match any real implementation.
 632      */
 633     if (is_nan(a_cls)) {
 634         return 0;
 635     } else if (is_nan(b_cls)) {
 636         return 1;
 637     } else {
 638         return 2;
 639     }
 640 #endif
 641 }
 642
 643 /*----------------------------------------------------------------------------
 644 | Returns 1 if the double-precision floating-point value `a' is a quiet
 645 | NaN; otherwise returns 0.
 646 *----------------------------------------------------------------------------*/
 647
 648 bool float64_is_quiet_nan(float64 a_, float_status *status)
 649 {
 650     if (no_signaling_nans(status)) {
 651         return float64_is_any_nan(a_);
 652     } else {
 653         uint64_t a = float64_val(a_);
 654         if (snan_bit_is_one(status)) {
 655             return (((a >> 51) & 0xFFF) == 0xFFE)
 656                 && (a & 0x0007FFFFFFFFFFFFULL);
 657         } else {
 658             return ((a << 1) >= 0xFFF0000000000000ULL);
 659         }
 660     }
 661 }
 662
 663 /*----------------------------------------------------------------------------
 664 | Returns 1 if the double-precision floating-point value `a' is a signaling
 665 | NaN; otherwise returns 0.
 666 *----------------------------------------------------------------------------*/
 667
 668 bool float64_is_signaling_nan(float64 a_, float_status *status)
 669 {
 670     if (no_signaling_nans(status)) {
 671         return 0;
 672     } else {
 673         uint64_t a = float64_val(a_);
 674         if (snan_bit_is_one(status)) {
 675             return ((a << 1) >= 0xFFF0000000000000ULL);
 676         } else {
 677             return (((a >> 51) & 0xFFF) == 0xFFE)
 678                 && (a & UINT64_C(0x0007FFFFFFFFFFFF));
 679         }
 680     }
 681 }
 682
 683 /*----------------------------------------------------------------------------
 684 | Returns 1 if the extended double-precision floating-point value `a' is a
 685 | quiet NaN; otherwise returns 0. This slightly differs from the same
 686 | function for other types as floatx80 has an explicit bit.
 687 *----------------------------------------------------------------------------*/
 688
 689 int floatx80_is_quiet_nan(floatx80 a, float_status *status)
 690 {
 691     if (no_signaling_nans(status)) {
 692         return floatx80_is_any_nan(a);
 693     } else {
 694         if (snan_bit_is_one(status)) {
 695             uint64_t aLow;
 696
 697             aLow = a.low & ~0x4000000000000000ULL;
 698             return ((a.high & 0x7FFF) == 0x7FFF)
 699                 && (aLow << 1)
 700                 && (a.low == aLow);
 701         } else {
 702             return ((a.high & 0x7FFF) == 0x7FFF)
 703                 && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1)));
 704         }
 705     }
 706 }
 707
 708 /*----------------------------------------------------------------------------
 709 | Returns 1 if the extended double-precision floating-point value `a' is a
 710 | signaling NaN; otherwise returns 0. This slightly differs from the same
 711 | function for other types as floatx80 has an explicit bit.
 712 *----------------------------------------------------------------------------*/
 713
 714 int floatx80_is_signaling_nan(floatx80 a, float_status *status)
 715 {
 716     if (no_signaling_nans(status)) {
 717         return 0;
 718     } else {
 719         if (snan_bit_is_one(status)) {
 720             return ((a.high & 0x7FFF) == 0x7FFF)
 721                 && ((a.low << 1) >= 0x8000000000000000ULL);
 722         } else {
 723             uint64_t aLow;
 724
 725             aLow = a.low & ~UINT64_C(0x4000000000000000);
 726             return ((a.high & 0x7FFF) == 0x7FFF)
 727                 && (uint64_t)(aLow << 1)
 728                 && (a.low == aLow);
 729         }
 730     }
 731 }
 732
 733 /*----------------------------------------------------------------------------
 734 | Returns a quiet NaN from a signalling NaN for the extended double-precision
 735 | floating point value `a'.
 736 *----------------------------------------------------------------------------*/
 737
 738 floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
 739 {
 740     /* None of the targets that have snan_bit_is_one use floatx80.  */
 741     assert(!snan_bit_is_one(status));
 742     a.low |= UINT64_C(0xC000000000000000);
 743     return a;
 744 }
 745
 746 /*----------------------------------------------------------------------------
 747 | Takes two extended double-precision floating-point values `a' and `b', one
 748 | of which is a NaN, and returns the appropriate NaN result.  If either `a' or
 749 | `b' is a signaling NaN, the invalid exception is raised.
 750 *----------------------------------------------------------------------------*/
 751
 752 floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
 753 {
 754     bool aIsLargerSignificand;
 755     FloatClass a_cls, b_cls;
 756
 757     /* This is not complete, but is good enough for pickNaN.  */
 758     a_cls = (!floatx80_is_any_nan(a)
 759              ? float_class_normal
 760              : floatx80_is_signaling_nan(a, status)
 761              ? float_class_snan
 762              : float_class_qnan);
 763     b_cls = (!floatx80_is_any_nan(b)
 764              ? float_class_normal
 765              : floatx80_is_signaling_nan(b, status)
 766              ? float_class_snan
 767              : float_class_qnan);
 768
 769     if (is_snan(a_cls) || is_snan(b_cls)) {
 770         float_raise(float_flag_invalid, status);
 771     }
 772
 773     if (status->default_nan_mode) {
 774         return floatx80_default_nan(status);
 775     }
 776
 777     if (a.low < b.low) {
 778         aIsLargerSignificand = 0;
 779     } else if (b.low < a.low) {
 780         aIsLargerSignificand = 1;
 781     } else {
 782         aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
 783     }
 784
 785     if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
 786         if (is_snan(b_cls)) {
 787             return floatx80_silence_nan(b, status);
 788         }
 789         return b;
 790     } else {
 791         if (is_snan(a_cls)) {
 792             return floatx80_silence_nan(a, status);
 793         }
 794         return a;
 795     }
 796 }
 797
 798 /*----------------------------------------------------------------------------
 799 | Returns 1 if the quadruple-precision floating-point value `a' is a quiet
 800 | NaN; otherwise returns 0.
 801 *----------------------------------------------------------------------------*/
 802
 803 bool float128_is_quiet_nan(float128 a, float_status *status)
 804 {
 805     if (no_signaling_nans(status)) {
 806         return float128_is_any_nan(a);
 807     } else {
 808         if (snan_bit_is_one(status)) {
 809             return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
 810                 && (a.low || (a.high & 0x00007FFFFFFFFFFFULL));
 811         } else {
 812             return ((a.high << 1) >= 0xFFFF000000000000ULL)
 813                 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
 814         }
 815     }
 816 }
 817
 818 /*----------------------------------------------------------------------------
 819 | Returns 1 if the quadruple-precision floating-point value `a' is a
 820 | signaling NaN; otherwise returns 0.
 821 *----------------------------------------------------------------------------*/
 822
 823 bool float128_is_signaling_nan(float128 a, float_status *status)
 824 {
 825     if (no_signaling_nans(status)) {
 826         return 0;
 827     } else {
 828         if (snan_bit_is_one(status)) {
 829             return ((a.high << 1) >= 0xFFFF000000000000ULL)
 830                 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
 831         } else {
 832             return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
 833                 && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF)));
 834         }
 835     }
 836 }