fpu/softfloat-specialize.c.inc

   1 /*
   2  * QEMU float support
   3  *
   4  * The code in this source file is derived from release 2a of the SoftFloat
   5  * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and
   6  * some later contributions) are provided under that license, as detailed below.
   7  * It has subsequently been modified by contributors to the QEMU Project,
   8  * so some portions are provided under:
   9  *  the SoftFloat-2a license
  10  *  the BSD license
  11  *  GPL-v2-or-later
  12  *
  13  * Any future contributions to this file after December 1st 2014 will be
  14  * taken to be licensed under the Softfloat-2a license unless specifically
  15  * indicated otherwise.
  16  */
  17
  18 /*
  19 ===============================================================================
  20 This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
  21 Arithmetic Package, Release 2a.
  22
  23 Written by John R. Hauser.  This work was made possible in part by the
  24 International Computer Science Institute, located at Suite 600, 1947 Center
  25 Street, Berkeley, California 94704.  Funding was partially provided by the
  26 National Science Foundation under grant MIP-9311980.  The original version
  27 of this code was written as part of a project to build a fixed-point vector
  28 processor in collaboration with the University of California at Berkeley,
  29 overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
  30 is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
  31 arithmetic/SoftFloat.html'.
  32
  33 THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort
  34 has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
  35 TIMES RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO
  36 PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
  37 AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
  38
  39 Derivative works are acceptable, even for commercial purposes, so long as
  40 (1) they include prominent notice that the work is derivative, and (2) they
  41 include prominent notice akin to these four paragraphs for those parts of
  42 this code that are retained.
  43
  44 ===============================================================================
  45 */
  46
  47 /* BSD licensing:
  48  * Copyright (c) 2006, Fabrice Bellard
  49  * All rights reserved.
  50  *
  51  * Redistribution and use in source and binary forms, with or without
  52  * modification, are permitted provided that the following conditions are met:
  53  *
  54  * 1. Redistributions of source code must retain the above copyright notice,
  55  * this list of conditions and the following disclaimer.
  56  *
  57  * 2. Redistributions in binary form must reproduce the above copyright notice,
  58  * this list of conditions and the following disclaimer in the documentation
  59  * and/or other materials provided with the distribution.
  60  *
  61  * 3. Neither the name of the copyright holder nor the names of its contributors
  62  * may be used to endorse or promote products derived from this software without
  63  * specific prior written permission.
  64  *
  65  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  66  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  67  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  68  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  69  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  70  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  71  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  72  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  73  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  74  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  75  * THE POSSIBILITY OF SUCH DAMAGE.
  76  */
  77
  78 /* Portions of this work are licensed under the terms of the GNU GPL,
  79  * version 2 or later. See the COPYING file in the top-level directory.
  80  */
  81
  82 /*
  83  * Define whether architecture deviates from IEEE in not supporting
  84  * signaling NaNs (so all NaNs are treated as quiet).
  85  */
  86 static inline bool no_signaling_nans(float_status *status)
  87 {
  88 #if defined(TARGET_XTENSA)
  89     return status->no_signaling_nans;
  90 #else
  91     return false;
  92 #endif
  93 }
  94
  95 /* Define how the architecture discriminates signaling NaNs.
  96  * This done with the most significant bit of the fraction.
  97  * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008
  98  * the msb must be zero.  MIPS is (so far) unique in supporting both the
  99  * 2008 revision and backward compatibility with their original choice.
 100  * Thus for MIPS we must make the choice at runtime.
 101  */
 102 static inline bool snan_bit_is_one(float_status *status)
 103 {
 104 #if defined(TARGET_MIPS)
 105     return status->snan_bit_is_one;
 106 #elif defined(TARGET_HPPA) || defined(TARGET_SH4)
 107     return 1;
 108 #else
 109     return 0;
 110 #endif
 111 }
 112
 113 /*----------------------------------------------------------------------------
 114 | For the deconstructed floating-point with fraction FRAC, return true
 115 | if the fraction represents a signalling NaN; otherwise false.
 116 *----------------------------------------------------------------------------*/
 117
 118 static bool parts_is_snan_frac(uint64_t frac, float_status *status)
 119 {
 120     if (no_signaling_nans(status)) {
 121         return false;
 122     } else {
 123         bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);
 124         return msb == snan_bit_is_one(status);
 125     }
 126 }
 127
 128 /*----------------------------------------------------------------------------
 129 | The pattern for a default generated deconstructed floating-point NaN.
 130 *----------------------------------------------------------------------------*/
 131
 132 static void parts64_default_nan(FloatParts64 *p, float_status *status)
 133 {
 134     bool sign = 0;
 135     uint64_t frac;
 136
 137 #if defined(TARGET_SPARC) || defined(TARGET_M68K)
 138     /* !snan_bit_is_one, set all bits */
 139     frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
 140 #elif defined(TARGET_I386) || defined(TARGET_X86_64) \
 141     || defined(TARGET_MICROBLAZE)
 142     /* !snan_bit_is_one, set sign and msb */
 143     frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
 144     sign = 1;
 145 #elif defined(TARGET_HPPA)
 146     /* snan_bit_is_one, set msb-1.  */
 147     frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
 148 #elif defined(TARGET_HEXAGON)
 149     sign = 1;
 150     frac = ~0ULL;
 151 #else
 152     /*
 153      * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
 154      * S390, SH4, TriCore, and Xtensa.  Our other supported targets,
 155      * CRIS, Nios2, and Tile, do not have floating-point.
 156      */
 157     if (snan_bit_is_one(status)) {
 158         /* set all bits other than msb */
 159         frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
 160     } else {
 161         /* set msb */
 162         frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
 163     }
 164 #endif
 165
 166     *p = (FloatParts64) {
 167         .cls = float_class_qnan,
 168         .sign = sign,
 169         .exp = INT_MAX,
 170         .frac = frac
 171     };
 172 }
 173
 174 static void parts128_default_nan(FloatParts128 *p, float_status *status)
 175 {
 176     /*
 177      * Extrapolate from the choices made by parts64_default_nan to fill
 178      * in the quad-floating format.  If the low bit is set, assume we
 179      * want to set all non-snan bits.
 180      */
 181     FloatParts64 p64;
 182     parts64_default_nan(&p64, status);
 183
 184     *p = (FloatParts128) {
 185         .cls = float_class_qnan,
 186         .sign = p64.sign,
 187         .exp = INT_MAX,
 188         .frac_hi = p64.frac,
 189         .frac_lo = -(p64.frac & 1)
 190     };
 191 }
 192
 193 /*----------------------------------------------------------------------------
 194 | Returns a quiet NaN from a signalling NaN for the deconstructed
 195 | floating-point parts.
 196 *----------------------------------------------------------------------------*/
 197
 198 static uint64_t parts_silence_nan_frac(uint64_t frac, float_status *status)
 199 {
 200     g_assert(!no_signaling_nans(status));
 201     g_assert(!status->default_nan_mode);
 202
 203     /* The only snan_bit_is_one target without default_nan_mode is HPPA. */
 204     if (snan_bit_is_one(status)) {
 205         frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1));
 206         frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2);
 207     } else {
 208         frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1);
 209     }
 210     return frac;
 211 }
 212
 213 static void parts64_silence_nan(FloatParts64 *p, float_status *status)
 214 {
 215     p->frac = parts_silence_nan_frac(p->frac, status);
 216     p->cls = float_class_qnan;
 217 }
 218
 219 static void parts128_silence_nan(FloatParts128 *p, float_status *status)
 220 {
 221     p->frac_hi = parts_silence_nan_frac(p->frac_hi, status);
 222     p->cls = float_class_qnan;
 223 }
 224
 225 /*----------------------------------------------------------------------------
 226 | The pattern for a default generated extended double-precision NaN.
 227 *----------------------------------------------------------------------------*/
 228 floatx80 floatx80_default_nan(float_status *status)
 229 {
 230     floatx80 r;
 231
 232     /* None of the targets that have snan_bit_is_one use floatx80.  */
 233     assert(!snan_bit_is_one(status));
 234 #if defined(TARGET_M68K)
 235     r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
 236     r.high = 0x7FFF;
 237 #else
 238     /* X86 */
 239     r.low = UINT64_C(0xC000000000000000);
 240     r.high = 0xFFFF;
 241 #endif
 242     return r;
 243 }
 244
 245 /*----------------------------------------------------------------------------
 246 | The pattern for a default generated extended double-precision inf.
 247 *----------------------------------------------------------------------------*/
 248
 249 #define floatx80_infinity_high 0x7FFF
 250 #if defined(TARGET_M68K)
 251 #define floatx80_infinity_low  UINT64_C(0x0000000000000000)
 252 #else
 253 #define floatx80_infinity_low  UINT64_C(0x8000000000000000)
 254 #endif
 255
 256 const floatx80 floatx80_infinity
 257     = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low);
 258
 259 /*----------------------------------------------------------------------------
 260 | Internal canonical NaN format.
 261 *----------------------------------------------------------------------------*/
 262 typedef struct {
 263     bool sign;
 264     uint64_t high, low;
 265 } commonNaNT;
 266
 267 /*----------------------------------------------------------------------------
 268 | Returns 1 if the half-precision floating-point value `a' is a quiet
 269 | NaN; otherwise returns 0.
 270 *----------------------------------------------------------------------------*/
 271
 272 bool float16_is_quiet_nan(float16 a_, float_status *status)
 273 {
 274     if (no_signaling_nans(status)) {
 275         return float16_is_any_nan(a_);
 276     } else {
 277         uint16_t a = float16_val(a_);
 278         if (snan_bit_is_one(status)) {
 279             return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
 280         } else {
 281
 282             return ((a >> 9) & 0x3F) == 0x3F;
 283         }
 284     }
 285 }
 286
 287 /*----------------------------------------------------------------------------
 288 | Returns 1 if the bfloat16 value `a' is a quiet
 289 | NaN; otherwise returns 0.
 290 *----------------------------------------------------------------------------*/
 291
 292 bool bfloat16_is_quiet_nan(bfloat16 a_, float_status *status)
 293 {
 294     if (no_signaling_nans(status)) {
 295         return bfloat16_is_any_nan(a_);
 296     } else {
 297         uint16_t a = a_;
 298         if (snan_bit_is_one(status)) {
 299             return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F);
 300         } else {
 301             return ((a >> 6) & 0x1FF) == 0x1FF;
 302         }
 303     }
 304 }
 305
 306 /*----------------------------------------------------------------------------
 307 | Returns 1 if the half-precision floating-point value `a' is a signaling
 308 | NaN; otherwise returns 0.
 309 *----------------------------------------------------------------------------*/
 310
 311 bool float16_is_signaling_nan(float16 a_, float_status *status)
 312 {
 313     if (no_signaling_nans(status)) {
 314         return 0;
 315     } else {
 316         uint16_t a = float16_val(a_);
 317         if (snan_bit_is_one(status)) {
 318             return ((a >> 9) & 0x3F) == 0x3F;
 319         } else {
 320             return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
 321         }
 322     }
 323 }
 324
 325 /*----------------------------------------------------------------------------
 326 | Returns 1 if the bfloat16 value `a' is a signaling
 327 | NaN; otherwise returns 0.
 328 *----------------------------------------------------------------------------*/
 329
 330 bool bfloat16_is_signaling_nan(bfloat16 a_, float_status *status)
 331 {
 332     if (no_signaling_nans(status)) {
 333         return 0;
 334     } else {
 335         uint16_t a = a_;
 336         if (snan_bit_is_one(status)) {
 337             return ((a >> 6) & 0x1FF) == 0x1FF;
 338         } else {
 339             return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F);
 340         }
 341     }
 342 }
 343
 344 /*----------------------------------------------------------------------------
 345 | Returns 1 if the single-precision floating-point value `a' is a quiet
 346 | NaN; otherwise returns 0.
 347 *----------------------------------------------------------------------------*/
 348
 349 bool float32_is_quiet_nan(float32 a_, float_status *status)
 350 {
 351     if (no_signaling_nans(status)) {
 352         return float32_is_any_nan(a_);
 353     } else {
 354         uint32_t a = float32_val(a_);
 355         if (snan_bit_is_one(status)) {
 356             return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
 357         } else {
 358             return ((uint32_t)(a << 1) >= 0xFF800000);
 359         }
 360     }
 361 }
 362
 363 /*----------------------------------------------------------------------------
 364 | Returns 1 if the single-precision floating-point value `a' is a signaling
 365 | NaN; otherwise returns 0.
 366 *----------------------------------------------------------------------------*/
 367
 368 bool float32_is_signaling_nan(float32 a_, float_status *status)
 369 {
 370     if (no_signaling_nans(status)) {
 371         return 0;
 372     } else {
 373         uint32_t a = float32_val(a_);
 374         if (snan_bit_is_one(status)) {
 375             return ((uint32_t)(a << 1) >= 0xFF800000);
 376         } else {
 377             return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
 378         }
 379     }
 380 }
 381
 382 /*----------------------------------------------------------------------------
 383 | Returns the result of converting the single-precision floating-point NaN
 384 | `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
 385 | exception is raised.
 386 *----------------------------------------------------------------------------*/
 387
 388 static commonNaNT float32ToCommonNaN(float32 a, float_status *status)
 389 {
 390     commonNaNT z;
 391
 392     if (float32_is_signaling_nan(a, status)) {
 393         float_raise(float_flag_invalid, status);
 394     }
 395     z.sign = float32_val(a) >> 31;
 396     z.low = 0;
 397     z.high = ((uint64_t)float32_val(a)) << 41;
 398     return z;
 399 }
 400
 401 /*----------------------------------------------------------------------------
 402 | Returns the result of converting the canonical NaN `a' to the single-
 403 | precision floating-point format.
 404 *----------------------------------------------------------------------------*/
 405
 406 static float32 commonNaNToFloat32(commonNaNT a, float_status *status)
 407 {
 408     uint32_t mantissa = a.high >> 41;
 409
 410     if (status->default_nan_mode) {
 411         return float32_default_nan(status);
 412     }
 413
 414     if (mantissa) {
 415         return make_float32(
 416             (((uint32_t)a.sign) << 31) | 0x7F800000 | (a.high >> 41));
 417     } else {
 418         return float32_default_nan(status);
 419     }
 420 }
 421
 422 /*----------------------------------------------------------------------------
 423 | Select which NaN to propagate for a two-input operation.
 424 | IEEE754 doesn't specify all the details of this, so the
 425 | algorithm is target-specific.
 426 | The routine is passed various bits of information about the
 427 | two NaNs and should return 0 to select NaN a and 1 for NaN b.
 428 | Note that signalling NaNs are always squashed to quiet NaNs
 429 | by the caller, by calling floatXX_silence_nan() before
 430 | returning them.
 431 |
 432 | aIsLargerSignificand is only valid if both a and b are NaNs
 433 | of some kind, and is true if a has the larger significand,
 434 | or if both a and b have the same significand but a is
 435 | positive but b is negative. It is only needed for the x87
 436 | tie-break rule.
 437 *----------------------------------------------------------------------------*/
 438
 439 static int pickNaN(FloatClass a_cls, FloatClass b_cls,
 440                    bool aIsLargerSignificand, float_status *status)
 441 {
 442 #if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA)
 443     /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take
 444      * the first of:
 445      *  1. A if it is signaling
 446      *  2. B if it is signaling
 447      *  3. A (quiet)
 448      *  4. B (quiet)
 449      * A signaling NaN is always quietened before returning it.
 450      */
 451     /* According to MIPS specifications, if one of the two operands is
 452      * a sNaN, a new qNaN has to be generated. This is done in
 453      * floatXX_silence_nan(). For qNaN inputs the specifications
 454      * says: "When possible, this QNaN result is one of the operand QNaN
 455      * values." In practice it seems that most implementations choose
 456      * the first operand if both operands are qNaN. In short this gives
 457      * the following rules:
 458      *  1. A if it is signaling
 459      *  2. B if it is signaling
 460      *  3. A (quiet)
 461      *  4. B (quiet)
 462      * A signaling NaN is always silenced before returning it.
 463      */
 464     if (is_snan(a_cls)) {
 465         return 0;
 466     } else if (is_snan(b_cls)) {
 467         return 1;
 468     } else if (is_qnan(a_cls)) {
 469         return 0;
 470     } else {
 471         return 1;
 472     }
 473 #elif defined(TARGET_PPC) || defined(TARGET_M68K)
 474     /* PowerPC propagation rules:
 475      *  1. A if it sNaN or qNaN
 476      *  2. B if it sNaN or qNaN
 477      * A signaling NaN is always silenced before returning it.
 478      */
 479     /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
 480      * 3.4 FLOATING-POINT INSTRUCTION DETAILS
 481      * If either operand, but not both operands, of an operation is a
 482      * nonsignaling NaN, then that NaN is returned as the result. If both
 483      * operands are nonsignaling NaNs, then the destination operand
 484      * nonsignaling NaN is returned as the result.
 485      * If either operand to an operation is a signaling NaN (SNaN), then the
 486      * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit
 487      * is set in the FPCR ENABLE byte, then the exception is taken and the
 488      * destination is not modified. If the SNaN exception enable bit is not
 489      * set, setting the SNaN bit in the operand to a one converts the SNaN to
 490      * a nonsignaling NaN. The operation then continues as described in the
 491      * preceding paragraph for nonsignaling NaNs.
 492      */
 493     if (is_nan(a_cls)) {
 494         return 0;
 495     } else {
 496         return 1;
 497     }
 498 #elif defined(TARGET_XTENSA)
 499     /*
 500      * Xtensa has two NaN propagation modes.
 501      * Which one is active is controlled by float_status::use_first_nan.
 502      */
 503     if (status->use_first_nan) {
 504         if (is_nan(a_cls)) {
 505             return 0;
 506         } else {
 507             return 1;
 508         }
 509     } else {
 510         if (is_nan(b_cls)) {
 511             return 1;
 512         } else {
 513             return 0;
 514         }
 515     }
 516 #else
 517     /* This implements x87 NaN propagation rules:
 518      * SNaN + QNaN => return the QNaN
 519      * two SNaNs => return the one with the larger significand, silenced
 520      * two QNaNs => return the one with the larger significand
 521      * SNaN and a non-NaN => return the SNaN, silenced
 522      * QNaN and a non-NaN => return the QNaN
 523      *
 524      * If we get down to comparing significands and they are the same,
 525      * return the NaN with the positive sign bit (if any).
 526      */
 527     if (is_snan(a_cls)) {
 528         if (is_snan(b_cls)) {
 529             return aIsLargerSignificand ? 0 : 1;
 530         }
 531         return is_qnan(b_cls) ? 1 : 0;
 532     } else if (is_qnan(a_cls)) {
 533         if (is_snan(b_cls) || !is_qnan(b_cls)) {
 534             return 0;
 535         } else {
 536             return aIsLargerSignificand ? 0 : 1;
 537         }
 538     } else {
 539         return 1;
 540     }
 541 #endif
 542 }
 543
 544 /*----------------------------------------------------------------------------
 545 | Select which NaN to propagate for a three-input operation.
 546 | For the moment we assume that no CPU needs the 'larger significand'
 547 | information.
 548 | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
 549 *----------------------------------------------------------------------------*/
 550 static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
 551                          bool infzero, float_status *status)
 552 {
 553 #if defined(TARGET_ARM)
 554     /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
 555      * the default NaN
 556      */
 557     if (infzero && is_qnan(c_cls)) {
 558         float_raise(float_flag_invalid, status);
 559         return 3;
 560     }
 561
 562     /* This looks different from the ARM ARM pseudocode, because the ARM ARM
 563      * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
 564      */
 565     if (is_snan(c_cls)) {
 566         return 2;
 567     } else if (is_snan(a_cls)) {
 568         return 0;
 569     } else if (is_snan(b_cls)) {
 570         return 1;
 571     } else if (is_qnan(c_cls)) {
 572         return 2;
 573     } else if (is_qnan(a_cls)) {
 574         return 0;
 575     } else {
 576         return 1;
 577     }
 578 #elif defined(TARGET_MIPS)
 579     if (snan_bit_is_one(status)) {
 580         /*
 581          * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
 582          * case sets InvalidOp and returns the default NaN
 583          */
 584         if (infzero) {
 585             float_raise(float_flag_invalid, status);
 586             return 3;
 587         }
 588         /* Prefer sNaN over qNaN, in the a, b, c order. */
 589         if (is_snan(a_cls)) {
 590             return 0;
 591         } else if (is_snan(b_cls)) {
 592             return 1;
 593         } else if (is_snan(c_cls)) {
 594             return 2;
 595         } else if (is_qnan(a_cls)) {
 596             return 0;
 597         } else if (is_qnan(b_cls)) {
 598             return 1;
 599         } else {
 600             return 2;
 601         }
 602     } else {
 603         /*
 604          * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
 605          * case sets InvalidOp and returns the input value 'c'
 606          */
 607         if (infzero) {
 608             float_raise(float_flag_invalid, status);
 609             return 2;
 610         }
 611         /* Prefer sNaN over qNaN, in the c, a, b order. */
 612         if (is_snan(c_cls)) {
 613             return 2;
 614         } else if (is_snan(a_cls)) {
 615             return 0;
 616         } else if (is_snan(b_cls)) {
 617             return 1;
 618         } else if (is_qnan(c_cls)) {
 619             return 2;
 620         } else if (is_qnan(a_cls)) {
 621             return 0;
 622         } else {
 623             return 1;
 624         }
 625     }
 626 #elif defined(TARGET_PPC)
 627     /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
 628      * to return an input NaN if we have one (ie c) rather than generating
 629      * a default NaN
 630      */
 631     if (infzero) {
 632         float_raise(float_flag_invalid, status);
 633         return 2;
 634     }
 635
 636     /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
 637      * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
 638      */
 639     if (is_nan(a_cls)) {
 640         return 0;
 641     } else if (is_nan(c_cls)) {
 642         return 2;
 643     } else {
 644         return 1;
 645     }
 646 #elif defined(TARGET_RISCV)
 647     /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
 648     if (infzero) {
 649         float_raise(float_flag_invalid, status);
 650     }
 651     return 3; /* default NaN */
 652 #elif defined(TARGET_XTENSA)
 653     /*
 654      * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
 655      * an input NaN if we have one (ie c).
 656      */
 657     if (infzero) {
 658         float_raise(float_flag_invalid, status);
 659         return 2;
 660     }
 661     if (status->use_first_nan) {
 662         if (is_nan(a_cls)) {
 663             return 0;
 664         } else if (is_nan(b_cls)) {
 665             return 1;
 666         } else {
 667             return 2;
 668         }
 669     } else {
 670         if (is_nan(c_cls)) {
 671             return 2;
 672         } else if (is_nan(b_cls)) {
 673             return 1;
 674         } else {
 675             return 0;
 676         }
 677     }
 678 #else
 679     /* A default implementation: prefer a to b to c.
 680      * This is unlikely to actually match any real implementation.
 681      */
 682     if (is_nan(a_cls)) {
 683         return 0;
 684     } else if (is_nan(b_cls)) {
 685         return 1;
 686     } else {
 687         return 2;
 688     }
 689 #endif
 690 }
 691
 692 /*----------------------------------------------------------------------------
 693 | Takes two single-precision floating-point values `a' and `b', one of which
 694 | is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a
 695 | signaling NaN, the invalid exception is raised.
 696 *----------------------------------------------------------------------------*/
 697
 698 static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status)
 699 {
 700     bool aIsLargerSignificand;
 701     uint32_t av, bv;
 702     FloatClass a_cls, b_cls;
 703
 704     /* This is not complete, but is good enough for pickNaN.  */
 705     a_cls = (!float32_is_any_nan(a)
 706              ? float_class_normal
 707              : float32_is_signaling_nan(a, status)
 708              ? float_class_snan
 709              : float_class_qnan);
 710     b_cls = (!float32_is_any_nan(b)
 711              ? float_class_normal
 712              : float32_is_signaling_nan(b, status)
 713              ? float_class_snan
 714              : float_class_qnan);
 715
 716     av = float32_val(a);
 717     bv = float32_val(b);
 718
 719     if (is_snan(a_cls) || is_snan(b_cls)) {
 720         float_raise(float_flag_invalid, status);
 721     }
 722
 723     if (status->default_nan_mode) {
 724         return float32_default_nan(status);
 725     }
 726
 727     if ((uint32_t)(av << 1) < (uint32_t)(bv << 1)) {
 728         aIsLargerSignificand = 0;
 729     } else if ((uint32_t)(bv << 1) < (uint32_t)(av << 1)) {
 730         aIsLargerSignificand = 1;
 731     } else {
 732         aIsLargerSignificand = (av < bv) ? 1 : 0;
 733     }
 734
 735     if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
 736         if (is_snan(b_cls)) {
 737             return float32_silence_nan(b, status);
 738         }
 739         return b;
 740     } else {
 741         if (is_snan(a_cls)) {
 742             return float32_silence_nan(a, status);
 743         }
 744         return a;
 745     }
 746 }
 747
 748 /*----------------------------------------------------------------------------
 749 | Returns 1 if the double-precision floating-point value `a' is a quiet
 750 | NaN; otherwise returns 0.
 751 *----------------------------------------------------------------------------*/
 752
 753 bool float64_is_quiet_nan(float64 a_, float_status *status)
 754 {
 755     if (no_signaling_nans(status)) {
 756         return float64_is_any_nan(a_);
 757     } else {
 758         uint64_t a = float64_val(a_);
 759         if (snan_bit_is_one(status)) {
 760             return (((a >> 51) & 0xFFF) == 0xFFE)
 761                 && (a & 0x0007FFFFFFFFFFFFULL);
 762         } else {
 763             return ((a << 1) >= 0xFFF0000000000000ULL);
 764         }
 765     }
 766 }
 767
 768 /*----------------------------------------------------------------------------
 769 | Returns 1 if the double-precision floating-point value `a' is a signaling
 770 | NaN; otherwise returns 0.
 771 *----------------------------------------------------------------------------*/
 772
 773 bool float64_is_signaling_nan(float64 a_, float_status *status)
 774 {
 775     if (no_signaling_nans(status)) {
 776         return 0;
 777     } else {
 778         uint64_t a = float64_val(a_);
 779         if (snan_bit_is_one(status)) {
 780             return ((a << 1) >= 0xFFF0000000000000ULL);
 781         } else {
 782             return (((a >> 51) & 0xFFF) == 0xFFE)
 783                 && (a & UINT64_C(0x0007FFFFFFFFFFFF));
 784         }
 785     }
 786 }
 787
 788 /*----------------------------------------------------------------------------
 789 | Returns the result of converting the double-precision floating-point NaN
 790 | `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
 791 | exception is raised.
 792 *----------------------------------------------------------------------------*/
 793
 794 static commonNaNT float64ToCommonNaN(float64 a, float_status *status)
 795 {
 796     commonNaNT z;
 797
 798     if (float64_is_signaling_nan(a, status)) {
 799         float_raise(float_flag_invalid, status);
 800     }
 801     z.sign = float64_val(a) >> 63;
 802     z.low = 0;
 803     z.high = float64_val(a) << 12;
 804     return z;
 805 }
 806
 807 /*----------------------------------------------------------------------------
 808 | Returns the result of converting the canonical NaN `a' to the double-
 809 | precision floating-point format.
 810 *----------------------------------------------------------------------------*/
 811
 812 static float64 commonNaNToFloat64(commonNaNT a, float_status *status)
 813 {
 814     uint64_t mantissa = a.high >> 12;
 815
 816     if (status->default_nan_mode) {
 817         return float64_default_nan(status);
 818     }
 819
 820     if (mantissa) {
 821         return make_float64(
 822               (((uint64_t) a.sign) << 63)
 823             | UINT64_C(0x7FF0000000000000)
 824             | (a.high >> 12));
 825     } else {
 826         return float64_default_nan(status);
 827     }
 828 }
 829
 830 /*----------------------------------------------------------------------------
 831 | Takes two double-precision floating-point values `a' and `b', one of which
 832 | is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a
 833 | signaling NaN, the invalid exception is raised.
 834 *----------------------------------------------------------------------------*/
 835
 836 static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status)
 837 {
 838     bool aIsLargerSignificand;
 839     uint64_t av, bv;
 840     FloatClass a_cls, b_cls;
 841
 842     /* This is not complete, but is good enough for pickNaN.  */
 843     a_cls = (!float64_is_any_nan(a)
 844              ? float_class_normal
 845              : float64_is_signaling_nan(a, status)
 846              ? float_class_snan
 847              : float_class_qnan);
 848     b_cls = (!float64_is_any_nan(b)
 849              ? float_class_normal
 850              : float64_is_signaling_nan(b, status)
 851              ? float_class_snan
 852              : float_class_qnan);
 853
 854     av = float64_val(a);
 855     bv = float64_val(b);
 856
 857     if (is_snan(a_cls) || is_snan(b_cls)) {
 858         float_raise(float_flag_invalid, status);
 859     }
 860
 861     if (status->default_nan_mode) {
 862         return float64_default_nan(status);
 863     }
 864
 865     if ((uint64_t)(av << 1) < (uint64_t)(bv << 1)) {
 866         aIsLargerSignificand = 0;
 867     } else if ((uint64_t)(bv << 1) < (uint64_t)(av << 1)) {
 868         aIsLargerSignificand = 1;
 869     } else {
 870         aIsLargerSignificand = (av < bv) ? 1 : 0;
 871     }
 872
 873     if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
 874         if (is_snan(b_cls)) {
 875             return float64_silence_nan(b, status);
 876         }
 877         return b;
 878     } else {
 879         if (is_snan(a_cls)) {
 880             return float64_silence_nan(a, status);
 881         }
 882         return a;
 883     }
 884 }
 885
 886 /*----------------------------------------------------------------------------
 887 | Returns 1 if the extended double-precision floating-point value `a' is a
 888 | quiet NaN; otherwise returns 0. This slightly differs from the same
 889 | function for other types as floatx80 has an explicit bit.
 890 *----------------------------------------------------------------------------*/
 891
 892 int floatx80_is_quiet_nan(floatx80 a, float_status *status)
 893 {
 894     if (no_signaling_nans(status)) {
 895         return floatx80_is_any_nan(a);
 896     } else {
 897         if (snan_bit_is_one(status)) {
 898             uint64_t aLow;
 899
 900             aLow = a.low & ~0x4000000000000000ULL;
 901             return ((a.high & 0x7FFF) == 0x7FFF)
 902                 && (aLow << 1)
 903                 && (a.low == aLow);
 904         } else {
 905             return ((a.high & 0x7FFF) == 0x7FFF)
 906                 && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1)));
 907         }
 908     }
 909 }
 910
 911 /*----------------------------------------------------------------------------
 912 | Returns 1 if the extended double-precision floating-point value `a' is a
 913 | signaling NaN; otherwise returns 0. This slightly differs from the same
 914 | function for other types as floatx80 has an explicit bit.
 915 *----------------------------------------------------------------------------*/
 916
 917 int floatx80_is_signaling_nan(floatx80 a, float_status *status)
 918 {
 919     if (no_signaling_nans(status)) {
 920         return 0;
 921     } else {
 922         if (snan_bit_is_one(status)) {
 923             return ((a.high & 0x7FFF) == 0x7FFF)
 924                 && ((a.low << 1) >= 0x8000000000000000ULL);
 925         } else {
 926             uint64_t aLow;
 927
 928             aLow = a.low & ~UINT64_C(0x4000000000000000);
 929             return ((a.high & 0x7FFF) == 0x7FFF)
 930                 && (uint64_t)(aLow << 1)
 931                 && (a.low == aLow);
 932         }
 933     }
 934 }
 935
 936 /*----------------------------------------------------------------------------
 937 | Returns a quiet NaN from a signalling NaN for the extended double-precision
 938 | floating point value `a'.
 939 *----------------------------------------------------------------------------*/
 940
 941 floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
 942 {
 943     /* None of the targets that have snan_bit_is_one use floatx80.  */
 944     assert(!snan_bit_is_one(status));
 945     a.low |= UINT64_C(0xC000000000000000);
 946     return a;
 947 }
 948
 949 /*----------------------------------------------------------------------------
 950 | Returns the result of converting the extended double-precision floating-
 951 | point NaN `a' to the canonical NaN format.  If `a' is a signaling NaN, the
 952 | invalid exception is raised.
 953 *----------------------------------------------------------------------------*/
 954
 955 static commonNaNT floatx80ToCommonNaN(floatx80 a, float_status *status)
 956 {
 957     floatx80 dflt;
 958     commonNaNT z;
 959
 960     if (floatx80_is_signaling_nan(a, status)) {
 961         float_raise(float_flag_invalid, status);
 962     }
 963     if (a.low >> 63) {
 964         z.sign = a.high >> 15;
 965         z.low = 0;
 966         z.high = a.low << 1;
 967     } else {
 968         dflt = floatx80_default_nan(status);
 969         z.sign = dflt.high >> 15;
 970         z.low = 0;
 971         z.high = dflt.low << 1;
 972     }
 973     return z;
 974 }
 975
 976 /*----------------------------------------------------------------------------
 977 | Returns the result of converting the canonical NaN `a' to the extended
 978 | double-precision floating-point format.
 979 *----------------------------------------------------------------------------*/
 980
 981 static floatx80 commonNaNToFloatx80(commonNaNT a, float_status *status)
 982 {
 983     floatx80 z;
 984
 985     if (status->default_nan_mode) {
 986         return floatx80_default_nan(status);
 987     }
 988
 989     if (a.high >> 1) {
 990         z.low = UINT64_C(0x8000000000000000) | a.high >> 1;
 991         z.high = (((uint16_t)a.sign) << 15) | 0x7FFF;
 992     } else {
 993         z = floatx80_default_nan(status);
 994     }
 995     return z;
 996 }
 997
 998 /*----------------------------------------------------------------------------
 999 | Takes two extended double-precision floating-point values `a' and `b', one
1000 | of which is a NaN, and returns the appropriate NaN result.  If either `a' or
1001 | `b' is a signaling NaN, the invalid exception is raised.
1002 *----------------------------------------------------------------------------*/
1003
1004 floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
1005 {
1006     bool aIsLargerSignificand;
1007     FloatClass a_cls, b_cls;
1008
1009     /* This is not complete, but is good enough for pickNaN.  */
1010     a_cls = (!floatx80_is_any_nan(a)
1011              ? float_class_normal
1012              : floatx80_is_signaling_nan(a, status)
1013              ? float_class_snan
1014              : float_class_qnan);
1015     b_cls = (!floatx80_is_any_nan(b)
1016              ? float_class_normal
1017              : floatx80_is_signaling_nan(b, status)
1018              ? float_class_snan
1019              : float_class_qnan);
1020
1021     if (is_snan(a_cls) || is_snan(b_cls)) {
1022         float_raise(float_flag_invalid, status);
1023     }
1024
1025     if (status->default_nan_mode) {
1026         return floatx80_default_nan(status);
1027     }
1028
1029     if (a.low < b.low) {
1030         aIsLargerSignificand = 0;
1031     } else if (b.low < a.low) {
1032         aIsLargerSignificand = 1;
1033     } else {
1034         aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
1035     }
1036
1037     if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
1038         if (is_snan(b_cls)) {
1039             return floatx80_silence_nan(b, status);
1040         }
1041         return b;
1042     } else {
1043         if (is_snan(a_cls)) {
1044             return floatx80_silence_nan(a, status);
1045         }
1046         return a;
1047     }
1048 }
1049
1050 /*----------------------------------------------------------------------------
1051 | Returns 1 if the quadruple-precision floating-point value `a' is a quiet
1052 | NaN; otherwise returns 0.
1053 *----------------------------------------------------------------------------*/
1054
1055 bool float128_is_quiet_nan(float128 a, float_status *status)
1056 {
1057     if (no_signaling_nans(status)) {
1058         return float128_is_any_nan(a);
1059     } else {
1060         if (snan_bit_is_one(status)) {
1061             return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
1062                 && (a.low || (a.high & 0x00007FFFFFFFFFFFULL));
1063         } else {
1064             return ((a.high << 1) >= 0xFFFF000000000000ULL)
1065                 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
1066         }
1067     }
1068 }
1069
1070 /*----------------------------------------------------------------------------
1071 | Returns 1 if the quadruple-precision floating-point value `a' is a
1072 | signaling NaN; otherwise returns 0.
1073 *----------------------------------------------------------------------------*/
1074
1075 bool float128_is_signaling_nan(float128 a, float_status *status)
1076 {
1077     if (no_signaling_nans(status)) {
1078         return 0;
1079     } else {
1080         if (snan_bit_is_one(status)) {
1081             return ((a.high << 1) >= 0xFFFF000000000000ULL)
1082                 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
1083         } else {
1084             return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
1085                 && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF)));
1086         }
1087     }
1088 }
1089
1090 /*----------------------------------------------------------------------------
1091 | Returns the result of converting the quadruple-precision floating-point NaN
1092 | `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
1093 | exception is raised.
1094 *----------------------------------------------------------------------------*/
1095
1096 static commonNaNT float128ToCommonNaN(float128 a, float_status *status)
1097 {
1098     commonNaNT z;
1099
1100     if (float128_is_signaling_nan(a, status)) {
1101         float_raise(float_flag_invalid, status);
1102     }
1103     z.sign = a.high >> 63;
1104     shortShift128Left(a.high, a.low, 16, &z.high, &z.low);
1105     return z;
1106 }
1107
1108 /*----------------------------------------------------------------------------
1109 | Returns the result of converting the canonical NaN `a' to the quadruple-
1110 | precision floating-point format.
1111 *----------------------------------------------------------------------------*/
1112
1113 static float128 commonNaNToFloat128(commonNaNT a, float_status *status)
1114 {
1115     float128 z;
1116
1117     if (status->default_nan_mode) {
1118         return float128_default_nan(status);
1119     }
1120
1121     shift128Right(a.high, a.low, 16, &z.high, &z.low);
1122     z.high |= (((uint64_t)a.sign) << 63) | UINT64_C(0x7FFF000000000000);
1123     return z;
1124 }
1125
1126 /*----------------------------------------------------------------------------
1127 | Takes two quadruple-precision floating-point values `a' and `b', one of
1128 | which is a NaN, and returns the appropriate NaN result.  If either `a' or
1129 | `b' is a signaling NaN, the invalid exception is raised.
1130 *----------------------------------------------------------------------------*/
1131
1132 static float128 propagateFloat128NaN(float128 a, float128 b,
1133                                      float_status *status)
1134 {
1135     bool aIsLargerSignificand;
1136     FloatClass a_cls, b_cls;
1137
1138     /* This is not complete, but is good enough for pickNaN.  */
1139     a_cls = (!float128_is_any_nan(a)
1140              ? float_class_normal
1141              : float128_is_signaling_nan(a, status)
1142              ? float_class_snan
1143              : float_class_qnan);
1144     b_cls = (!float128_is_any_nan(b)
1145              ? float_class_normal
1146              : float128_is_signaling_nan(b, status)
1147              ? float_class_snan
1148              : float_class_qnan);
1149
1150     if (is_snan(a_cls) || is_snan(b_cls)) {
1151         float_raise(float_flag_invalid, status);
1152     }
1153
1154     if (status->default_nan_mode) {
1155         return float128_default_nan(status);
1156     }
1157
1158     if (lt128(a.high << 1, a.low, b.high << 1, b.low)) {
1159         aIsLargerSignificand = 0;
1160     } else if (lt128(b.high << 1, b.low, a.high << 1, a.low)) {
1161         aIsLargerSignificand = 1;
1162     } else {
1163         aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
1164     }
1165
1166     if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
1167         if (is_snan(b_cls)) {
1168             return float128_silence_nan(b, status);
1169         }
1170         return b;
1171     } else {
1172         if (is_snan(a_cls)) {
1173             return float128_silence_nan(a, status);
1174         }
1175         return a;
1176     }
1177 }