fpu/softfloat-specialize.c.inc

   1 /*
   2  * QEMU float support
   3  *
   4  * The code in this source file is derived from release 2a of the SoftFloat
   5  * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and
   6  * some later contributions) are provided under that license, as detailed below.
   7  * It has subsequently been modified by contributors to the QEMU Project,
   8  * so some portions are provided under:
   9  *  the SoftFloat-2a license
  10  *  the BSD license
  11  *  GPL-v2-or-later
  12  *
  13  * Any future contributions to this file after December 1st 2014 will be
  14  * taken to be licensed under the Softfloat-2a license unless specifically
  15  * indicated otherwise.
  16  */
  17
  18 /*
  19 ===============================================================================
  20 This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
  21 Arithmetic Package, Release 2a.
  22
  23 Written by John R. Hauser.  This work was made possible in part by the
  24 International Computer Science Institute, located at Suite 600, 1947 Center
  25 Street, Berkeley, California 94704.  Funding was partially provided by the
  26 National Science Foundation under grant MIP-9311980.  The original version
  27 of this code was written as part of a project to build a fixed-point vector
  28 processor in collaboration with the University of California at Berkeley,
  29 overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
  30 is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
  31 arithmetic/SoftFloat.html'.
  32
  33 THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort
  34 has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
  35 TIMES RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO
  36 PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
  37 AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
  38
  39 Derivative works are acceptable, even for commercial purposes, so long as
  40 (1) they include prominent notice that the work is derivative, and (2) they
  41 include prominent notice akin to these four paragraphs for those parts of
  42 this code that are retained.
  43
  44 ===============================================================================
  45 */
  46
  47 /* BSD licensing:
  48  * Copyright (c) 2006, Fabrice Bellard
  49  * All rights reserved.
  50  *
  51  * Redistribution and use in source and binary forms, with or without
  52  * modification, are permitted provided that the following conditions are met:
  53  *
  54  * 1. Redistributions of source code must retain the above copyright notice,
  55  * this list of conditions and the following disclaimer.
  56  *
  57  * 2. Redistributions in binary form must reproduce the above copyright notice,
  58  * this list of conditions and the following disclaimer in the documentation
  59  * and/or other materials provided with the distribution.
  60  *
  61  * 3. Neither the name of the copyright holder nor the names of its contributors
  62  * may be used to endorse or promote products derived from this software without
  63  * specific prior written permission.
  64  *
  65  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  66  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  67  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  68  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  69  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  70  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  71  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  72  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  73  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  74  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  75  * THE POSSIBILITY OF SUCH DAMAGE.
  76  */
  77
  78 /* Portions of this work are licensed under the terms of the GNU GPL,
  79  * version 2 or later. See the COPYING file in the top-level directory.
  80  */
  81
  82 /*
  83  * Define whether architecture deviates from IEEE in not supporting
  84  * signaling NaNs (so all NaNs are treated as quiet).
  85  */
  86 static inline bool no_signaling_nans(float_status *status)
  87 {
  88 #if defined(TARGET_XTENSA)
  89     return status->no_signaling_nans;
  90 #else
  91     return false;
  92 #endif
  93 }
  94
  95 /* Define how the architecture discriminates signaling NaNs.
  96  * This done with the most significant bit of the fraction.
  97  * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008
  98  * the msb must be zero.  MIPS is (so far) unique in supporting both the
  99  * 2008 revision and backward compatibility with their original choice.
 100  * Thus for MIPS we must make the choice at runtime.
 101  */
 102 static inline bool snan_bit_is_one(float_status *status)
 103 {
 104 #if defined(TARGET_MIPS)
 105     return status->snan_bit_is_one;
 106 #elif defined(TARGET_HPPA) || defined(TARGET_UNICORE32) || defined(TARGET_SH4)
 107     return 1;
 108 #else
 109     return 0;
 110 #endif
 111 }
 112
 113 /*----------------------------------------------------------------------------
 114 | For the deconstructed floating-point with fraction FRAC, return true
 115 | if the fraction represents a signalling NaN; otherwise false.
 116 *----------------------------------------------------------------------------*/
 117
 118 static bool parts_is_snan_frac(uint64_t frac, float_status *status)
 119 {
 120     if (no_signaling_nans(status)) {
 121         return false;
 122     } else {
 123         bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);
 124         return msb == snan_bit_is_one(status);
 125     }
 126 }
 127
 128 /*----------------------------------------------------------------------------
 129 | The pattern for a default generated deconstructed floating-point NaN.
 130 *----------------------------------------------------------------------------*/
 131
 132 static FloatParts parts_default_nan(float_status *status)
 133 {
 134     bool sign = 0;
 135     uint64_t frac;
 136
 137 #if defined(TARGET_SPARC) || defined(TARGET_M68K)
 138     /* !snan_bit_is_one, set all bits */
 139     frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
 140 #elif defined(TARGET_I386) || defined(TARGET_X86_64) \
 141     || defined(TARGET_MICROBLAZE)
 142     /* !snan_bit_is_one, set sign and msb */
 143     frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
 144     sign = 1;
 145 #elif defined(TARGET_HPPA)
 146     /* snan_bit_is_one, set msb-1.  */
 147     frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
 148 #elif defined(TARGET_HEXAGON)
 149     sign = 1;
 150     frac = ~0ULL;
 151 #else
 152     /* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
 153      * S390, SH4, TriCore, and Xtensa.  I cannot find documentation
 154      * for Unicore32; the choice from the original commit is unchanged.
 155      * Our other supported targets, CRIS, LM32, Moxie, Nios2, and Tile,
 156      * do not have floating-point.
 157      */
 158     if (snan_bit_is_one(status)) {
 159         /* set all bits other than msb */
 160         frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
 161     } else {
 162         /* set msb */
 163         frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
 164     }
 165 #endif
 166
 167     return (FloatParts) {
 168         .cls = float_class_qnan,
 169         .sign = sign,
 170         .exp = INT_MAX,
 171         .frac = frac
 172     };
 173 }
 174
 175 /*----------------------------------------------------------------------------
 176 | Returns a quiet NaN from a signalling NaN for the deconstructed
 177 | floating-point parts.
 178 *----------------------------------------------------------------------------*/
 179
 180 static FloatParts parts_silence_nan(FloatParts a, float_status *status)
 181 {
 182     g_assert(!no_signaling_nans(status));
 183 #if defined(TARGET_HPPA)
 184     a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1));
 185     a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2);
 186 #else
 187     if (snan_bit_is_one(status)) {
 188         return parts_default_nan(status);
 189     } else {
 190         a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1);
 191     }
 192 #endif
 193     a.cls = float_class_qnan;
 194     return a;
 195 }
 196
 197 /*----------------------------------------------------------------------------
 198 | The pattern for a default generated extended double-precision NaN.
 199 *----------------------------------------------------------------------------*/
 200 floatx80 floatx80_default_nan(float_status *status)
 201 {
 202     floatx80 r;
 203
 204     /* None of the targets that have snan_bit_is_one use floatx80.  */
 205     assert(!snan_bit_is_one(status));
 206 #if defined(TARGET_M68K)
 207     r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
 208     r.high = 0x7FFF;
 209 #else
 210     /* X86 */
 211     r.low = UINT64_C(0xC000000000000000);
 212     r.high = 0xFFFF;
 213 #endif
 214     return r;
 215 }
 216
 217 /*----------------------------------------------------------------------------
 218 | The pattern for a default generated extended double-precision inf.
 219 *----------------------------------------------------------------------------*/
 220
 221 #define floatx80_infinity_high 0x7FFF
 222 #if defined(TARGET_M68K)
 223 #define floatx80_infinity_low  UINT64_C(0x0000000000000000)
 224 #else
 225 #define floatx80_infinity_low  UINT64_C(0x8000000000000000)
 226 #endif
 227
 228 const floatx80 floatx80_infinity
 229     = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low);
 230
 231 /*----------------------------------------------------------------------------
 232 | Raises the exceptions specified by `flags'.  Floating-point traps can be
 233 | defined here if desired.  It is currently not possible for such a trap
 234 | to substitute a result value.  If traps are not implemented, this routine
 235 | should be simply `float_exception_flags |= flags;'.
 236 *----------------------------------------------------------------------------*/
 237
 238 void float_raise(uint8_t flags, float_status *status)
 239 {
 240     status->float_exception_flags |= flags;
 241 }
 242
 243 /*----------------------------------------------------------------------------
 244 | Internal canonical NaN format.
 245 *----------------------------------------------------------------------------*/
 246 typedef struct {
 247     bool sign;
 248     uint64_t high, low;
 249 } commonNaNT;
 250
 251 /*----------------------------------------------------------------------------
 252 | Returns 1 if the half-precision floating-point value `a' is a quiet
 253 | NaN; otherwise returns 0.
 254 *----------------------------------------------------------------------------*/
 255
 256 bool float16_is_quiet_nan(float16 a_, float_status *status)
 257 {
 258     if (no_signaling_nans(status)) {
 259         return float16_is_any_nan(a_);
 260     } else {
 261         uint16_t a = float16_val(a_);
 262         if (snan_bit_is_one(status)) {
 263             return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
 264         } else {
 265
 266             return ((a >> 9) & 0x3F) == 0x3F;
 267         }
 268     }
 269 }
 270
 271 /*----------------------------------------------------------------------------
 272 | Returns 1 if the bfloat16 value `a' is a quiet
 273 | NaN; otherwise returns 0.
 274 *----------------------------------------------------------------------------*/
 275
 276 bool bfloat16_is_quiet_nan(bfloat16 a_, float_status *status)
 277 {
 278     if (no_signaling_nans(status)) {
 279         return bfloat16_is_any_nan(a_);
 280     } else {
 281         uint16_t a = a_;
 282         if (snan_bit_is_one(status)) {
 283             return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F);
 284         } else {
 285             return ((a >> 6) & 0x1FF) == 0x1FF;
 286         }
 287     }
 288 }
 289
 290 /*----------------------------------------------------------------------------
 291 | Returns 1 if the half-precision floating-point value `a' is a signaling
 292 | NaN; otherwise returns 0.
 293 *----------------------------------------------------------------------------*/
 294
 295 bool float16_is_signaling_nan(float16 a_, float_status *status)
 296 {
 297     if (no_signaling_nans(status)) {
 298         return 0;
 299     } else {
 300         uint16_t a = float16_val(a_);
 301         if (snan_bit_is_one(status)) {
 302             return ((a >> 9) & 0x3F) == 0x3F;
 303         } else {
 304             return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
 305         }
 306     }
 307 }
 308
 309 /*----------------------------------------------------------------------------
 310 | Returns 1 if the bfloat16 value `a' is a signaling
 311 | NaN; otherwise returns 0.
 312 *----------------------------------------------------------------------------*/
 313
 314 bool bfloat16_is_signaling_nan(bfloat16 a_, float_status *status)
 315 {
 316     if (no_signaling_nans(status)) {
 317         return 0;
 318     } else {
 319         uint16_t a = a_;
 320         if (snan_bit_is_one(status)) {
 321             return ((a >> 6) & 0x1FF) == 0x1FF;
 322         } else {
 323             return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F);
 324         }
 325     }
 326 }
 327
 328 /*----------------------------------------------------------------------------
 329 | Returns 1 if the single-precision floating-point value `a' is a quiet
 330 | NaN; otherwise returns 0.
 331 *----------------------------------------------------------------------------*/
 332
 333 bool float32_is_quiet_nan(float32 a_, float_status *status)
 334 {
 335     if (no_signaling_nans(status)) {
 336         return float32_is_any_nan(a_);
 337     } else {
 338         uint32_t a = float32_val(a_);
 339         if (snan_bit_is_one(status)) {
 340             return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
 341         } else {
 342             return ((uint32_t)(a << 1) >= 0xFF800000);
 343         }
 344     }
 345 }
 346
 347 /*----------------------------------------------------------------------------
 348 | Returns 1 if the single-precision floating-point value `a' is a signaling
 349 | NaN; otherwise returns 0.
 350 *----------------------------------------------------------------------------*/
 351
 352 bool float32_is_signaling_nan(float32 a_, float_status *status)
 353 {
 354     if (no_signaling_nans(status)) {
 355         return 0;
 356     } else {
 357         uint32_t a = float32_val(a_);
 358         if (snan_bit_is_one(status)) {
 359             return ((uint32_t)(a << 1) >= 0xFF800000);
 360         } else {
 361             return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
 362         }
 363     }
 364 }
 365
 366 /*----------------------------------------------------------------------------
 367 | Returns the result of converting the single-precision floating-point NaN
 368 | `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
 369 | exception is raised.
 370 *----------------------------------------------------------------------------*/
 371
 372 static commonNaNT float32ToCommonNaN(float32 a, float_status *status)
 373 {
 374     commonNaNT z;
 375
 376     if (float32_is_signaling_nan(a, status)) {
 377         float_raise(float_flag_invalid, status);
 378     }
 379     z.sign = float32_val(a) >> 31;
 380     z.low = 0;
 381     z.high = ((uint64_t)float32_val(a)) << 41;
 382     return z;
 383 }
 384
 385 /*----------------------------------------------------------------------------
 386 | Returns the result of converting the canonical NaN `a' to the single-
 387 | precision floating-point format.
 388 *----------------------------------------------------------------------------*/
 389
 390 static float32 commonNaNToFloat32(commonNaNT a, float_status *status)
 391 {
 392     uint32_t mantissa = a.high >> 41;
 393
 394     if (status->default_nan_mode) {
 395         return float32_default_nan(status);
 396     }
 397
 398     if (mantissa) {
 399         return make_float32(
 400             (((uint32_t)a.sign) << 31) | 0x7F800000 | (a.high >> 41));
 401     } else {
 402         return float32_default_nan(status);
 403     }
 404 }
 405
 406 /*----------------------------------------------------------------------------
 407 | Select which NaN to propagate for a two-input operation.
 408 | IEEE754 doesn't specify all the details of this, so the
 409 | algorithm is target-specific.
 410 | The routine is passed various bits of information about the
 411 | two NaNs and should return 0 to select NaN a and 1 for NaN b.
 412 | Note that signalling NaNs are always squashed to quiet NaNs
 413 | by the caller, by calling floatXX_silence_nan() before
 414 | returning them.
 415 |
 416 | aIsLargerSignificand is only valid if both a and b are NaNs
 417 | of some kind, and is true if a has the larger significand,
 418 | or if both a and b have the same significand but a is
 419 | positive but b is negative. It is only needed for the x87
 420 | tie-break rule.
 421 *----------------------------------------------------------------------------*/
 422
 423 static int pickNaN(FloatClass a_cls, FloatClass b_cls,
 424                    bool aIsLargerSignificand, float_status *status)
 425 {
 426 #if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA)
 427     /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take
 428      * the first of:
 429      *  1. A if it is signaling
 430      *  2. B if it is signaling
 431      *  3. A (quiet)
 432      *  4. B (quiet)
 433      * A signaling NaN is always quietened before returning it.
 434      */
 435     /* According to MIPS specifications, if one of the two operands is
 436      * a sNaN, a new qNaN has to be generated. This is done in
 437      * floatXX_silence_nan(). For qNaN inputs the specifications
 438      * says: "When possible, this QNaN result is one of the operand QNaN
 439      * values." In practice it seems that most implementations choose
 440      * the first operand if both operands are qNaN. In short this gives
 441      * the following rules:
 442      *  1. A if it is signaling
 443      *  2. B if it is signaling
 444      *  3. A (quiet)
 445      *  4. B (quiet)
 446      * A signaling NaN is always silenced before returning it.
 447      */
 448     if (is_snan(a_cls)) {
 449         return 0;
 450     } else if (is_snan(b_cls)) {
 451         return 1;
 452     } else if (is_qnan(a_cls)) {
 453         return 0;
 454     } else {
 455         return 1;
 456     }
 457 #elif defined(TARGET_PPC) || defined(TARGET_M68K)
 458     /* PowerPC propagation rules:
 459      *  1. A if it sNaN or qNaN
 460      *  2. B if it sNaN or qNaN
 461      * A signaling NaN is always silenced before returning it.
 462      */
 463     /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
 464      * 3.4 FLOATING-POINT INSTRUCTION DETAILS
 465      * If either operand, but not both operands, of an operation is a
 466      * nonsignaling NaN, then that NaN is returned as the result. If both
 467      * operands are nonsignaling NaNs, then the destination operand
 468      * nonsignaling NaN is returned as the result.
 469      * If either operand to an operation is a signaling NaN (SNaN), then the
 470      * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit
 471      * is set in the FPCR ENABLE byte, then the exception is taken and the
 472      * destination is not modified. If the SNaN exception enable bit is not
 473      * set, setting the SNaN bit in the operand to a one converts the SNaN to
 474      * a nonsignaling NaN. The operation then continues as described in the
 475      * preceding paragraph for nonsignaling NaNs.
 476      */
 477     if (is_nan(a_cls)) {
 478         return 0;
 479     } else {
 480         return 1;
 481     }
 482 #elif defined(TARGET_XTENSA)
 483     /*
 484      * Xtensa has two NaN propagation modes.
 485      * Which one is active is controlled by float_status::use_first_nan.
 486      */
 487     if (status->use_first_nan) {
 488         if (is_nan(a_cls)) {
 489             return 0;
 490         } else {
 491             return 1;
 492         }
 493     } else {
 494         if (is_nan(b_cls)) {
 495             return 1;
 496         } else {
 497             return 0;
 498         }
 499     }
 500 #else
 501     /* This implements x87 NaN propagation rules:
 502      * SNaN + QNaN => return the QNaN
 503      * two SNaNs => return the one with the larger significand, silenced
 504      * two QNaNs => return the one with the larger significand
 505      * SNaN and a non-NaN => return the SNaN, silenced
 506      * QNaN and a non-NaN => return the QNaN
 507      *
 508      * If we get down to comparing significands and they are the same,
 509      * return the NaN with the positive sign bit (if any).
 510      */
 511     if (is_snan(a_cls)) {
 512         if (is_snan(b_cls)) {
 513             return aIsLargerSignificand ? 0 : 1;
 514         }
 515         return is_qnan(b_cls) ? 1 : 0;
 516     } else if (is_qnan(a_cls)) {
 517         if (is_snan(b_cls) || !is_qnan(b_cls)) {
 518             return 0;
 519         } else {
 520             return aIsLargerSignificand ? 0 : 1;
 521         }
 522     } else {
 523         return 1;
 524     }
 525 #endif
 526 }
 527
 528 /*----------------------------------------------------------------------------
 529 | Select which NaN to propagate for a three-input operation.
 530 | For the moment we assume that no CPU needs the 'larger significand'
 531 | information.
 532 | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
 533 *----------------------------------------------------------------------------*/
 534 static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
 535                          bool infzero, float_status *status)
 536 {
 537 #if defined(TARGET_ARM)
 538     /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
 539      * the default NaN
 540      */
 541     if (infzero && is_qnan(c_cls)) {
 542         float_raise(float_flag_invalid, status);
 543         return 3;
 544     }
 545
 546     /* This looks different from the ARM ARM pseudocode, because the ARM ARM
 547      * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
 548      */
 549     if (is_snan(c_cls)) {
 550         return 2;
 551     } else if (is_snan(a_cls)) {
 552         return 0;
 553     } else if (is_snan(b_cls)) {
 554         return 1;
 555     } else if (is_qnan(c_cls)) {
 556         return 2;
 557     } else if (is_qnan(a_cls)) {
 558         return 0;
 559     } else {
 560         return 1;
 561     }
 562 #elif defined(TARGET_MIPS)
 563     if (snan_bit_is_one(status)) {
 564         /*
 565          * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
 566          * case sets InvalidOp and returns the default NaN
 567          */
 568         if (infzero) {
 569             float_raise(float_flag_invalid, status);
 570             return 3;
 571         }
 572         /* Prefer sNaN over qNaN, in the a, b, c order. */
 573         if (is_snan(a_cls)) {
 574             return 0;
 575         } else if (is_snan(b_cls)) {
 576             return 1;
 577         } else if (is_snan(c_cls)) {
 578             return 2;
 579         } else if (is_qnan(a_cls)) {
 580             return 0;
 581         } else if (is_qnan(b_cls)) {
 582             return 1;
 583         } else {
 584             return 2;
 585         }
 586     } else {
 587         /*
 588          * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
 589          * case sets InvalidOp and returns the input value 'c'
 590          */
 591         if (infzero) {
 592             float_raise(float_flag_invalid, status);
 593             return 2;
 594         }
 595         /* Prefer sNaN over qNaN, in the c, a, b order. */
 596         if (is_snan(c_cls)) {
 597             return 2;
 598         } else if (is_snan(a_cls)) {
 599             return 0;
 600         } else if (is_snan(b_cls)) {
 601             return 1;
 602         } else if (is_qnan(c_cls)) {
 603             return 2;
 604         } else if (is_qnan(a_cls)) {
 605             return 0;
 606         } else {
 607             return 1;
 608         }
 609     }
 610 #elif defined(TARGET_PPC)
 611     /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
 612      * to return an input NaN if we have one (ie c) rather than generating
 613      * a default NaN
 614      */
 615     if (infzero) {
 616         float_raise(float_flag_invalid, status);
 617         return 2;
 618     }
 619
 620     /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
 621      * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
 622      */
 623     if (is_nan(a_cls)) {
 624         return 0;
 625     } else if (is_nan(c_cls)) {
 626         return 2;
 627     } else {
 628         return 1;
 629     }
 630 #elif defined(TARGET_RISCV)
 631     /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
 632     if (infzero) {
 633         float_raise(float_flag_invalid, status);
 634     }
 635     return 3; /* default NaN */
 636 #elif defined(TARGET_XTENSA)
 637     /*
 638      * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
 639      * an input NaN if we have one (ie c).
 640      */
 641     if (infzero) {
 642         float_raise(float_flag_invalid, status);
 643         return 2;
 644     }
 645     if (status->use_first_nan) {
 646         if (is_nan(a_cls)) {
 647             return 0;
 648         } else if (is_nan(b_cls)) {
 649             return 1;
 650         } else {
 651             return 2;
 652         }
 653     } else {
 654         if (is_nan(c_cls)) {
 655             return 2;
 656         } else if (is_nan(b_cls)) {
 657             return 1;
 658         } else {
 659             return 0;
 660         }
 661     }
 662 #else
 663     /* A default implementation: prefer a to b to c.
 664      * This is unlikely to actually match any real implementation.
 665      */
 666     if (is_nan(a_cls)) {
 667         return 0;
 668     } else if (is_nan(b_cls)) {
 669         return 1;
 670     } else {
 671         return 2;
 672     }
 673 #endif
 674 }
 675
 676 /*----------------------------------------------------------------------------
 677 | Takes two single-precision floating-point values `a' and `b', one of which
 678 | is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a
 679 | signaling NaN, the invalid exception is raised.
 680 *----------------------------------------------------------------------------*/
 681
 682 static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status)
 683 {
 684     bool aIsLargerSignificand;
 685     uint32_t av, bv;
 686     FloatClass a_cls, b_cls;
 687
 688     /* This is not complete, but is good enough for pickNaN.  */
 689     a_cls = (!float32_is_any_nan(a)
 690              ? float_class_normal
 691              : float32_is_signaling_nan(a, status)
 692              ? float_class_snan
 693              : float_class_qnan);
 694     b_cls = (!float32_is_any_nan(b)
 695              ? float_class_normal
 696              : float32_is_signaling_nan(b, status)
 697              ? float_class_snan
 698              : float_class_qnan);
 699
 700     av = float32_val(a);
 701     bv = float32_val(b);
 702
 703     if (is_snan(a_cls) || is_snan(b_cls)) {
 704         float_raise(float_flag_invalid, status);
 705     }
 706
 707     if (status->default_nan_mode) {
 708         return float32_default_nan(status);
 709     }
 710
 711     if ((uint32_t)(av << 1) < (uint32_t)(bv << 1)) {
 712         aIsLargerSignificand = 0;
 713     } else if ((uint32_t)(bv << 1) < (uint32_t)(av << 1)) {
 714         aIsLargerSignificand = 1;
 715     } else {
 716         aIsLargerSignificand = (av < bv) ? 1 : 0;
 717     }
 718
 719     if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
 720         if (is_snan(b_cls)) {
 721             return float32_silence_nan(b, status);
 722         }
 723         return b;
 724     } else {
 725         if (is_snan(a_cls)) {
 726             return float32_silence_nan(a, status);
 727         }
 728         return a;
 729     }
 730 }
 731
 732 /*----------------------------------------------------------------------------
 733 | Returns 1 if the double-precision floating-point value `a' is a quiet
 734 | NaN; otherwise returns 0.
 735 *----------------------------------------------------------------------------*/
 736
 737 bool float64_is_quiet_nan(float64 a_, float_status *status)
 738 {
 739     if (no_signaling_nans(status)) {
 740         return float64_is_any_nan(a_);
 741     } else {
 742         uint64_t a = float64_val(a_);
 743         if (snan_bit_is_one(status)) {
 744             return (((a >> 51) & 0xFFF) == 0xFFE)
 745                 && (a & 0x0007FFFFFFFFFFFFULL);
 746         } else {
 747             return ((a << 1) >= 0xFFF0000000000000ULL);
 748         }
 749     }
 750 }
 751
 752 /*----------------------------------------------------------------------------
 753 | Returns 1 if the double-precision floating-point value `a' is a signaling
 754 | NaN; otherwise returns 0.
 755 *----------------------------------------------------------------------------*/
 756
 757 bool float64_is_signaling_nan(float64 a_, float_status *status)
 758 {
 759     if (no_signaling_nans(status)) {
 760         return 0;
 761     } else {
 762         uint64_t a = float64_val(a_);
 763         if (snan_bit_is_one(status)) {
 764             return ((a << 1) >= 0xFFF0000000000000ULL);
 765         } else {
 766             return (((a >> 51) & 0xFFF) == 0xFFE)
 767                 && (a & UINT64_C(0x0007FFFFFFFFFFFF));
 768         }
 769     }
 770 }
 771
 772 /*----------------------------------------------------------------------------
 773 | Returns the result of converting the double-precision floating-point NaN
 774 | `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
 775 | exception is raised.
 776 *----------------------------------------------------------------------------*/
 777
 778 static commonNaNT float64ToCommonNaN(float64 a, float_status *status)
 779 {
 780     commonNaNT z;
 781
 782     if (float64_is_signaling_nan(a, status)) {
 783         float_raise(float_flag_invalid, status);
 784     }
 785     z.sign = float64_val(a) >> 63;
 786     z.low = 0;
 787     z.high = float64_val(a) << 12;
 788     return z;
 789 }
 790
 791 /*----------------------------------------------------------------------------
 792 | Returns the result of converting the canonical NaN `a' to the double-
 793 | precision floating-point format.
 794 *----------------------------------------------------------------------------*/
 795
 796 static float64 commonNaNToFloat64(commonNaNT a, float_status *status)
 797 {
 798     uint64_t mantissa = a.high >> 12;
 799
 800     if (status->default_nan_mode) {
 801         return float64_default_nan(status);
 802     }
 803
 804     if (mantissa) {
 805         return make_float64(
 806               (((uint64_t) a.sign) << 63)
 807             | UINT64_C(0x7FF0000000000000)
 808             | (a.high >> 12));
 809     } else {
 810         return float64_default_nan(status);
 811     }
 812 }
 813
 814 /*----------------------------------------------------------------------------
 815 | Takes two double-precision floating-point values `a' and `b', one of which
 816 | is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a
 817 | signaling NaN, the invalid exception is raised.
 818 *----------------------------------------------------------------------------*/
 819
 820 static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status)
 821 {
 822     bool aIsLargerSignificand;
 823     uint64_t av, bv;
 824     FloatClass a_cls, b_cls;
 825
 826     /* This is not complete, but is good enough for pickNaN.  */
 827     a_cls = (!float64_is_any_nan(a)
 828              ? float_class_normal
 829              : float64_is_signaling_nan(a, status)
 830              ? float_class_snan
 831              : float_class_qnan);
 832     b_cls = (!float64_is_any_nan(b)
 833              ? float_class_normal
 834              : float64_is_signaling_nan(b, status)
 835              ? float_class_snan
 836              : float_class_qnan);
 837
 838     av = float64_val(a);
 839     bv = float64_val(b);
 840
 841     if (is_snan(a_cls) || is_snan(b_cls)) {
 842         float_raise(float_flag_invalid, status);
 843     }
 844
 845     if (status->default_nan_mode) {
 846         return float64_default_nan(status);
 847     }
 848
 849     if ((uint64_t)(av << 1) < (uint64_t)(bv << 1)) {
 850         aIsLargerSignificand = 0;
 851     } else if ((uint64_t)(bv << 1) < (uint64_t)(av << 1)) {
 852         aIsLargerSignificand = 1;
 853     } else {
 854         aIsLargerSignificand = (av < bv) ? 1 : 0;
 855     }
 856
 857     if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
 858         if (is_snan(b_cls)) {
 859             return float64_silence_nan(b, status);
 860         }
 861         return b;
 862     } else {
 863         if (is_snan(a_cls)) {
 864             return float64_silence_nan(a, status);
 865         }
 866         return a;
 867     }
 868 }
 869
 870 /*----------------------------------------------------------------------------
 871 | Returns 1 if the extended double-precision floating-point value `a' is a
 872 | quiet NaN; otherwise returns 0. This slightly differs from the same
 873 | function for other types as floatx80 has an explicit bit.
 874 *----------------------------------------------------------------------------*/
 875
 876 int floatx80_is_quiet_nan(floatx80 a, float_status *status)
 877 {
 878     if (no_signaling_nans(status)) {
 879         return floatx80_is_any_nan(a);
 880     } else {
 881         if (snan_bit_is_one(status)) {
 882             uint64_t aLow;
 883
 884             aLow = a.low & ~0x4000000000000000ULL;
 885             return ((a.high & 0x7FFF) == 0x7FFF)
 886                 && (aLow << 1)
 887                 && (a.low == aLow);
 888         } else {
 889             return ((a.high & 0x7FFF) == 0x7FFF)
 890                 && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1)));
 891         }
 892     }
 893 }
 894
 895 /*----------------------------------------------------------------------------
 896 | Returns 1 if the extended double-precision floating-point value `a' is a
 897 | signaling NaN; otherwise returns 0. This slightly differs from the same
 898 | function for other types as floatx80 has an explicit bit.
 899 *----------------------------------------------------------------------------*/
 900
 901 int floatx80_is_signaling_nan(floatx80 a, float_status *status)
 902 {
 903     if (no_signaling_nans(status)) {
 904         return 0;
 905     } else {
 906         if (snan_bit_is_one(status)) {
 907             return ((a.high & 0x7FFF) == 0x7FFF)
 908                 && ((a.low << 1) >= 0x8000000000000000ULL);
 909         } else {
 910             uint64_t aLow;
 911
 912             aLow = a.low & ~UINT64_C(0x4000000000000000);
 913             return ((a.high & 0x7FFF) == 0x7FFF)
 914                 && (uint64_t)(aLow << 1)
 915                 && (a.low == aLow);
 916         }
 917     }
 918 }
 919
 920 /*----------------------------------------------------------------------------
 921 | Returns a quiet NaN from a signalling NaN for the extended double-precision
 922 | floating point value `a'.
 923 *----------------------------------------------------------------------------*/
 924
 925 floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
 926 {
 927     /* None of the targets that have snan_bit_is_one use floatx80.  */
 928     assert(!snan_bit_is_one(status));
 929     a.low |= UINT64_C(0xC000000000000000);
 930     return a;
 931 }
 932
 933 /*----------------------------------------------------------------------------
 934 | Returns the result of converting the extended double-precision floating-
 935 | point NaN `a' to the canonical NaN format.  If `a' is a signaling NaN, the
 936 | invalid exception is raised.
 937 *----------------------------------------------------------------------------*/
 938
 939 static commonNaNT floatx80ToCommonNaN(floatx80 a, float_status *status)
 940 {
 941     floatx80 dflt;
 942     commonNaNT z;
 943
 944     if (floatx80_is_signaling_nan(a, status)) {
 945         float_raise(float_flag_invalid, status);
 946     }
 947     if (a.low >> 63) {
 948         z.sign = a.high >> 15;
 949         z.low = 0;
 950         z.high = a.low << 1;
 951     } else {
 952         dflt = floatx80_default_nan(status);
 953         z.sign = dflt.high >> 15;
 954         z.low = 0;
 955         z.high = dflt.low << 1;
 956     }
 957     return z;
 958 }
 959
 960 /*----------------------------------------------------------------------------
 961 | Returns the result of converting the canonical NaN `a' to the extended
 962 | double-precision floating-point format.
 963 *----------------------------------------------------------------------------*/
 964
 965 static floatx80 commonNaNToFloatx80(commonNaNT a, float_status *status)
 966 {
 967     floatx80 z;
 968
 969     if (status->default_nan_mode) {
 970         return floatx80_default_nan(status);
 971     }
 972
 973     if (a.high >> 1) {
 974         z.low = UINT64_C(0x8000000000000000) | a.high >> 1;
 975         z.high = (((uint16_t)a.sign) << 15) | 0x7FFF;
 976     } else {
 977         z = floatx80_default_nan(status);
 978     }
 979     return z;
 980 }
 981
 982 /*----------------------------------------------------------------------------
 983 | Takes two extended double-precision floating-point values `a' and `b', one
 984 | of which is a NaN, and returns the appropriate NaN result.  If either `a' or
 985 | `b' is a signaling NaN, the invalid exception is raised.
 986 *----------------------------------------------------------------------------*/
 987
 988 floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
 989 {
 990     bool aIsLargerSignificand;
 991     FloatClass a_cls, b_cls;
 992
 993     /* This is not complete, but is good enough for pickNaN.  */
 994     a_cls = (!floatx80_is_any_nan(a)
 995              ? float_class_normal
 996              : floatx80_is_signaling_nan(a, status)
 997              ? float_class_snan
 998              : float_class_qnan);
 999     b_cls = (!floatx80_is_any_nan(b)
1000              ? float_class_normal
1001              : floatx80_is_signaling_nan(b, status)
1002              ? float_class_snan
1003              : float_class_qnan);
1004
1005     if (is_snan(a_cls) || is_snan(b_cls)) {
1006         float_raise(float_flag_invalid, status);
1007     }
1008
1009     if (status->default_nan_mode) {
1010         return floatx80_default_nan(status);
1011     }
1012
1013     if (a.low < b.low) {
1014         aIsLargerSignificand = 0;
1015     } else if (b.low < a.low) {
1016         aIsLargerSignificand = 1;
1017     } else {
1018         aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
1019     }
1020
1021     if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
1022         if (is_snan(b_cls)) {
1023             return floatx80_silence_nan(b, status);
1024         }
1025         return b;
1026     } else {
1027         if (is_snan(a_cls)) {
1028             return floatx80_silence_nan(a, status);
1029         }
1030         return a;
1031     }
1032 }
1033
1034 /*----------------------------------------------------------------------------
1035 | Returns 1 if the quadruple-precision floating-point value `a' is a quiet
1036 | NaN; otherwise returns 0.
1037 *----------------------------------------------------------------------------*/
1038
1039 bool float128_is_quiet_nan(float128 a, float_status *status)
1040 {
1041     if (no_signaling_nans(status)) {
1042         return float128_is_any_nan(a);
1043     } else {
1044         if (snan_bit_is_one(status)) {
1045             return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
1046                 && (a.low || (a.high & 0x00007FFFFFFFFFFFULL));
1047         } else {
1048             return ((a.high << 1) >= 0xFFFF000000000000ULL)
1049                 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
1050         }
1051     }
1052 }
1053
1054 /*----------------------------------------------------------------------------
1055 | Returns 1 if the quadruple-precision floating-point value `a' is a
1056 | signaling NaN; otherwise returns 0.
1057 *----------------------------------------------------------------------------*/
1058
1059 bool float128_is_signaling_nan(float128 a, float_status *status)
1060 {
1061     if (no_signaling_nans(status)) {
1062         return 0;
1063     } else {
1064         if (snan_bit_is_one(status)) {
1065             return ((a.high << 1) >= 0xFFFF000000000000ULL)
1066                 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
1067         } else {
1068             return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
1069                 && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF)));
1070         }
1071     }
1072 }
1073
1074 /*----------------------------------------------------------------------------
1075 | Returns a quiet NaN from a signalling NaN for the quadruple-precision
1076 | floating point value `a'.
1077 *----------------------------------------------------------------------------*/
1078
1079 float128 float128_silence_nan(float128 a, float_status *status)
1080 {
1081     if (no_signaling_nans(status)) {
1082         g_assert_not_reached();
1083     } else {
1084         if (snan_bit_is_one(status)) {
1085             return float128_default_nan(status);
1086         } else {
1087             a.high |= UINT64_C(0x0000800000000000);
1088             return a;
1089         }
1090     }
1091 }
1092
1093 /*----------------------------------------------------------------------------
1094 | Returns the result of converting the quadruple-precision floating-point NaN
1095 | `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
1096 | exception is raised.
1097 *----------------------------------------------------------------------------*/
1098
1099 static commonNaNT float128ToCommonNaN(float128 a, float_status *status)
1100 {
1101     commonNaNT z;
1102
1103     if (float128_is_signaling_nan(a, status)) {
1104         float_raise(float_flag_invalid, status);
1105     }
1106     z.sign = a.high >> 63;
1107     shortShift128Left(a.high, a.low, 16, &z.high, &z.low);
1108     return z;
1109 }
1110
1111 /*----------------------------------------------------------------------------
1112 | Returns the result of converting the canonical NaN `a' to the quadruple-
1113 | precision floating-point format.
1114 *----------------------------------------------------------------------------*/
1115
1116 static float128 commonNaNToFloat128(commonNaNT a, float_status *status)
1117 {
1118     float128 z;
1119
1120     if (status->default_nan_mode) {
1121         return float128_default_nan(status);
1122     }
1123
1124     shift128Right(a.high, a.low, 16, &z.high, &z.low);
1125     z.high |= (((uint64_t)a.sign) << 63) | UINT64_C(0x7FFF000000000000);
1126     return z;
1127 }
1128
1129 /*----------------------------------------------------------------------------
1130 | Takes two quadruple-precision floating-point values `a' and `b', one of
1131 | which is a NaN, and returns the appropriate NaN result.  If either `a' or
1132 | `b' is a signaling NaN, the invalid exception is raised.
1133 *----------------------------------------------------------------------------*/
1134
1135 static float128 propagateFloat128NaN(float128 a, float128 b,
1136                                      float_status *status)
1137 {
1138     bool aIsLargerSignificand;
1139     FloatClass a_cls, b_cls;
1140
1141     /* This is not complete, but is good enough for pickNaN.  */
1142     a_cls = (!float128_is_any_nan(a)
1143              ? float_class_normal
1144              : float128_is_signaling_nan(a, status)
1145              ? float_class_snan
1146              : float_class_qnan);
1147     b_cls = (!float128_is_any_nan(b)
1148              ? float_class_normal
1149              : float128_is_signaling_nan(b, status)
1150              ? float_class_snan
1151              : float_class_qnan);
1152
1153     if (is_snan(a_cls) || is_snan(b_cls)) {
1154         float_raise(float_flag_invalid, status);
1155     }
1156
1157     if (status->default_nan_mode) {
1158         return float128_default_nan(status);
1159     }
1160
1161     if (lt128(a.high << 1, a.low, b.high << 1, b.low)) {
1162         aIsLargerSignificand = 0;
1163     } else if (lt128(b.high << 1, b.low, a.high << 1, a.low)) {
1164         aIsLargerSignificand = 1;
1165     } else {
1166         aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
1167     }
1168
1169     if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
1170         if (is_snan(b_cls)) {
1171             return float128_silence_nan(b, status);
1172         }
1173         return b;
1174     } else {
1175         if (is_snan(a_cls)) {
1176             return float128_silence_nan(a, status);
1177         }
1178         return a;
1179     }
1180 }