fpu/softfloat-specialize.h

   1 /*
   2  * QEMU float support
   3  *
   4  * The code in this source file is derived from release 2a of the SoftFloat
   5  * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and
   6  * some later contributions) are provided under that license, as detailed below.
   7  * It has subsequently been modified by contributors to the QEMU Project,
   8  * so some portions are provided under:
   9  *  the SoftFloat-2a license
  10  *  the BSD license
  11  *  GPL-v2-or-later
  12  *
  13  * Any future contributions to this file after December 1st 2014 will be
  14  * taken to be licensed under the Softfloat-2a license unless specifically
  15  * indicated otherwise.
  16  */
  17
  18 /*
  19 ===============================================================================
  20 This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
  21 Arithmetic Package, Release 2a.
  22
  23 Written by John R. Hauser.  This work was made possible in part by the
  24 International Computer Science Institute, located at Suite 600, 1947 Center
  25 Street, Berkeley, California 94704.  Funding was partially provided by the
  26 National Science Foundation under grant MIP-9311980.  The original version
  27 of this code was written as part of a project to build a fixed-point vector
  28 processor in collaboration with the University of California at Berkeley,
  29 overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
  30 is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
  31 arithmetic/SoftFloat.html'.
  32
  33 THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort
  34 has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
  35 TIMES RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO
  36 PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
  37 AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
  38
  39 Derivative works are acceptable, even for commercial purposes, so long as
  40 (1) they include prominent notice that the work is derivative, and (2) they
  41 include prominent notice akin to these four paragraphs for those parts of
  42 this code that are retained.
  43
  44 ===============================================================================
  45 */
  46
  47 /* BSD licensing:
  48  * Copyright (c) 2006, Fabrice Bellard
  49  * All rights reserved.
  50  *
  51  * Redistribution and use in source and binary forms, with or without
  52  * modification, are permitted provided that the following conditions are met:
  53  *
  54  * 1. Redistributions of source code must retain the above copyright notice,
  55  * this list of conditions and the following disclaimer.
  56  *
  57  * 2. Redistributions in binary form must reproduce the above copyright notice,
  58  * this list of conditions and the following disclaimer in the documentation
  59  * and/or other materials provided with the distribution.
  60  *
  61  * 3. Neither the name of the copyright holder nor the names of its contributors
  62  * may be used to endorse or promote products derived from this software without
  63  * specific prior written permission.
  64  *
  65  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  66  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  67  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  68  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  69  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  70  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  71  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  72  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  73  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  74  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  75  * THE POSSIBILITY OF SUCH DAMAGE.
  76  */
  77
  78 /* Portions of this work are licensed under the terms of the GNU GPL,
  79  * version 2 or later. See the COPYING file in the top-level directory.
  80  */
  81
  82 #if defined(TARGET_XTENSA)
  83 /* Define for architectures which deviate from IEEE in not supporting
  84  * signaling NaNs (so all NaNs are treated as quiet).
  85  */
  86 #define NO_SIGNALING_NANS 1
  87 #endif
  88
  89 /*----------------------------------------------------------------------------
  90 | For the deconstructed floating-point with fraction FRAC, return true
  91 | if the fraction represents a signalling NaN; otherwise false.
  92 *----------------------------------------------------------------------------*/
  93
  94 static bool parts_is_snan_frac(uint64_t frac, float_status *status)
  95 {
  96 #ifdef NO_SIGNALING_NANS
  97     return false;
  98 #else
  99     flag msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);
 100     return msb == status->snan_bit_is_one;
 101 #endif
 102 }
 103
 104 /*----------------------------------------------------------------------------
 105 | The pattern for a default generated deconstructed floating-point NaN.
 106 *----------------------------------------------------------------------------*/
 107
 108 static FloatParts parts_default_nan(float_status *status)
 109 {
 110     bool sign = 0;
 111     uint64_t frac;
 112
 113 #if defined(TARGET_SPARC) || defined(TARGET_M68K)
 114     frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
 115 #elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \
 116       defined(TARGET_S390X) || defined(TARGET_RISCV)
 117     frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
 118 #elif defined(TARGET_HPPA)
 119     frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
 120 #else
 121     if (status->snan_bit_is_one) {
 122         frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
 123     } else {
 124 #if defined(TARGET_MIPS)
 125         frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
 126 #else
 127         frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
 128         sign = 1;
 129 #endif
 130     }
 131 #endif
 132
 133     return (FloatParts) {
 134         .cls = float_class_qnan,
 135         .sign = sign,
 136         .exp = INT_MAX,
 137         .frac = frac
 138     };
 139 }
 140
 141 /*----------------------------------------------------------------------------
 142 | Returns a quiet NaN from a signalling NaN for the deconstructed
 143 | floating-point parts.
 144 *----------------------------------------------------------------------------*/
 145
 146 static FloatParts parts_silence_nan(FloatParts a, float_status *status)
 147 {
 148 #ifdef NO_SIGNALING_NANS
 149     g_assert_not_reached();
 150 #elif defined(TARGET_HPPA)
 151     a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1));
 152     a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2);
 153 #else
 154     if (status->snan_bit_is_one) {
 155         return parts_default_nan(status);
 156     } else {
 157         a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1);
 158     }
 159 #endif
 160     a.cls = float_class_qnan;
 161     return a;
 162 }
 163
 164 /*----------------------------------------------------------------------------
 165 | The pattern for a default generated half-precision NaN.
 166 *----------------------------------------------------------------------------*/
 167 float16 float16_default_nan(float_status *status)
 168 {
 169 #if defined(TARGET_ARM)
 170     return const_float16(0x7E00);
 171 #else
 172     if (status->snan_bit_is_one) {
 173         return const_float16(0x7DFF);
 174     } else {
 175 #if defined(TARGET_MIPS)
 176         return const_float16(0x7E00);
 177 #else
 178         return const_float16(0xFE00);
 179 #endif
 180     }
 181 #endif
 182 }
 183
 184 /*----------------------------------------------------------------------------
 185 | The pattern for a default generated single-precision NaN.
 186 *----------------------------------------------------------------------------*/
 187 float32 float32_default_nan(float_status *status)
 188 {
 189 #if defined(TARGET_SPARC) || defined(TARGET_M68K)
 190     return const_float32(0x7FFFFFFF);
 191 #elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \
 192       defined(TARGET_XTENSA) || defined(TARGET_S390X) || \
 193       defined(TARGET_TRICORE) || defined(TARGET_RISCV)
 194     return const_float32(0x7FC00000);
 195 #elif defined(TARGET_HPPA)
 196     return const_float32(0x7FA00000);
 197 #else
 198     if (status->snan_bit_is_one) {
 199         return const_float32(0x7FBFFFFF);
 200     } else {
 201 #if defined(TARGET_MIPS)
 202         return const_float32(0x7FC00000);
 203 #else
 204         return const_float32(0xFFC00000);
 205 #endif
 206     }
 207 #endif
 208 }
 209
 210 /*----------------------------------------------------------------------------
 211 | The pattern for a default generated double-precision NaN.
 212 *----------------------------------------------------------------------------*/
 213 float64 float64_default_nan(float_status *status)
 214 {
 215 #if defined(TARGET_SPARC) || defined(TARGET_M68K)
 216     return const_float64(LIT64(0x7FFFFFFFFFFFFFFF));
 217 #elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \
 218       defined(TARGET_S390X) || defined(TARGET_RISCV)
 219     return const_float64(LIT64(0x7FF8000000000000));
 220 #elif defined(TARGET_HPPA)
 221     return const_float64(LIT64(0x7FF4000000000000));
 222 #else
 223     if (status->snan_bit_is_one) {
 224         return const_float64(LIT64(0x7FF7FFFFFFFFFFFF));
 225     } else {
 226 #if defined(TARGET_MIPS)
 227         return const_float64(LIT64(0x7FF8000000000000));
 228 #else
 229         return const_float64(LIT64(0xFFF8000000000000));
 230 #endif
 231     }
 232 #endif
 233 }
 234
 235 /*----------------------------------------------------------------------------
 236 | The pattern for a default generated extended double-precision NaN.
 237 *----------------------------------------------------------------------------*/
 238 floatx80 floatx80_default_nan(float_status *status)
 239 {
 240     floatx80 r;
 241 #if defined(TARGET_M68K)
 242     r.low = LIT64(0xFFFFFFFFFFFFFFFF);
 243     r.high = 0x7FFF;
 244 #else
 245     if (status->snan_bit_is_one) {
 246         r.low = LIT64(0xBFFFFFFFFFFFFFFF);
 247         r.high = 0x7FFF;
 248     } else {
 249         r.low = LIT64(0xC000000000000000);
 250         r.high = 0xFFFF;
 251     }
 252 #endif
 253     return r;
 254 }
 255
 256 /*----------------------------------------------------------------------------
 257 | The pattern for a default generated extended double-precision inf.
 258 *----------------------------------------------------------------------------*/
 259
 260 #define floatx80_infinity_high 0x7FFF
 261 #if defined(TARGET_M68K)
 262 #define floatx80_infinity_low  LIT64(0x0000000000000000)
 263 #else
 264 #define floatx80_infinity_low  LIT64(0x8000000000000000)
 265 #endif
 266
 267 const floatx80 floatx80_infinity
 268     = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low);
 269
 270 /*----------------------------------------------------------------------------
 271 | The pattern for a default generated quadruple-precision NaN.
 272 *----------------------------------------------------------------------------*/
 273 float128 float128_default_nan(float_status *status)
 274 {
 275     float128 r;
 276
 277     if (status->snan_bit_is_one) {
 278         r.low = LIT64(0xFFFFFFFFFFFFFFFF);
 279         r.high = LIT64(0x7FFF7FFFFFFFFFFF);
 280     } else {
 281         r.low = LIT64(0x0000000000000000);
 282 #if defined(TARGET_S390X) || defined(TARGET_PPC) || defined(TARGET_RISCV)
 283         r.high = LIT64(0x7FFF800000000000);
 284 #else
 285         r.high = LIT64(0xFFFF800000000000);
 286 #endif
 287     }
 288     return r;
 289 }
 290
 291 /*----------------------------------------------------------------------------
 292 | Raises the exceptions specified by `flags'.  Floating-point traps can be
 293 | defined here if desired.  It is currently not possible for such a trap
 294 | to substitute a result value.  If traps are not implemented, this routine
 295 | should be simply `float_exception_flags |= flags;'.
 296 *----------------------------------------------------------------------------*/
 297
 298 void float_raise(uint8_t flags, float_status *status)
 299 {
 300     status->float_exception_flags |= flags;
 301 }
 302
 303 /*----------------------------------------------------------------------------
 304 | Internal canonical NaN format.
 305 *----------------------------------------------------------------------------*/
 306 typedef struct {
 307     flag sign;
 308     uint64_t high, low;
 309 } commonNaNT;
 310
 311 /*----------------------------------------------------------------------------
 312 | Returns 1 if the half-precision floating-point value `a' is a quiet
 313 | NaN; otherwise returns 0.
 314 *----------------------------------------------------------------------------*/
 315
 316 int float16_is_quiet_nan(float16 a_, float_status *status)
 317 {
 318 #ifdef NO_SIGNALING_NANS
 319     return float16_is_any_nan(a_);
 320 #else
 321     uint16_t a = float16_val(a_);
 322     if (status->snan_bit_is_one) {
 323         return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
 324     } else {
 325         return ((a & ~0x8000) >= 0x7C80);
 326     }
 327 #endif
 328 }
 329
 330 /*----------------------------------------------------------------------------
 331 | Returns 1 if the half-precision floating-point value `a' is a signaling
 332 | NaN; otherwise returns 0.
 333 *----------------------------------------------------------------------------*/
 334
 335 int float16_is_signaling_nan(float16 a_, float_status *status)
 336 {
 337 #ifdef NO_SIGNALING_NANS
 338     return 0;
 339 #else
 340     uint16_t a = float16_val(a_);
 341     if (status->snan_bit_is_one) {
 342         return ((a & ~0x8000) >= 0x7C80);
 343     } else {
 344         return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
 345     }
 346 #endif
 347 }
 348
 349 /*----------------------------------------------------------------------------
 350 | Returns a quiet NaN from a signalling NaN for the half-precision
 351 | floating point value `a'.
 352 *----------------------------------------------------------------------------*/
 353
 354 float16 float16_silence_nan(float16 a, float_status *status)
 355 {
 356 #ifdef NO_SIGNALING_NANS
 357     g_assert_not_reached();
 358 #else
 359     if (status->snan_bit_is_one) {
 360         return float16_default_nan(status);
 361     } else {
 362         return a | (1 << 9);
 363     }
 364 #endif
 365 }
 366
 367 /*----------------------------------------------------------------------------
 368 | Returns a quiet NaN if the half-precision floating point value `a' is a
 369 | signaling NaN; otherwise returns `a'.
 370 *----------------------------------------------------------------------------*/
 371
 372 float16 float16_maybe_silence_nan(float16 a, float_status *status)
 373 {
 374     if (float16_is_signaling_nan(a, status)) {
 375         return float16_silence_nan(a, status);
 376     }
 377     return a;
 378 }
 379
 380 /*----------------------------------------------------------------------------
 381 | Returns 1 if the single-precision floating-point value `a' is a quiet
 382 | NaN; otherwise returns 0.
 383 *----------------------------------------------------------------------------*/
 384
 385 int float32_is_quiet_nan(float32 a_, float_status *status)
 386 {
 387 #ifdef NO_SIGNALING_NANS
 388     return float32_is_any_nan(a_);
 389 #else
 390     uint32_t a = float32_val(a_);
 391     if (status->snan_bit_is_one) {
 392         return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
 393     } else {
 394         return ((uint32_t)(a << 1) >= 0xFF800000);
 395     }
 396 #endif
 397 }
 398
 399 /*----------------------------------------------------------------------------
 400 | Returns 1 if the single-precision floating-point value `a' is a signaling
 401 | NaN; otherwise returns 0.
 402 *----------------------------------------------------------------------------*/
 403
 404 int float32_is_signaling_nan(float32 a_, float_status *status)
 405 {
 406 #ifdef NO_SIGNALING_NANS
 407     return 0;
 408 #else
 409     uint32_t a = float32_val(a_);
 410     if (status->snan_bit_is_one) {
 411         return ((uint32_t)(a << 1) >= 0xFF800000);
 412     } else {
 413         return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
 414     }
 415 #endif
 416 }
 417
 418 /*----------------------------------------------------------------------------
 419 | Returns a quiet NaN from a signalling NaN for the single-precision
 420 | floating point value `a'.
 421 *----------------------------------------------------------------------------*/
 422
 423 float32 float32_silence_nan(float32 a, float_status *status)
 424 {
 425 #ifdef NO_SIGNALING_NANS
 426     g_assert_not_reached();
 427 #else
 428     if (status->snan_bit_is_one) {
 429 # ifdef TARGET_HPPA
 430         a &= ~0x00400000;
 431         a |=  0x00200000;
 432         return a;
 433 # else
 434         return float32_default_nan(status);
 435 # endif
 436     } else {
 437         return a | (1 << 22);
 438     }
 439 #endif
 440 }
 441 /*----------------------------------------------------------------------------
 442 | Returns a quiet NaN if the single-precision floating point value `a' is a
 443 | signaling NaN; otherwise returns `a'.
 444 *----------------------------------------------------------------------------*/
 445
 446 float32 float32_maybe_silence_nan(float32 a, float_status *status)
 447 {
 448     if (float32_is_signaling_nan(a, status)) {
 449         return float32_silence_nan(a, status);
 450     }
 451     return a;
 452 }
 453
 454 /*----------------------------------------------------------------------------
 455 | Returns the result of converting the single-precision floating-point NaN
 456 | `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
 457 | exception is raised.
 458 *----------------------------------------------------------------------------*/
 459
 460 static commonNaNT float32ToCommonNaN(float32 a, float_status *status)
 461 {
 462     commonNaNT z;
 463
 464     if (float32_is_signaling_nan(a, status)) {
 465         float_raise(float_flag_invalid, status);
 466     }
 467     z.sign = float32_val(a) >> 31;
 468     z.low = 0;
 469     z.high = ((uint64_t)float32_val(a)) << 41;
 470     return z;
 471 }
 472
 473 /*----------------------------------------------------------------------------
 474 | Returns the result of converting the canonical NaN `a' to the single-
 475 | precision floating-point format.
 476 *----------------------------------------------------------------------------*/
 477
 478 static float32 commonNaNToFloat32(commonNaNT a, float_status *status)
 479 {
 480     uint32_t mantissa = a.high >> 41;
 481
 482     if (status->default_nan_mode) {
 483         return float32_default_nan(status);
 484     }
 485
 486     if (mantissa) {
 487         return make_float32(
 488             (((uint32_t)a.sign) << 31) | 0x7F800000 | (a.high >> 41));
 489     } else {
 490         return float32_default_nan(status);
 491     }
 492 }
 493
 494 /*----------------------------------------------------------------------------
 495 | Select which NaN to propagate for a two-input operation.
 496 | IEEE754 doesn't specify all the details of this, so the
 497 | algorithm is target-specific.
 498 | The routine is passed various bits of information about the
 499 | two NaNs and should return 0 to select NaN a and 1 for NaN b.
 500 | Note that signalling NaNs are always squashed to quiet NaNs
 501 | by the caller, by calling floatXX_maybe_silence_nan() before
 502 | returning them.
 503 |
 504 | aIsLargerSignificand is only valid if both a and b are NaNs
 505 | of some kind, and is true if a has the larger significand,
 506 | or if both a and b have the same significand but a is
 507 | positive but b is negative. It is only needed for the x87
 508 | tie-break rule.
 509 *----------------------------------------------------------------------------*/
 510
 511 #if defined(TARGET_ARM)
 512 static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 513                    flag aIsLargerSignificand)
 514 {
 515     /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take
 516      * the first of:
 517      *  1. A if it is signaling
 518      *  2. B if it is signaling
 519      *  3. A (quiet)
 520      *  4. B (quiet)
 521      * A signaling NaN is always quietened before returning it.
 522      */
 523     if (aIsSNaN) {
 524         return 0;
 525     } else if (bIsSNaN) {
 526         return 1;
 527     } else if (aIsQNaN) {
 528         return 0;
 529     } else {
 530         return 1;
 531     }
 532 }
 533 #elif defined(TARGET_MIPS) || defined(TARGET_HPPA)
 534 static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 535                     flag aIsLargerSignificand)
 536 {
 537     /* According to MIPS specifications, if one of the two operands is
 538      * a sNaN, a new qNaN has to be generated. This is done in
 539      * floatXX_maybe_silence_nan(). For qNaN inputs the specifications
 540      * says: "When possible, this QNaN result is one of the operand QNaN
 541      * values." In practice it seems that most implementations choose
 542      * the first operand if both operands are qNaN. In short this gives
 543      * the following rules:
 544      *  1. A if it is signaling
 545      *  2. B if it is signaling
 546      *  3. A (quiet)
 547      *  4. B (quiet)
 548      * A signaling NaN is always silenced before returning it.
 549      */
 550     if (aIsSNaN) {
 551         return 0;
 552     } else if (bIsSNaN) {
 553         return 1;
 554     } else if (aIsQNaN) {
 555         return 0;
 556     } else {
 557         return 1;
 558     }
 559 }
 560 #elif defined(TARGET_PPC) || defined(TARGET_XTENSA)
 561 static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 562                    flag aIsLargerSignificand)
 563 {
 564     /* PowerPC propagation rules:
 565      *  1. A if it sNaN or qNaN
 566      *  2. B if it sNaN or qNaN
 567      * A signaling NaN is always silenced before returning it.
 568      */
 569     if (aIsSNaN || aIsQNaN) {
 570         return 0;
 571     } else {
 572         return 1;
 573     }
 574 }
 575 #elif defined(TARGET_M68K)
 576 static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 577                    flag aIsLargerSignificand)
 578 {
 579     /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
 580      * 3.4 FLOATING-POINT INSTRUCTION DETAILS
 581      * If either operand, but not both operands, of an operation is a
 582      * nonsignaling NaN, then that NaN is returned as the result. If both
 583      * operands are nonsignaling NaNs, then the destination operand
 584      * nonsignaling NaN is returned as the result.
 585      * If either operand to an operation is a signaling NaN (SNaN), then the
 586      * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit
 587      * is set in the FPCR ENABLE byte, then the exception is taken and the
 588      * destination is not modified. If the SNaN exception enable bit is not
 589      * set, setting the SNaN bit in the operand to a one converts the SNaN to
 590      * a nonsignaling NaN. The operation then continues as described in the
 591      * preceding paragraph for nonsignaling NaNs.
 592      */
 593     if (aIsQNaN || aIsSNaN) { /* a is the destination operand */
 594         return 0; /* return the destination operand */
 595     } else {
 596         return 1; /* return b */
 597     }
 598 }
 599 #else
 600 static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 601                     flag aIsLargerSignificand)
 602 {
 603     /* This implements x87 NaN propagation rules:
 604      * SNaN + QNaN => return the QNaN
 605      * two SNaNs => return the one with the larger significand, silenced
 606      * two QNaNs => return the one with the larger significand
 607      * SNaN and a non-NaN => return the SNaN, silenced
 608      * QNaN and a non-NaN => return the QNaN
 609      *
 610      * If we get down to comparing significands and they are the same,
 611      * return the NaN with the positive sign bit (if any).
 612      */
 613     if (aIsSNaN) {
 614         if (bIsSNaN) {
 615             return aIsLargerSignificand ? 0 : 1;
 616         }
 617         return bIsQNaN ? 1 : 0;
 618     } else if (aIsQNaN) {
 619         if (bIsSNaN || !bIsQNaN) {
 620             return 0;
 621         } else {
 622             return aIsLargerSignificand ? 0 : 1;
 623         }
 624     } else {
 625         return 1;
 626     }
 627 }
 628 #endif
 629
 630 /*----------------------------------------------------------------------------
 631 | Select which NaN to propagate for a three-input operation.
 632 | For the moment we assume that no CPU needs the 'larger significand'
 633 | information.
 634 | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
 635 *----------------------------------------------------------------------------*/
 636 #if defined(TARGET_ARM)
 637 static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 638                          flag cIsQNaN, flag cIsSNaN, flag infzero,
 639                          float_status *status)
 640 {
 641     /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
 642      * the default NaN
 643      */
 644     if (infzero && cIsQNaN) {
 645         float_raise(float_flag_invalid, status);
 646         return 3;
 647     }
 648
 649     /* This looks different from the ARM ARM pseudocode, because the ARM ARM
 650      * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
 651      */
 652     if (cIsSNaN) {
 653         return 2;
 654     } else if (aIsSNaN) {
 655         return 0;
 656     } else if (bIsSNaN) {
 657         return 1;
 658     } else if (cIsQNaN) {
 659         return 2;
 660     } else if (aIsQNaN) {
 661         return 0;
 662     } else {
 663         return 1;
 664     }
 665 }
 666 #elif defined(TARGET_MIPS)
 667 static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 668                          flag cIsQNaN, flag cIsSNaN, flag infzero,
 669                          float_status *status)
 670 {
 671     /* For MIPS, the (inf,zero,qnan) case sets InvalidOp and returns
 672      * the default NaN
 673      */
 674     if (infzero) {
 675         float_raise(float_flag_invalid, status);
 676         return 3;
 677     }
 678
 679     if (status->snan_bit_is_one) {
 680         /* Prefer sNaN over qNaN, in the a, b, c order. */
 681         if (aIsSNaN) {
 682             return 0;
 683         } else if (bIsSNaN) {
 684             return 1;
 685         } else if (cIsSNaN) {
 686             return 2;
 687         } else if (aIsQNaN) {
 688             return 0;
 689         } else if (bIsQNaN) {
 690             return 1;
 691         } else {
 692             return 2;
 693         }
 694     } else {
 695         /* Prefer sNaN over qNaN, in the c, a, b order. */
 696         if (cIsSNaN) {
 697             return 2;
 698         } else if (aIsSNaN) {
 699             return 0;
 700         } else if (bIsSNaN) {
 701             return 1;
 702         } else if (cIsQNaN) {
 703             return 2;
 704         } else if (aIsQNaN) {
 705             return 0;
 706         } else {
 707             return 1;
 708         }
 709     }
 710 }
 711 #elif defined(TARGET_PPC)
 712 static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 713                          flag cIsQNaN, flag cIsSNaN, flag infzero,
 714                          float_status *status)
 715 {
 716     /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
 717      * to return an input NaN if we have one (ie c) rather than generating
 718      * a default NaN
 719      */
 720     if (infzero) {
 721         float_raise(float_flag_invalid, status);
 722         return 2;
 723     }
 724
 725     /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
 726      * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
 727      */
 728     if (aIsSNaN || aIsQNaN) {
 729         return 0;
 730     } else if (cIsSNaN || cIsQNaN) {
 731         return 2;
 732     } else {
 733         return 1;
 734     }
 735 }
 736 #else
 737 /* A default implementation: prefer a to b to c.
 738  * This is unlikely to actually match any real implementation.
 739  */
 740 static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 741                          flag cIsQNaN, flag cIsSNaN, flag infzero,
 742                          float_status *status)
 743 {
 744     if (aIsSNaN || aIsQNaN) {
 745         return 0;
 746     } else if (bIsSNaN || bIsQNaN) {
 747         return 1;
 748     } else {
 749         return 2;
 750     }
 751 }
 752 #endif
 753
 754 /*----------------------------------------------------------------------------
 755 | Takes two single-precision floating-point values `a' and `b', one of which
 756 | is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a
 757 | signaling NaN, the invalid exception is raised.
 758 *----------------------------------------------------------------------------*/
 759
 760 static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status)
 761 {
 762     flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
 763     flag aIsLargerSignificand;
 764     uint32_t av, bv;
 765
 766     aIsQuietNaN = float32_is_quiet_nan(a, status);
 767     aIsSignalingNaN = float32_is_signaling_nan(a, status);
 768     bIsQuietNaN = float32_is_quiet_nan(b, status);
 769     bIsSignalingNaN = float32_is_signaling_nan(b, status);
 770     av = float32_val(a);
 771     bv = float32_val(b);
 772
 773     if (aIsSignalingNaN | bIsSignalingNaN) {
 774         float_raise(float_flag_invalid, status);
 775     }
 776
 777     if (status->default_nan_mode) {
 778         return float32_default_nan(status);
 779     }
 780
 781     if ((uint32_t)(av << 1) < (uint32_t)(bv << 1)) {
 782         aIsLargerSignificand = 0;
 783     } else if ((uint32_t)(bv << 1) < (uint32_t)(av << 1)) {
 784         aIsLargerSignificand = 1;
 785     } else {
 786         aIsLargerSignificand = (av < bv) ? 1 : 0;
 787     }
 788
 789     if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
 790                 aIsLargerSignificand)) {
 791         return float32_maybe_silence_nan(b, status);
 792     } else {
 793         return float32_maybe_silence_nan(a, status);
 794     }
 795 }
 796
 797 /*----------------------------------------------------------------------------
 798 | Returns 1 if the double-precision floating-point value `a' is a quiet
 799 | NaN; otherwise returns 0.
 800 *----------------------------------------------------------------------------*/
 801
 802 int float64_is_quiet_nan(float64 a_, float_status *status)
 803 {
 804 #ifdef NO_SIGNALING_NANS
 805     return float64_is_any_nan(a_);
 806 #else
 807     uint64_t a = float64_val(a_);
 808     if (status->snan_bit_is_one) {
 809         return (((a >> 51) & 0xFFF) == 0xFFE)
 810             && (a & 0x0007FFFFFFFFFFFFULL);
 811     } else {
 812         return ((a << 1) >= 0xFFF0000000000000ULL);
 813     }
 814 #endif
 815 }
 816
 817 /*----------------------------------------------------------------------------
 818 | Returns 1 if the double-precision floating-point value `a' is a signaling
 819 | NaN; otherwise returns 0.
 820 *----------------------------------------------------------------------------*/
 821
 822 int float64_is_signaling_nan(float64 a_, float_status *status)
 823 {
 824 #ifdef NO_SIGNALING_NANS
 825     return 0;
 826 #else
 827     uint64_t a = float64_val(a_);
 828     if (status->snan_bit_is_one) {
 829         return ((a << 1) >= 0xFFF0000000000000ULL);
 830     } else {
 831         return (((a >> 51) & 0xFFF) == 0xFFE)
 832             && (a & LIT64(0x0007FFFFFFFFFFFF));
 833     }
 834 #endif
 835 }
 836
 837 /*----------------------------------------------------------------------------
 838 | Returns a quiet NaN from a signalling NaN for the double-precision
 839 | floating point value `a'.
 840 *----------------------------------------------------------------------------*/
 841
 842 float64 float64_silence_nan(float64 a, float_status *status)
 843 {
 844 #ifdef NO_SIGNALING_NANS
 845     g_assert_not_reached();
 846 #else
 847     if (status->snan_bit_is_one) {
 848 # ifdef TARGET_HPPA
 849         a &= ~0x0008000000000000ULL;
 850         a |=  0x0004000000000000ULL;
 851         return a;
 852 # else
 853         return float64_default_nan(status);
 854 # endif
 855     } else {
 856         return a | LIT64(0x0008000000000000);
 857     }
 858 #endif
 859 }
 860
 861 /*----------------------------------------------------------------------------
 862 | Returns a quiet NaN if the double-precision floating point value `a' is a
 863 | signaling NaN; otherwise returns `a'.
 864 *----------------------------------------------------------------------------*/
 865
 866 float64 float64_maybe_silence_nan(float64 a, float_status *status)
 867 {
 868     if (float64_is_signaling_nan(a, status)) {
 869         return float64_silence_nan(a, status);
 870     }
 871     return a;
 872 }
 873
 874 /*----------------------------------------------------------------------------
 875 | Returns the result of converting the double-precision floating-point NaN
 876 | `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
 877 | exception is raised.
 878 *----------------------------------------------------------------------------*/
 879
 880 static commonNaNT float64ToCommonNaN(float64 a, float_status *status)
 881 {
 882     commonNaNT z;
 883
 884     if (float64_is_signaling_nan(a, status)) {
 885         float_raise(float_flag_invalid, status);
 886     }
 887     z.sign = float64_val(a) >> 63;
 888     z.low = 0;
 889     z.high = float64_val(a) << 12;
 890     return z;
 891 }
 892
 893 /*----------------------------------------------------------------------------
 894 | Returns the result of converting the canonical NaN `a' to the double-
 895 | precision floating-point format.
 896 *----------------------------------------------------------------------------*/
 897
 898 static float64 commonNaNToFloat64(commonNaNT a, float_status *status)
 899 {
 900     uint64_t mantissa = a.high >> 12;
 901
 902     if (status->default_nan_mode) {
 903         return float64_default_nan(status);
 904     }
 905
 906     if (mantissa) {
 907         return make_float64(
 908               (((uint64_t) a.sign) << 63)
 909             | LIT64(0x7FF0000000000000)
 910             | (a.high >> 12));
 911     } else {
 912         return float64_default_nan(status);
 913     }
 914 }
 915
 916 /*----------------------------------------------------------------------------
 917 | Takes two double-precision floating-point values `a' and `b', one of which
 918 | is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a
 919 | signaling NaN, the invalid exception is raised.
 920 *----------------------------------------------------------------------------*/
 921
 922 static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status)
 923 {
 924     flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
 925     flag aIsLargerSignificand;
 926     uint64_t av, bv;
 927
 928     aIsQuietNaN = float64_is_quiet_nan(a, status);
 929     aIsSignalingNaN = float64_is_signaling_nan(a, status);
 930     bIsQuietNaN = float64_is_quiet_nan(b, status);
 931     bIsSignalingNaN = float64_is_signaling_nan(b, status);
 932     av = float64_val(a);
 933     bv = float64_val(b);
 934
 935     if (aIsSignalingNaN | bIsSignalingNaN) {
 936         float_raise(float_flag_invalid, status);
 937     }
 938
 939     if (status->default_nan_mode) {
 940         return float64_default_nan(status);
 941     }
 942
 943     if ((uint64_t)(av << 1) < (uint64_t)(bv << 1)) {
 944         aIsLargerSignificand = 0;
 945     } else if ((uint64_t)(bv << 1) < (uint64_t)(av << 1)) {
 946         aIsLargerSignificand = 1;
 947     } else {
 948         aIsLargerSignificand = (av < bv) ? 1 : 0;
 949     }
 950
 951     if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
 952                 aIsLargerSignificand)) {
 953         return float64_maybe_silence_nan(b, status);
 954     } else {
 955         return float64_maybe_silence_nan(a, status);
 956     }
 957 }
 958
 959 /*----------------------------------------------------------------------------
 960 | Returns 1 if the extended double-precision floating-point value `a' is a
 961 | quiet NaN; otherwise returns 0. This slightly differs from the same
 962 | function for other types as floatx80 has an explicit bit.
 963 *----------------------------------------------------------------------------*/
 964
 965 int floatx80_is_quiet_nan(floatx80 a, float_status *status)
 966 {
 967 #ifdef NO_SIGNALING_NANS
 968     return floatx80_is_any_nan(a);
 969 #else
 970     if (status->snan_bit_is_one) {
 971         uint64_t aLow;
 972
 973         aLow = a.low & ~0x4000000000000000ULL;
 974         return ((a.high & 0x7FFF) == 0x7FFF)
 975             && (aLow << 1)
 976             && (a.low == aLow);
 977     } else {
 978         return ((a.high & 0x7FFF) == 0x7FFF)
 979             && (LIT64(0x8000000000000000) <= ((uint64_t)(a.low << 1)));
 980     }
 981 #endif
 982 }
 983
 984 /*----------------------------------------------------------------------------
 985 | Returns 1 if the extended double-precision floating-point value `a' is a
 986 | signaling NaN; otherwise returns 0. This slightly differs from the same
 987 | function for other types as floatx80 has an explicit bit.
 988 *----------------------------------------------------------------------------*/
 989
 990 int floatx80_is_signaling_nan(floatx80 a, float_status *status)
 991 {
 992 #ifdef NO_SIGNALING_NANS
 993     return 0;
 994 #else
 995     if (status->snan_bit_is_one) {
 996         return ((a.high & 0x7FFF) == 0x7FFF)
 997             && ((a.low << 1) >= 0x8000000000000000ULL);
 998     } else {
 999         uint64_t aLow;
1000
1001         aLow = a.low & ~LIT64(0x4000000000000000);
1002         return ((a.high & 0x7FFF) == 0x7FFF)
1003             && (uint64_t)(aLow << 1)
1004             && (a.low == aLow);
1005     }
1006 #endif
1007 }
1008
1009 /*----------------------------------------------------------------------------
1010 | Returns a quiet NaN from a signalling NaN for the extended double-precision
1011 | floating point value `a'.
1012 *----------------------------------------------------------------------------*/
1013
1014 floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
1015 {
1016 #ifdef NO_SIGNALING_NANS
1017     g_assert_not_reached();
1018 #else
1019     if (status->snan_bit_is_one) {
1020         return floatx80_default_nan(status);
1021     } else {
1022         a.low |= LIT64(0xC000000000000000);
1023         return a;
1024     }
1025 #endif
1026 }
1027
1028 /*----------------------------------------------------------------------------
1029 | Returns a quiet NaN if the extended double-precision floating point value
1030 | `a' is a signaling NaN; otherwise returns `a'.
1031 *----------------------------------------------------------------------------*/
1032
1033 floatx80 floatx80_maybe_silence_nan(floatx80 a, float_status *status)
1034 {
1035     if (floatx80_is_signaling_nan(a, status)) {
1036         return floatx80_silence_nan(a, status);
1037     }
1038     return a;
1039 }
1040
1041 /*----------------------------------------------------------------------------
1042 | Returns the result of converting the extended double-precision floating-
1043 | point NaN `a' to the canonical NaN format.  If `a' is a signaling NaN, the
1044 | invalid exception is raised.
1045 *----------------------------------------------------------------------------*/
1046
1047 static commonNaNT floatx80ToCommonNaN(floatx80 a, float_status *status)
1048 {
1049     floatx80 dflt;
1050     commonNaNT z;
1051
1052     if (floatx80_is_signaling_nan(a, status)) {
1053         float_raise(float_flag_invalid, status);
1054     }
1055     if (a.low >> 63) {
1056         z.sign = a.high >> 15;
1057         z.low = 0;
1058         z.high = a.low << 1;
1059     } else {
1060         dflt = floatx80_default_nan(status);
1061         z.sign = dflt.high >> 15;
1062         z.low = 0;
1063         z.high = dflt.low << 1;
1064     }
1065     return z;
1066 }
1067
1068 /*----------------------------------------------------------------------------
1069 | Returns the result of converting the canonical NaN `a' to the extended
1070 | double-precision floating-point format.
1071 *----------------------------------------------------------------------------*/
1072
1073 static floatx80 commonNaNToFloatx80(commonNaNT a, float_status *status)
1074 {
1075     floatx80 z;
1076
1077     if (status->default_nan_mode) {
1078         return floatx80_default_nan(status);
1079     }
1080
1081     if (a.high >> 1) {
1082         z.low = LIT64(0x8000000000000000) | a.high >> 1;
1083         z.high = (((uint16_t)a.sign) << 15) | 0x7FFF;
1084     } else {
1085         z = floatx80_default_nan(status);
1086     }
1087     return z;
1088 }
1089
1090 /*----------------------------------------------------------------------------
1091 | Takes two extended double-precision floating-point values `a' and `b', one
1092 | of which is a NaN, and returns the appropriate NaN result.  If either `a' or
1093 | `b' is a signaling NaN, the invalid exception is raised.
1094 *----------------------------------------------------------------------------*/
1095
1096 floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
1097 {
1098     flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
1099     flag aIsLargerSignificand;
1100
1101     aIsQuietNaN = floatx80_is_quiet_nan(a, status);
1102     aIsSignalingNaN = floatx80_is_signaling_nan(a, status);
1103     bIsQuietNaN = floatx80_is_quiet_nan(b, status);
1104     bIsSignalingNaN = floatx80_is_signaling_nan(b, status);
1105
1106     if (aIsSignalingNaN | bIsSignalingNaN) {
1107         float_raise(float_flag_invalid, status);
1108     }
1109
1110     if (status->default_nan_mode) {
1111         return floatx80_default_nan(status);
1112     }
1113
1114     if (a.low < b.low) {
1115         aIsLargerSignificand = 0;
1116     } else if (b.low < a.low) {
1117         aIsLargerSignificand = 1;
1118     } else {
1119         aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
1120     }
1121
1122     if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
1123                 aIsLargerSignificand)) {
1124         return floatx80_maybe_silence_nan(b, status);
1125     } else {
1126         return floatx80_maybe_silence_nan(a, status);
1127     }
1128 }
1129
1130 /*----------------------------------------------------------------------------
1131 | Returns 1 if the quadruple-precision floating-point value `a' is a quiet
1132 | NaN; otherwise returns 0.
1133 *----------------------------------------------------------------------------*/
1134
1135 int float128_is_quiet_nan(float128 a, float_status *status)
1136 {
1137 #ifdef NO_SIGNALING_NANS
1138     return float128_is_any_nan(a);
1139 #else
1140     if (status->snan_bit_is_one) {
1141         return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
1142             && (a.low || (a.high & 0x00007FFFFFFFFFFFULL));
1143     } else {
1144         return ((a.high << 1) >= 0xFFFF000000000000ULL)
1145             && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
1146     }
1147 #endif
1148 }
1149
1150 /*----------------------------------------------------------------------------
1151 | Returns 1 if the quadruple-precision floating-point value `a' is a
1152 | signaling NaN; otherwise returns 0.
1153 *----------------------------------------------------------------------------*/
1154
1155 int float128_is_signaling_nan(float128 a, float_status *status)
1156 {
1157 #ifdef NO_SIGNALING_NANS
1158     return 0;
1159 #else
1160     if (status->snan_bit_is_one) {
1161         return ((a.high << 1) >= 0xFFFF000000000000ULL)
1162             && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
1163     } else {
1164         return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
1165             && (a.low || (a.high & LIT64(0x00007FFFFFFFFFFF)));
1166     }
1167 #endif
1168 }
1169
1170 /*----------------------------------------------------------------------------
1171 | Returns a quiet NaN from a signalling NaN for the quadruple-precision
1172 | floating point value `a'.
1173 *----------------------------------------------------------------------------*/
1174
1175 float128 float128_silence_nan(float128 a, float_status *status)
1176 {
1177 #ifdef NO_SIGNALING_NANS
1178     g_assert_not_reached();
1179 #else
1180     if (status->snan_bit_is_one) {
1181         return float128_default_nan(status);
1182     } else {
1183         a.high |= LIT64(0x0000800000000000);
1184         return a;
1185     }
1186 #endif
1187 }
1188
1189 /*----------------------------------------------------------------------------
1190 | Returns a quiet NaN if the quadruple-precision floating point value `a' is
1191 | a signaling NaN; otherwise returns `a'.
1192 *----------------------------------------------------------------------------*/
1193
1194 float128 float128_maybe_silence_nan(float128 a, float_status *status)
1195 {
1196     if (float128_is_signaling_nan(a, status)) {
1197         return float128_silence_nan(a, status);
1198     }
1199     return a;
1200 }
1201
1202 /*----------------------------------------------------------------------------
1203 | Returns the result of converting the quadruple-precision floating-point NaN
1204 | `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
1205 | exception is raised.
1206 *----------------------------------------------------------------------------*/
1207
1208 static commonNaNT float128ToCommonNaN(float128 a, float_status *status)
1209 {
1210     commonNaNT z;
1211
1212     if (float128_is_signaling_nan(a, status)) {
1213         float_raise(float_flag_invalid, status);
1214     }
1215     z.sign = a.high >> 63;
1216     shortShift128Left(a.high, a.low, 16, &z.high, &z.low);
1217     return z;
1218 }
1219
1220 /*----------------------------------------------------------------------------
1221 | Returns the result of converting the canonical NaN `a' to the quadruple-
1222 | precision floating-point format.
1223 *----------------------------------------------------------------------------*/
1224
1225 static float128 commonNaNToFloat128(commonNaNT a, float_status *status)
1226 {
1227     float128 z;
1228
1229     if (status->default_nan_mode) {
1230         return float128_default_nan(status);
1231     }
1232
1233     shift128Right(a.high, a.low, 16, &z.high, &z.low);
1234     z.high |= (((uint64_t)a.sign) << 63) | LIT64(0x7FFF000000000000);
1235     return z;
1236 }
1237
1238 /*----------------------------------------------------------------------------
1239 | Takes two quadruple-precision floating-point values `a' and `b', one of
1240 | which is a NaN, and returns the appropriate NaN result.  If either `a' or
1241 | `b' is a signaling NaN, the invalid exception is raised.
1242 *----------------------------------------------------------------------------*/
1243
1244 static float128 propagateFloat128NaN(float128 a, float128 b,
1245                                      float_status *status)
1246 {
1247     flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
1248     flag aIsLargerSignificand;
1249
1250     aIsQuietNaN = float128_is_quiet_nan(a, status);
1251     aIsSignalingNaN = float128_is_signaling_nan(a, status);
1252     bIsQuietNaN = float128_is_quiet_nan(b, status);
1253     bIsSignalingNaN = float128_is_signaling_nan(b, status);
1254
1255     if (aIsSignalingNaN | bIsSignalingNaN) {
1256         float_raise(float_flag_invalid, status);
1257     }
1258
1259     if (status->default_nan_mode) {
1260         return float128_default_nan(status);
1261     }
1262
1263     if (lt128(a.high << 1, a.low, b.high << 1, b.low)) {
1264         aIsLargerSignificand = 0;
1265     } else if (lt128(b.high << 1, b.low, a.high << 1, a.low)) {
1266         aIsLargerSignificand = 1;
1267     } else {
1268         aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
1269     }
1270
1271     if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
1272                 aIsLargerSignificand)) {
1273         return float128_maybe_silence_nan(b, status);
1274     } else {
1275         return float128_maybe_silence_nan(a, status);
1276     }
1277 }