fpu/softfloat-specialize.h

   1 /*
   2  * QEMU float support
   3  *
   4  * The code in this source file is derived from release 2a of the SoftFloat
   5  * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and
   6  * some later contributions) are provided under that license, as detailed below.
   7  * It has subsequently been modified by contributors to the QEMU Project,
   8  * so some portions are provided under:
   9  *  the SoftFloat-2a license
  10  *  the BSD license
  11  *  GPL-v2-or-later
  12  *
  13  * Any future contributions to this file after December 1st 2014 will be
  14  * taken to be licensed under the Softfloat-2a license unless specifically
  15  * indicated otherwise.
  16  */
  17
  18 /*
  19 ===============================================================================
  20 This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
  21 Arithmetic Package, Release 2a.
  22
  23 Written by John R. Hauser.  This work was made possible in part by the
  24 International Computer Science Institute, located at Suite 600, 1947 Center
  25 Street, Berkeley, California 94704.  Funding was partially provided by the
  26 National Science Foundation under grant MIP-9311980.  The original version
  27 of this code was written as part of a project to build a fixed-point vector
  28 processor in collaboration with the University of California at Berkeley,
  29 overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
  30 is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
  31 arithmetic/SoftFloat.html'.
  32
  33 THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort
  34 has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
  35 TIMES RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO
  36 PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
  37 AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
  38
  39 Derivative works are acceptable, even for commercial purposes, so long as
  40 (1) they include prominent notice that the work is derivative, and (2) they
  41 include prominent notice akin to these four paragraphs for those parts of
  42 this code that are retained.
  43
  44 ===============================================================================
  45 */
  46
  47 /* BSD licensing:
  48  * Copyright (c) 2006, Fabrice Bellard
  49  * All rights reserved.
  50  *
  51  * Redistribution and use in source and binary forms, with or without
  52  * modification, are permitted provided that the following conditions are met:
  53  *
  54  * 1. Redistributions of source code must retain the above copyright notice,
  55  * this list of conditions and the following disclaimer.
  56  *
  57  * 2. Redistributions in binary form must reproduce the above copyright notice,
  58  * this list of conditions and the following disclaimer in the documentation
  59  * and/or other materials provided with the distribution.
  60  *
  61  * 3. Neither the name of the copyright holder nor the names of its contributors
  62  * may be used to endorse or promote products derived from this software without
  63  * specific prior written permission.
  64  *
  65  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  66  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  67  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  68  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  69  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  70  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  71  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  72  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  73  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  74  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  75  * THE POSSIBILITY OF SUCH DAMAGE.
  76  */
  77
  78 /* Portions of this work are licensed under the terms of the GNU GPL,
  79  * version 2 or later. See the COPYING file in the top-level directory.
  80  */
  81
  82 #if defined(TARGET_XTENSA)
  83 /* Define for architectures which deviate from IEEE in not supporting
  84  * signaling NaNs (so all NaNs are treated as quiet).
  85  */
  86 #define NO_SIGNALING_NANS 1
  87 #endif
  88
  89 /*----------------------------------------------------------------------------
  90 | The pattern for a default generated half-precision NaN.
  91 *----------------------------------------------------------------------------*/
  92 float16 float16_default_nan(float_status *status)
  93 {
  94 #if defined(TARGET_ARM)
  95     return const_float16(0x7E00);
  96 #else
  97     if (status->snan_bit_is_one) {
  98         return const_float16(0x7DFF);
  99     } else {
 100 #if defined(TARGET_MIPS)
 101         return const_float16(0x7E00);
 102 #else
 103         return const_float16(0xFE00);
 104 #endif
 105     }
 106 #endif
 107 }
 108
 109 /*----------------------------------------------------------------------------
 110 | The pattern for a default generated single-precision NaN.
 111 *----------------------------------------------------------------------------*/
 112 float32 float32_default_nan(float_status *status)
 113 {
 114 #if defined(TARGET_SPARC) || defined(TARGET_M68K)
 115     return const_float32(0x7FFFFFFF);
 116 #elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \
 117       defined(TARGET_XTENSA) || defined(TARGET_S390X) || defined(TARGET_TRICORE)
 118     return const_float32(0x7FC00000);
 119 #elif defined(TARGET_HPPA)
 120     return const_float32(0x7FA00000);
 121 #else
 122     if (status->snan_bit_is_one) {
 123         return const_float32(0x7FBFFFFF);
 124     } else {
 125 #if defined(TARGET_MIPS)
 126         return const_float32(0x7FC00000);
 127 #else
 128         return const_float32(0xFFC00000);
 129 #endif
 130     }
 131 #endif
 132 }
 133
 134 /*----------------------------------------------------------------------------
 135 | The pattern for a default generated double-precision NaN.
 136 *----------------------------------------------------------------------------*/
 137 float64 float64_default_nan(float_status *status)
 138 {
 139 #if defined(TARGET_SPARC) || defined(TARGET_M68K)
 140     return const_float64(LIT64(0x7FFFFFFFFFFFFFFF));
 141 #elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \
 142       defined(TARGET_S390X)
 143     return const_float64(LIT64(0x7FF8000000000000));
 144 #elif defined(TARGET_HPPA)
 145     return const_float64(LIT64(0x7FF4000000000000));
 146 #else
 147     if (status->snan_bit_is_one) {
 148         return const_float64(LIT64(0x7FF7FFFFFFFFFFFF));
 149     } else {
 150 #if defined(TARGET_MIPS)
 151         return const_float64(LIT64(0x7FF8000000000000));
 152 #else
 153         return const_float64(LIT64(0xFFF8000000000000));
 154 #endif
 155     }
 156 #endif
 157 }
 158
 159 /*----------------------------------------------------------------------------
 160 | The pattern for a default generated extended double-precision NaN.
 161 *----------------------------------------------------------------------------*/
 162 floatx80 floatx80_default_nan(float_status *status)
 163 {
 164     floatx80 r;
 165 #if defined(TARGET_M68K)
 166     r.low = LIT64(0xFFFFFFFFFFFFFFFF);
 167     r.high = 0x7FFF;
 168 #else
 169     if (status->snan_bit_is_one) {
 170         r.low = LIT64(0xBFFFFFFFFFFFFFFF);
 171         r.high = 0x7FFF;
 172     } else {
 173         r.low = LIT64(0xC000000000000000);
 174         r.high = 0xFFFF;
 175     }
 176 #endif
 177     return r;
 178 }
 179
 180 /*----------------------------------------------------------------------------
 181 | The pattern for a default generated quadruple-precision NaN.
 182 *----------------------------------------------------------------------------*/
 183 float128 float128_default_nan(float_status *status)
 184 {
 185     float128 r;
 186
 187     if (status->snan_bit_is_one) {
 188         r.low = LIT64(0xFFFFFFFFFFFFFFFF);
 189         r.high = LIT64(0x7FFF7FFFFFFFFFFF);
 190     } else {
 191         r.low = LIT64(0x0000000000000000);
 192 #if defined(TARGET_S390X) || defined(TARGET_PPC)
 193         r.high = LIT64(0x7FFF800000000000);
 194 #else
 195         r.high = LIT64(0xFFFF800000000000);
 196 #endif
 197     }
 198     return r;
 199 }
 200
 201 /*----------------------------------------------------------------------------
 202 | Raises the exceptions specified by `flags'.  Floating-point traps can be
 203 | defined here if desired.  It is currently not possible for such a trap
 204 | to substitute a result value.  If traps are not implemented, this routine
 205 | should be simply `float_exception_flags |= flags;'.
 206 *----------------------------------------------------------------------------*/
 207
 208 void float_raise(uint8_t flags, float_status *status)
 209 {
 210     status->float_exception_flags |= flags;
 211 }
 212
 213 /*----------------------------------------------------------------------------
 214 | Internal canonical NaN format.
 215 *----------------------------------------------------------------------------*/
 216 typedef struct {
 217     flag sign;
 218     uint64_t high, low;
 219 } commonNaNT;
 220
 221 #ifdef NO_SIGNALING_NANS
 222 int float16_is_quiet_nan(float16 a_, float_status *status)
 223 {
 224     return float16_is_any_nan(a_);
 225 }
 226
 227 int float16_is_signaling_nan(float16 a_, float_status *status)
 228 {
 229     return 0;
 230 }
 231 #else
 232 /*----------------------------------------------------------------------------
 233 | Returns 1 if the half-precision floating-point value `a' is a quiet
 234 | NaN; otherwise returns 0.
 235 *----------------------------------------------------------------------------*/
 236
 237 int float16_is_quiet_nan(float16 a_, float_status *status)
 238 {
 239     uint16_t a = float16_val(a_);
 240     if (status->snan_bit_is_one) {
 241         return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
 242     } else {
 243         return ((a & ~0x8000) >= 0x7C80);
 244     }
 245 }
 246
 247 /*----------------------------------------------------------------------------
 248 | Returns 1 if the half-precision floating-point value `a' is a signaling
 249 | NaN; otherwise returns 0.
 250 *----------------------------------------------------------------------------*/
 251
 252 int float16_is_signaling_nan(float16 a_, float_status *status)
 253 {
 254     uint16_t a = float16_val(a_);
 255     if (status->snan_bit_is_one) {
 256         return ((a & ~0x8000) >= 0x7C80);
 257     } else {
 258         return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
 259     }
 260 }
 261 #endif
 262
 263 /*----------------------------------------------------------------------------
 264 | Returns a quiet NaN if the half-precision floating point value `a' is a
 265 | signaling NaN; otherwise returns `a'.
 266 *----------------------------------------------------------------------------*/
 267 float16 float16_maybe_silence_nan(float16 a_, float_status *status)
 268 {
 269     if (float16_is_signaling_nan(a_, status)) {
 270         if (status->snan_bit_is_one) {
 271             return float16_default_nan(status);
 272         } else {
 273             uint16_t a = float16_val(a_);
 274             a |= (1 << 9);
 275             return make_float16(a);
 276         }
 277     }
 278     return a_;
 279 }
 280
 281 /*----------------------------------------------------------------------------
 282 | Returns the result of converting the half-precision floating-point NaN
 283 | `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
 284 | exception is raised.
 285 *----------------------------------------------------------------------------*/
 286
 287 static commonNaNT float16ToCommonNaN(float16 a, float_status *status)
 288 {
 289     commonNaNT z;
 290
 291     if (float16_is_signaling_nan(a, status)) {
 292         float_raise(float_flag_invalid, status);
 293     }
 294     z.sign = float16_val(a) >> 15;
 295     z.low = 0;
 296     z.high = ((uint64_t) float16_val(a)) << 54;
 297     return z;
 298 }
 299
 300 /*----------------------------------------------------------------------------
 301 | Returns the result of converting the canonical NaN `a' to the half-
 302 | precision floating-point format.
 303 *----------------------------------------------------------------------------*/
 304
 305 static float16 commonNaNToFloat16(commonNaNT a, float_status *status)
 306 {
 307     uint16_t mantissa = a.high >> 54;
 308
 309     if (status->default_nan_mode) {
 310         return float16_default_nan(status);
 311     }
 312
 313     if (mantissa) {
 314         return make_float16(((((uint16_t) a.sign) << 15)
 315                              | (0x1F << 10) | mantissa));
 316     } else {
 317         return float16_default_nan(status);
 318     }
 319 }
 320
 321 #ifdef NO_SIGNALING_NANS
 322 int float32_is_quiet_nan(float32 a_, float_status *status)
 323 {
 324     return float32_is_any_nan(a_);
 325 }
 326
 327 int float32_is_signaling_nan(float32 a_, float_status *status)
 328 {
 329     return 0;
 330 }
 331 #else
 332 /*----------------------------------------------------------------------------
 333 | Returns 1 if the single-precision floating-point value `a' is a quiet
 334 | NaN; otherwise returns 0.
 335 *----------------------------------------------------------------------------*/
 336
 337 int float32_is_quiet_nan(float32 a_, float_status *status)
 338 {
 339     uint32_t a = float32_val(a_);
 340     if (status->snan_bit_is_one) {
 341         return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
 342     } else {
 343         return ((uint32_t)(a << 1) >= 0xFF800000);
 344     }
 345 }
 346
 347 /*----------------------------------------------------------------------------
 348 | Returns 1 if the single-precision floating-point value `a' is a signaling
 349 | NaN; otherwise returns 0.
 350 *----------------------------------------------------------------------------*/
 351
 352 int float32_is_signaling_nan(float32 a_, float_status *status)
 353 {
 354     uint32_t a = float32_val(a_);
 355     if (status->snan_bit_is_one) {
 356         return ((uint32_t)(a << 1) >= 0xFF800000);
 357     } else {
 358         return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
 359     }
 360 }
 361 #endif
 362
 363 /*----------------------------------------------------------------------------
 364 | Returns a quiet NaN if the single-precision floating point value `a' is a
 365 | signaling NaN; otherwise returns `a'.
 366 *----------------------------------------------------------------------------*/
 367
 368 float32 float32_maybe_silence_nan(float32 a_, float_status *status)
 369 {
 370     if (float32_is_signaling_nan(a_, status)) {
 371         if (status->snan_bit_is_one) {
 372 #ifdef TARGET_HPPA
 373             uint32_t a = float32_val(a_);
 374             a &= ~0x00400000;
 375             a |=  0x00200000;
 376             return make_float32(a);
 377 #else
 378             return float32_default_nan(status);
 379 #endif
 380         } else {
 381             uint32_t a = float32_val(a_);
 382             a |= (1 << 22);
 383             return make_float32(a);
 384         }
 385     }
 386     return a_;
 387 }
 388
 389 /*----------------------------------------------------------------------------
 390 | Returns the result of converting the single-precision floating-point NaN
 391 | `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
 392 | exception is raised.
 393 *----------------------------------------------------------------------------*/
 394
 395 static commonNaNT float32ToCommonNaN(float32 a, float_status *status)
 396 {
 397     commonNaNT z;
 398
 399     if (float32_is_signaling_nan(a, status)) {
 400         float_raise(float_flag_invalid, status);
 401     }
 402     z.sign = float32_val(a) >> 31;
 403     z.low = 0;
 404     z.high = ((uint64_t)float32_val(a)) << 41;
 405     return z;
 406 }
 407
 408 /*----------------------------------------------------------------------------
 409 | Returns the result of converting the canonical NaN `a' to the single-
 410 | precision floating-point format.
 411 *----------------------------------------------------------------------------*/
 412
 413 static float32 commonNaNToFloat32(commonNaNT a, float_status *status)
 414 {
 415     uint32_t mantissa = a.high >> 41;
 416
 417     if (status->default_nan_mode) {
 418         return float32_default_nan(status);
 419     }
 420
 421     if (mantissa) {
 422         return make_float32(
 423             (((uint32_t)a.sign) << 31) | 0x7F800000 | (a.high >> 41));
 424     } else {
 425         return float32_default_nan(status);
 426     }
 427 }
 428
 429 /*----------------------------------------------------------------------------
 430 | Select which NaN to propagate for a two-input operation.
 431 | IEEE754 doesn't specify all the details of this, so the
 432 | algorithm is target-specific.
 433 | The routine is passed various bits of information about the
 434 | two NaNs and should return 0 to select NaN a and 1 for NaN b.
 435 | Note that signalling NaNs are always squashed to quiet NaNs
 436 | by the caller, by calling floatXX_maybe_silence_nan() before
 437 | returning them.
 438 |
 439 | aIsLargerSignificand is only valid if both a and b are NaNs
 440 | of some kind, and is true if a has the larger significand,
 441 | or if both a and b have the same significand but a is
 442 | positive but b is negative. It is only needed for the x87
 443 | tie-break rule.
 444 *----------------------------------------------------------------------------*/
 445
 446 #if defined(TARGET_ARM)
 447 static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 448                    flag aIsLargerSignificand)
 449 {
 450     /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take
 451      * the first of:
 452      *  1. A if it is signaling
 453      *  2. B if it is signaling
 454      *  3. A (quiet)
 455      *  4. B (quiet)
 456      * A signaling NaN is always quietened before returning it.
 457      */
 458     if (aIsSNaN) {
 459         return 0;
 460     } else if (bIsSNaN) {
 461         return 1;
 462     } else if (aIsQNaN) {
 463         return 0;
 464     } else {
 465         return 1;
 466     }
 467 }
 468 #elif defined(TARGET_MIPS) || defined(TARGET_HPPA)
 469 static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 470                     flag aIsLargerSignificand)
 471 {
 472     /* According to MIPS specifications, if one of the two operands is
 473      * a sNaN, a new qNaN has to be generated. This is done in
 474      * floatXX_maybe_silence_nan(). For qNaN inputs the specifications
 475      * says: "When possible, this QNaN result is one of the operand QNaN
 476      * values." In practice it seems that most implementations choose
 477      * the first operand if both operands are qNaN. In short this gives
 478      * the following rules:
 479      *  1. A if it is signaling
 480      *  2. B if it is signaling
 481      *  3. A (quiet)
 482      *  4. B (quiet)
 483      * A signaling NaN is always silenced before returning it.
 484      */
 485     if (aIsSNaN) {
 486         return 0;
 487     } else if (bIsSNaN) {
 488         return 1;
 489     } else if (aIsQNaN) {
 490         return 0;
 491     } else {
 492         return 1;
 493     }
 494 }
 495 #elif defined(TARGET_PPC) || defined(TARGET_XTENSA)
 496 static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 497                    flag aIsLargerSignificand)
 498 {
 499     /* PowerPC propagation rules:
 500      *  1. A if it sNaN or qNaN
 501      *  2. B if it sNaN or qNaN
 502      * A signaling NaN is always silenced before returning it.
 503      */
 504     if (aIsSNaN || aIsQNaN) {
 505         return 0;
 506     } else {
 507         return 1;
 508     }
 509 }
 510 #elif defined(TARGET_M68K)
 511 static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 512                    flag aIsLargerSignificand)
 513 {
 514     /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
 515      * 3.4 FLOATING-POINT INSTRUCTION DETAILS
 516      * If either operand, but not both operands, of an operation is a
 517      * nonsignaling NaN, then that NaN is returned as the result. If both
 518      * operands are nonsignaling NaNs, then the destination operand
 519      * nonsignaling NaN is returned as the result.
 520      * If either operand to an operation is a signaling NaN (SNaN), then the
 521      * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit
 522      * is set in the FPCR ENABLE byte, then the exception is taken and the
 523      * destination is not modified. If the SNaN exception enable bit is not
 524      * set, setting the SNaN bit in the operand to a one converts the SNaN to
 525      * a nonsignaling NaN. The operation then continues as described in the
 526      * preceding paragraph for nonsignaling NaNs.
 527      */
 528     if (aIsQNaN || aIsSNaN) { /* a is the destination operand */
 529         return 0; /* return the destination operand */
 530     } else {
 531         return 1; /* return b */
 532     }
 533 }
 534 #else
 535 static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 536                     flag aIsLargerSignificand)
 537 {
 538     /* This implements x87 NaN propagation rules:
 539      * SNaN + QNaN => return the QNaN
 540      * two SNaNs => return the one with the larger significand, silenced
 541      * two QNaNs => return the one with the larger significand
 542      * SNaN and a non-NaN => return the SNaN, silenced
 543      * QNaN and a non-NaN => return the QNaN
 544      *
 545      * If we get down to comparing significands and they are the same,
 546      * return the NaN with the positive sign bit (if any).
 547      */
 548     if (aIsSNaN) {
 549         if (bIsSNaN) {
 550             return aIsLargerSignificand ? 0 : 1;
 551         }
 552         return bIsQNaN ? 1 : 0;
 553     } else if (aIsQNaN) {
 554         if (bIsSNaN || !bIsQNaN) {
 555             return 0;
 556         } else {
 557             return aIsLargerSignificand ? 0 : 1;
 558         }
 559     } else {
 560         return 1;
 561     }
 562 }
 563 #endif
 564
 565 /*----------------------------------------------------------------------------
 566 | Select which NaN to propagate for a three-input operation.
 567 | For the moment we assume that no CPU needs the 'larger significand'
 568 | information.
 569 | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
 570 *----------------------------------------------------------------------------*/
 571 #if defined(TARGET_ARM)
 572 static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 573                          flag cIsQNaN, flag cIsSNaN, flag infzero,
 574                          float_status *status)
 575 {
 576     /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
 577      * the default NaN
 578      */
 579     if (infzero && cIsQNaN) {
 580         float_raise(float_flag_invalid, status);
 581         return 3;
 582     }
 583
 584     /* This looks different from the ARM ARM pseudocode, because the ARM ARM
 585      * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
 586      */
 587     if (cIsSNaN) {
 588         return 2;
 589     } else if (aIsSNaN) {
 590         return 0;
 591     } else if (bIsSNaN) {
 592         return 1;
 593     } else if (cIsQNaN) {
 594         return 2;
 595     } else if (aIsQNaN) {
 596         return 0;
 597     } else {
 598         return 1;
 599     }
 600 }
 601 #elif defined(TARGET_MIPS)
 602 static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 603                          flag cIsQNaN, flag cIsSNaN, flag infzero,
 604                          float_status *status)
 605 {
 606     /* For MIPS, the (inf,zero,qnan) case sets InvalidOp and returns
 607      * the default NaN
 608      */
 609     if (infzero) {
 610         float_raise(float_flag_invalid, status);
 611         return 3;
 612     }
 613
 614     if (status->snan_bit_is_one) {
 615         /* Prefer sNaN over qNaN, in the a, b, c order. */
 616         if (aIsSNaN) {
 617             return 0;
 618         } else if (bIsSNaN) {
 619             return 1;
 620         } else if (cIsSNaN) {
 621             return 2;
 622         } else if (aIsQNaN) {
 623             return 0;
 624         } else if (bIsQNaN) {
 625             return 1;
 626         } else {
 627             return 2;
 628         }
 629     } else {
 630         /* Prefer sNaN over qNaN, in the c, a, b order. */
 631         if (cIsSNaN) {
 632             return 2;
 633         } else if (aIsSNaN) {
 634             return 0;
 635         } else if (bIsSNaN) {
 636             return 1;
 637         } else if (cIsQNaN) {
 638             return 2;
 639         } else if (aIsQNaN) {
 640             return 0;
 641         } else {
 642             return 1;
 643         }
 644     }
 645 }
 646 #elif defined(TARGET_PPC)
 647 static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 648                          flag cIsQNaN, flag cIsSNaN, flag infzero,
 649                          float_status *status)
 650 {
 651     /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
 652      * to return an input NaN if we have one (ie c) rather than generating
 653      * a default NaN
 654      */
 655     if (infzero) {
 656         float_raise(float_flag_invalid, status);
 657         return 2;
 658     }
 659
 660     /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
 661      * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
 662      */
 663     if (aIsSNaN || aIsQNaN) {
 664         return 0;
 665     } else if (cIsSNaN || cIsQNaN) {
 666         return 2;
 667     } else {
 668         return 1;
 669     }
 670 }
 671 #else
 672 /* A default implementation: prefer a to b to c.
 673  * This is unlikely to actually match any real implementation.
 674  */
 675 static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 676                          flag cIsQNaN, flag cIsSNaN, flag infzero,
 677                          float_status *status)
 678 {
 679     if (aIsSNaN || aIsQNaN) {
 680         return 0;
 681     } else if (bIsSNaN || bIsQNaN) {
 682         return 1;
 683     } else {
 684         return 2;
 685     }
 686 }
 687 #endif
 688
 689 /*----------------------------------------------------------------------------
 690 | Takes two single-precision floating-point values `a' and `b', one of which
 691 | is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a
 692 | signaling NaN, the invalid exception is raised.
 693 *----------------------------------------------------------------------------*/
 694
 695 static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status)
 696 {
 697     flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
 698     flag aIsLargerSignificand;
 699     uint32_t av, bv;
 700
 701     aIsQuietNaN = float32_is_quiet_nan(a, status);
 702     aIsSignalingNaN = float32_is_signaling_nan(a, status);
 703     bIsQuietNaN = float32_is_quiet_nan(b, status);
 704     bIsSignalingNaN = float32_is_signaling_nan(b, status);
 705     av = float32_val(a);
 706     bv = float32_val(b);
 707
 708     if (aIsSignalingNaN | bIsSignalingNaN) {
 709         float_raise(float_flag_invalid, status);
 710     }
 711
 712     if (status->default_nan_mode) {
 713         return float32_default_nan(status);
 714     }
 715
 716     if ((uint32_t)(av << 1) < (uint32_t)(bv << 1)) {
 717         aIsLargerSignificand = 0;
 718     } else if ((uint32_t)(bv << 1) < (uint32_t)(av << 1)) {
 719         aIsLargerSignificand = 1;
 720     } else {
 721         aIsLargerSignificand = (av < bv) ? 1 : 0;
 722     }
 723
 724     if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
 725                 aIsLargerSignificand)) {
 726         return float32_maybe_silence_nan(b, status);
 727     } else {
 728         return float32_maybe_silence_nan(a, status);
 729     }
 730 }
 731
 732 #ifdef NO_SIGNALING_NANS
 733 int float64_is_quiet_nan(float64 a_, float_status *status)
 734 {
 735     return float64_is_any_nan(a_);
 736 }
 737
 738 int float64_is_signaling_nan(float64 a_, float_status *status)
 739 {
 740     return 0;
 741 }
 742 #else
 743 /*----------------------------------------------------------------------------
 744 | Returns 1 if the double-precision floating-point value `a' is a quiet
 745 | NaN; otherwise returns 0.
 746 *----------------------------------------------------------------------------*/
 747
 748 int float64_is_quiet_nan(float64 a_, float_status *status)
 749 {
 750     uint64_t a = float64_val(a_);
 751     if (status->snan_bit_is_one) {
 752         return (((a >> 51) & 0xFFF) == 0xFFE)
 753             && (a & 0x0007FFFFFFFFFFFFULL);
 754     } else {
 755         return ((a << 1) >= 0xFFF0000000000000ULL);
 756     }
 757 }
 758
 759 /*----------------------------------------------------------------------------
 760 | Returns 1 if the double-precision floating-point value `a' is a signaling
 761 | NaN; otherwise returns 0.
 762 *----------------------------------------------------------------------------*/
 763
 764 int float64_is_signaling_nan(float64 a_, float_status *status)
 765 {
 766     uint64_t a = float64_val(a_);
 767     if (status->snan_bit_is_one) {
 768         return ((a << 1) >= 0xFFF0000000000000ULL);
 769     } else {
 770         return (((a >> 51) & 0xFFF) == 0xFFE)
 771             && (a & LIT64(0x0007FFFFFFFFFFFF));
 772     }
 773 }
 774 #endif
 775
 776 /*----------------------------------------------------------------------------
 777 | Returns a quiet NaN if the double-precision floating point value `a' is a
 778 | signaling NaN; otherwise returns `a'.
 779 *----------------------------------------------------------------------------*/
 780
 781 float64 float64_maybe_silence_nan(float64 a_, float_status *status)
 782 {
 783     if (float64_is_signaling_nan(a_, status)) {
 784         if (status->snan_bit_is_one) {
 785 #ifdef TARGET_HPPA
 786             uint64_t a = float64_val(a_);
 787             a &= ~0x0008000000000000ULL;
 788             a |=  0x0004000000000000ULL;
 789             return make_float64(a);
 790 #else
 791             return float64_default_nan(status);
 792 #endif
 793         } else {
 794             uint64_t a = float64_val(a_);
 795             a |= LIT64(0x0008000000000000);
 796             return make_float64(a);
 797         }
 798     }
 799     return a_;
 800 }
 801
 802 /*----------------------------------------------------------------------------
 803 | Returns the result of converting the double-precision floating-point NaN
 804 | `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
 805 | exception is raised.
 806 *----------------------------------------------------------------------------*/
 807
 808 static commonNaNT float64ToCommonNaN(float64 a, float_status *status)
 809 {
 810     commonNaNT z;
 811
 812     if (float64_is_signaling_nan(a, status)) {
 813         float_raise(float_flag_invalid, status);
 814     }
 815     z.sign = float64_val(a) >> 63;
 816     z.low = 0;
 817     z.high = float64_val(a) << 12;
 818     return z;
 819 }
 820
 821 /*----------------------------------------------------------------------------
 822 | Returns the result of converting the canonical NaN `a' to the double-
 823 | precision floating-point format.
 824 *----------------------------------------------------------------------------*/
 825
 826 static float64 commonNaNToFloat64(commonNaNT a, float_status *status)
 827 {
 828     uint64_t mantissa = a.high >> 12;
 829
 830     if (status->default_nan_mode) {
 831         return float64_default_nan(status);
 832     }
 833
 834     if (mantissa) {
 835         return make_float64(
 836               (((uint64_t) a.sign) << 63)
 837             | LIT64(0x7FF0000000000000)
 838             | (a.high >> 12));
 839     } else {
 840         return float64_default_nan(status);
 841     }
 842 }
 843
 844 /*----------------------------------------------------------------------------
 845 | Takes two double-precision floating-point values `a' and `b', one of which
 846 | is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a
 847 | signaling NaN, the invalid exception is raised.
 848 *----------------------------------------------------------------------------*/
 849
 850 static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status)
 851 {
 852     flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
 853     flag aIsLargerSignificand;
 854     uint64_t av, bv;
 855
 856     aIsQuietNaN = float64_is_quiet_nan(a, status);
 857     aIsSignalingNaN = float64_is_signaling_nan(a, status);
 858     bIsQuietNaN = float64_is_quiet_nan(b, status);
 859     bIsSignalingNaN = float64_is_signaling_nan(b, status);
 860     av = float64_val(a);
 861     bv = float64_val(b);
 862
 863     if (aIsSignalingNaN | bIsSignalingNaN) {
 864         float_raise(float_flag_invalid, status);
 865     }
 866
 867     if (status->default_nan_mode) {
 868         return float64_default_nan(status);
 869     }
 870
 871     if ((uint64_t)(av << 1) < (uint64_t)(bv << 1)) {
 872         aIsLargerSignificand = 0;
 873     } else if ((uint64_t)(bv << 1) < (uint64_t)(av << 1)) {
 874         aIsLargerSignificand = 1;
 875     } else {
 876         aIsLargerSignificand = (av < bv) ? 1 : 0;
 877     }
 878
 879     if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
 880                 aIsLargerSignificand)) {
 881         return float64_maybe_silence_nan(b, status);
 882     } else {
 883         return float64_maybe_silence_nan(a, status);
 884     }
 885 }
 886
 887 #ifdef NO_SIGNALING_NANS
 888 int floatx80_is_quiet_nan(floatx80 a_, float_status *status)
 889 {
 890     return floatx80_is_any_nan(a_);
 891 }
 892
 893 int floatx80_is_signaling_nan(floatx80 a_, float_status *status)
 894 {
 895     return 0;
 896 }
 897 #else
 898 /*----------------------------------------------------------------------------
 899 | Returns 1 if the extended double-precision floating-point value `a' is a
 900 | quiet NaN; otherwise returns 0. This slightly differs from the same
 901 | function for other types as floatx80 has an explicit bit.
 902 *----------------------------------------------------------------------------*/
 903
 904 int floatx80_is_quiet_nan(floatx80 a, float_status *status)
 905 {
 906     if (status->snan_bit_is_one) {
 907         uint64_t aLow;
 908
 909         aLow = a.low & ~0x4000000000000000ULL;
 910         return ((a.high & 0x7FFF) == 0x7FFF)
 911             && (aLow << 1)
 912             && (a.low == aLow);
 913     } else {
 914         return ((a.high & 0x7FFF) == 0x7FFF)
 915             && (LIT64(0x8000000000000000) <= ((uint64_t)(a.low << 1)));
 916     }
 917 }
 918
 919 /*----------------------------------------------------------------------------
 920 | Returns 1 if the extended double-precision floating-point value `a' is a
 921 | signaling NaN; otherwise returns 0. This slightly differs from the same
 922 | function for other types as floatx80 has an explicit bit.
 923 *----------------------------------------------------------------------------*/
 924
 925 int floatx80_is_signaling_nan(floatx80 a, float_status *status)
 926 {
 927     if (status->snan_bit_is_one) {
 928         return ((a.high & 0x7FFF) == 0x7FFF)
 929             && ((a.low << 1) >= 0x8000000000000000ULL);
 930     } else {
 931         uint64_t aLow;
 932
 933         aLow = a.low & ~LIT64(0x4000000000000000);
 934         return ((a.high & 0x7FFF) == 0x7FFF)
 935             && (uint64_t)(aLow << 1)
 936             && (a.low == aLow);
 937     }
 938 }
 939 #endif
 940
 941 /*----------------------------------------------------------------------------
 942 | Returns a quiet NaN if the extended double-precision floating point value
 943 | `a' is a signaling NaN; otherwise returns `a'.
 944 *----------------------------------------------------------------------------*/
 945
 946 floatx80 floatx80_maybe_silence_nan(floatx80 a, float_status *status)
 947 {
 948     if (floatx80_is_signaling_nan(a, status)) {
 949         if (status->snan_bit_is_one) {
 950             a = floatx80_default_nan(status);
 951         } else {
 952             a.low |= LIT64(0xC000000000000000);
 953             return a;
 954         }
 955     }
 956     return a;
 957 }
 958
 959 /*----------------------------------------------------------------------------
 960 | Returns the result of converting the extended double-precision floating-
 961 | point NaN `a' to the canonical NaN format.  If `a' is a signaling NaN, the
 962 | invalid exception is raised.
 963 *----------------------------------------------------------------------------*/
 964
 965 static commonNaNT floatx80ToCommonNaN(floatx80 a, float_status *status)
 966 {
 967     floatx80 dflt;
 968     commonNaNT z;
 969
 970     if (floatx80_is_signaling_nan(a, status)) {
 971         float_raise(float_flag_invalid, status);
 972     }
 973     if (a.low >> 63) {
 974         z.sign = a.high >> 15;
 975         z.low = 0;
 976         z.high = a.low << 1;
 977     } else {
 978         dflt = floatx80_default_nan(status);
 979         z.sign = dflt.high >> 15;
 980         z.low = 0;
 981         z.high = dflt.low << 1;
 982     }
 983     return z;
 984 }
 985
 986 /*----------------------------------------------------------------------------
 987 | Returns the result of converting the canonical NaN `a' to the extended
 988 | double-precision floating-point format.
 989 *----------------------------------------------------------------------------*/
 990
 991 static floatx80 commonNaNToFloatx80(commonNaNT a, float_status *status)
 992 {
 993     floatx80 z;
 994
 995     if (status->default_nan_mode) {
 996         return floatx80_default_nan(status);
 997     }
 998
 999     if (a.high >> 1) {
1000         z.low = LIT64(0x8000000000000000) | a.high >> 1;
1001         z.high = (((uint16_t)a.sign) << 15) | 0x7FFF;
1002     } else {
1003         z = floatx80_default_nan(status);
1004     }
1005     return z;
1006 }
1007
1008 /*----------------------------------------------------------------------------
1009 | Takes two extended double-precision floating-point values `a' and `b', one
1010 | of which is a NaN, and returns the appropriate NaN result.  If either `a' or
1011 | `b' is a signaling NaN, the invalid exception is raised.
1012 *----------------------------------------------------------------------------*/
1013
1014 floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
1015 {
1016     flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
1017     flag aIsLargerSignificand;
1018
1019     aIsQuietNaN = floatx80_is_quiet_nan(a, status);
1020     aIsSignalingNaN = floatx80_is_signaling_nan(a, status);
1021     bIsQuietNaN = floatx80_is_quiet_nan(b, status);
1022     bIsSignalingNaN = floatx80_is_signaling_nan(b, status);
1023
1024     if (aIsSignalingNaN | bIsSignalingNaN) {
1025         float_raise(float_flag_invalid, status);
1026     }
1027
1028     if (status->default_nan_mode) {
1029         return floatx80_default_nan(status);
1030     }
1031
1032     if (a.low < b.low) {
1033         aIsLargerSignificand = 0;
1034     } else if (b.low < a.low) {
1035         aIsLargerSignificand = 1;
1036     } else {
1037         aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
1038     }
1039
1040     if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
1041                 aIsLargerSignificand)) {
1042         return floatx80_maybe_silence_nan(b, status);
1043     } else {
1044         return floatx80_maybe_silence_nan(a, status);
1045     }
1046 }
1047
1048 #ifdef NO_SIGNALING_NANS
1049 int float128_is_quiet_nan(float128 a_, float_status *status)
1050 {
1051     return float128_is_any_nan(a_);
1052 }
1053
1054 int float128_is_signaling_nan(float128 a_, float_status *status)
1055 {
1056     return 0;
1057 }
1058 #else
1059 /*----------------------------------------------------------------------------
1060 | Returns 1 if the quadruple-precision floating-point value `a' is a quiet
1061 | NaN; otherwise returns 0.
1062 *----------------------------------------------------------------------------*/
1063
1064 int float128_is_quiet_nan(float128 a, float_status *status)
1065 {
1066     if (status->snan_bit_is_one) {
1067         return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
1068             && (a.low || (a.high & 0x00007FFFFFFFFFFFULL));
1069     } else {
1070         return ((a.high << 1) >= 0xFFFF000000000000ULL)
1071             && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
1072     }
1073 }
1074
1075 /*----------------------------------------------------------------------------
1076 | Returns 1 if the quadruple-precision floating-point value `a' is a
1077 | signaling NaN; otherwise returns 0.
1078 *----------------------------------------------------------------------------*/
1079
1080 int float128_is_signaling_nan(float128 a, float_status *status)
1081 {
1082     if (status->snan_bit_is_one) {
1083         return ((a.high << 1) >= 0xFFFF000000000000ULL)
1084             && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
1085     } else {
1086         return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
1087             && (a.low || (a.high & LIT64(0x00007FFFFFFFFFFF)));
1088     }
1089 }
1090 #endif
1091
1092 /*----------------------------------------------------------------------------
1093 | Returns a quiet NaN if the quadruple-precision floating point value `a' is
1094 | a signaling NaN; otherwise returns `a'.
1095 *----------------------------------------------------------------------------*/
1096
1097 float128 float128_maybe_silence_nan(float128 a, float_status *status)
1098 {
1099     if (float128_is_signaling_nan(a, status)) {
1100         if (status->snan_bit_is_one) {
1101             a = float128_default_nan(status);
1102         } else {
1103             a.high |= LIT64(0x0000800000000000);
1104             return a;
1105         }
1106     }
1107     return a;
1108 }
1109
1110 /*----------------------------------------------------------------------------
1111 | Returns the result of converting the quadruple-precision floating-point NaN
1112 | `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
1113 | exception is raised.
1114 *----------------------------------------------------------------------------*/
1115
1116 static commonNaNT float128ToCommonNaN(float128 a, float_status *status)
1117 {
1118     commonNaNT z;
1119
1120     if (float128_is_signaling_nan(a, status)) {
1121         float_raise(float_flag_invalid, status);
1122     }
1123     z.sign = a.high >> 63;
1124     shortShift128Left(a.high, a.low, 16, &z.high, &z.low);
1125     return z;
1126 }
1127
1128 /*----------------------------------------------------------------------------
1129 | Returns the result of converting the canonical NaN `a' to the quadruple-
1130 | precision floating-point format.
1131 *----------------------------------------------------------------------------*/
1132
1133 static float128 commonNaNToFloat128(commonNaNT a, float_status *status)
1134 {
1135     float128 z;
1136
1137     if (status->default_nan_mode) {
1138         return float128_default_nan(status);
1139     }
1140
1141     shift128Right(a.high, a.low, 16, &z.high, &z.low);
1142     z.high |= (((uint64_t)a.sign) << 63) | LIT64(0x7FFF000000000000);
1143     return z;
1144 }
1145
1146 /*----------------------------------------------------------------------------
1147 | Takes two quadruple-precision floating-point values `a' and `b', one of
1148 | which is a NaN, and returns the appropriate NaN result.  If either `a' or
1149 | `b' is a signaling NaN, the invalid exception is raised.
1150 *----------------------------------------------------------------------------*/
1151
1152 static float128 propagateFloat128NaN(float128 a, float128 b,
1153                                      float_status *status)
1154 {
1155     flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
1156     flag aIsLargerSignificand;
1157
1158     aIsQuietNaN = float128_is_quiet_nan(a, status);
1159     aIsSignalingNaN = float128_is_signaling_nan(a, status);
1160     bIsQuietNaN = float128_is_quiet_nan(b, status);
1161     bIsSignalingNaN = float128_is_signaling_nan(b, status);
1162
1163     if (aIsSignalingNaN | bIsSignalingNaN) {
1164         float_raise(float_flag_invalid, status);
1165     }
1166
1167     if (status->default_nan_mode) {
1168         return float128_default_nan(status);
1169     }
1170
1171     if (lt128(a.high << 1, a.low, b.high << 1, b.low)) {
1172         aIsLargerSignificand = 0;
1173     } else if (lt128(b.high << 1, b.low, a.high << 1, a.low)) {
1174         aIsLargerSignificand = 1;
1175     } else {
1176         aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
1177     }
1178
1179     if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
1180                 aIsLargerSignificand)) {
1181         return float128_maybe_silence_nan(b, status);
1182     } else {
1183         return float128_maybe_silence_nan(a, status);
1184     }
1185 }