grub-core/kern/arm/cache.S

   1 /*
   2  *  GRUB  --  GRand Unified Bootloader
   3  *  Copyright (C) 2013  Free Software Foundation, Inc.
   4  *
   5  *  GRUB is free software: you can redistribute it and/or modify
   6  *  it under the terms of the GNU General Public License as published by
   7  *  the Free Software Foundation, either version 3 of the License, or
   8  *  (at your option) any later version.
   9  *
  10  *  GRUB is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with GRUB.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <grub/symbol.h>
  20
  21         .file   "cache.S"
  22         .text
  23         .syntax unified
  24 #if !defined (__thumb2__) || !defined (ARMV7)
  25         .arm
  26 #else
  27         .thumb
  28 #endif
  29
  30 #if !defined (ARMV6) && !defined (ARMV7)
  31 # error Unsupported architecture version!
  32 #endif
  33
  34         .align  2
  35
  36 /*
  37  * Simple cache maintenance functions
  38  */
  39
  40 @ r0 - *beg (inclusive)
  41 @ r1 - *end (exclusive)
  42 @void grub_arm_clean_dcache_range (grub_addr_t start, grub_addr_t end, grub_addr_t dlinesz)
  43 #ifdef ARMV6
  44 FUNCTION(grub_arm_clean_dcache_range_armv6)
  45 #else
  46 FUNCTION(grub_arm_clean_dcache_range_armv7)
  47 #endif
  48         DSB
  49         @ Clean data cache for range to point-of-unification
  50 1:      cmp     r0, r1
  51         bge     2f
  52 #ifdef ARMV6
  53         mcr     p15, 0, r0, c7, c10, 1  @ Clean data cache line by MVA
  54 #else
  55         mcr     p15, 0, r0, c7, c11, 1  @ DCCMVAU
  56 #endif
  57         add     r0, r0, r2              @ Next line
  58         b       1b
  59 2:      DSB
  60         bx      lr
  61
  62 @ r0 - *beg (inclusive)
  63 @ r1 - *end (exclusive)
  64 #ifdef ARMV6
  65 FUNCTION(grub_arm_invalidate_icache_range_armv6)
  66 #else
  67 FUNCTION(grub_arm_invalidate_icache_range_armv7)
  68 #endif
  69         @ Invalidate instruction cache for range to point-of-unification
  70 1:      cmp     r0, r1
  71         bge     2f
  72         mcr     p15, 0, r0, c7, c5, 1   @ ICIMVAU
  73         add     r0, r0, r2              @ Next line
  74         b       1b
  75         @ Branch predictor invalidate all
  76 2:      mcr     p15, 0, r0, c7, c5, 6   @ BPIALL
  77         DSB
  78         ISB
  79         bx      lr
  80
  81 #ifdef ARMV6
  82 FUNCTION(grub_arm_disable_caches_mmu_armv6)
  83 #else
  84 FUNCTION(grub_arm_disable_caches_mmu_armv7)
  85 #endif
  86
  87         push    {r4, lr}
  88
  89         @ disable D-cache
  90         mrc     p15, 0, r0, c1, c0, 0
  91         bic     r0, r0, #(1 << 2)
  92         mcr     p15, 0, r0, c1, c0, 0
  93         DSB
  94         ISB
  95
  96         @ clean/invalidate D-cache
  97         bl      clean_invalidate_dcache
  98
  99         @ disable I-cache
 100         mrc     p15, 0, r0, c1, c0, 0
 101         bic     r0, r0, #(1 << 12)
 102         mcr     p15, 0, r0, c1, c0, 0
 103         DSB
 104         ISB
 105
 106         @ invalidate I-cache (also invalidates branch predictors)
 107         mcr     p15, 0, r0, c7, c5, 0
 108         DSB
 109         ISB
 110
 111         @ clear SCTLR M bit
 112         mrc     p15, 0, r0, c1, c0, 0
 113         bic     r0, r0, #(1 << 0)
 114         mcr     p15, 0, r0, c1, c0, 0
 115
 116         mcr     p15, 0, r0, c8, c7, 0   @ invalidate TLB
 117         mcr     p15, 0, r0, c7, c5, 6   @ invalidate branch predictor
 118         DSB
 119         ISB
 120
 121         pop     {r4, lr}
 122         bx      lr
 123