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1 /*
2 * QEMU<->ACPI BIOS PCI hotplug interface
3 *
4 * QEMU supports PCI hotplug via ACPI. This module
5 * implements the interface between QEMU and the ACPI BIOS.
6 * Interface specification - see docs/specs/acpi_pci_hotplug.txt
7 *
8 * Copyright (c) 2013, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
9 * Copyright (c) 2006 Fabrice Bellard
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License version 2.1 as published by the Free Software Foundation.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, see <http://www.gnu.org/licenses/>
22 *
23 * Contributions after 2012-01-13 are licensed under the terms of the
24 * GNU GPL, version 2 or (at your option) any later version.
25 */
26
27 #include "qemu/osdep.h"
28 #include "hw/acpi/pcihp.h"
29
30 #include "hw/pci-host/i440fx.h"
31 #include "hw/pci/pci.h"
32 #include "hw/pci/pci_bridge.h"
33 #include "hw/acpi/acpi.h"
34 #include "hw/pci/pci_bus.h"
35 #include "migration/vmstate.h"
36 #include "qapi/error.h"
37 #include "qom/qom-qobject.h"
38 #include "trace.h"
39
40 #define ACPI_PCIHP_ADDR 0xae00
41 #define ACPI_PCIHP_SIZE 0x0018
42 #define PCI_UP_BASE 0x0000
43 #define PCI_DOWN_BASE 0x0004
44 #define PCI_EJ_BASE 0x0008
45 #define PCI_RMV_BASE 0x000c
46 #define PCI_SEL_BASE 0x0010
47 #define PCI_AIDX_BASE 0x0014
48
49 typedef struct AcpiPciHpFind {
50 int bsel;
51 PCIBus *bus;
52 } AcpiPciHpFind;
53
54 static gint g_cmp_uint32(gconstpointer a, gconstpointer b, gpointer user_data)
55 {
56 return a - b;
57 }
58
59 static GSequence *pci_acpi_index_list(void)
60 {
61 static GSequence *used_acpi_index_list;
62
63 if (!used_acpi_index_list) {
64 used_acpi_index_list = g_sequence_new(NULL);
65 }
66 return used_acpi_index_list;
67 }
68
69 static int acpi_pcihp_get_bsel(PCIBus *bus)
70 {
71 Error *local_err = NULL;
72 uint64_t bsel = object_property_get_uint(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
73 &local_err);
74
75 if (local_err || bsel >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
76 if (local_err) {
77 error_free(local_err);
78 }
79 return -1;
80 } else {
81 return bsel;
82 }
83 }
84
85 /* Assign BSEL property to all buses. In the future, this can be changed
86 * to only assign to buses that support hotplug.
87 */
88 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
89 {
90 unsigned *bsel_alloc = opaque;
91 unsigned *bus_bsel;
92
93 if (qbus_is_hotpluggable(BUS(bus))) {
94 bus_bsel = g_malloc(sizeof *bus_bsel);
95
96 *bus_bsel = (*bsel_alloc)++;
97 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
98 bus_bsel, OBJ_PROP_FLAG_READ);
99 }
100
101 return bsel_alloc;
102 }
103
104 static void acpi_set_pci_info(void)
105 {
106 static bool bsel_is_set;
107 PCIBus *bus;
108 unsigned bsel_alloc = ACPI_PCIHP_BSEL_DEFAULT;
109
110 if (bsel_is_set) {
111 return;
112 }
113 bsel_is_set = true;
114
115 bus = find_i440fx(); /* TODO: Q35 support */
116 if (bus) {
117 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
118 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
119 }
120 }
121
122 static void acpi_pcihp_disable_root_bus(void)
123 {
124 static bool root_hp_disabled;
125 PCIBus *bus;
126
127 if (root_hp_disabled) {
128 return;
129 }
130
131 bus = find_i440fx();
132 if (bus) {
133 /* setting the hotplug handler to NULL makes the bus non-hotpluggable */
134 qbus_set_hotplug_handler(BUS(bus), NULL);
135 }
136 root_hp_disabled = true;
137 return;
138 }
139
140 static void acpi_pcihp_test_hotplug_bus(PCIBus *bus, void *opaque)
141 {
142 AcpiPciHpFind *find = opaque;
143 if (find->bsel == acpi_pcihp_get_bsel(bus)) {
144 find->bus = bus;
145 }
146 }
147
148 static PCIBus *acpi_pcihp_find_hotplug_bus(AcpiPciHpState *s, int bsel)
149 {
150 AcpiPciHpFind find = { .bsel = bsel, .bus = NULL };
151
152 if (bsel < 0) {
153 return NULL;
154 }
155
156 pci_for_each_bus(s->root, acpi_pcihp_test_hotplug_bus, &find);
157
158 /* Make bsel 0 eject root bus if bsel property is not set,
159 * for compatibility with non acpi setups.
160 * TODO: really needed?
161 */
162 if (!bsel && !find.bus) {
163 find.bus = s->root;
164 }
165
166 /*
167 * Check if find.bus is actually hotpluggable. If bsel is set to
168 * NULL for example on the root bus in order to make it
169 * non-hotpluggable, find.bus will match the root bus when bsel
170 * is 0. See acpi_pcihp_test_hotplug_bus() above. Since the
171 * bus is not hotpluggable however, we should not select the bus.
172 * Instead, we should set find.bus to NULL in that case. In the check
173 * below, we generalize this case for all buses, not just the root bus.
174 * The callers of this function check for a null return value and
175 * handle them appropriately.
176 */
177 if (find.bus && !qbus_is_hotpluggable(BUS(find.bus))) {
178 find.bus = NULL;
179 }
180 return find.bus;
181 }
182
183 static bool acpi_pcihp_pc_no_hotplug(AcpiPciHpState *s, PCIDevice *dev)
184 {
185 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
186 DeviceClass *dc = DEVICE_GET_CLASS(dev);
187 /*
188 * ACPI doesn't allow hotplug of bridge devices. Don't allow
189 * hot-unplug of bridge devices unless they were added by hotplug
190 * (and so, not described by acpi).
191 */
192 return (pc->is_bridge && !dev->qdev.hotplugged) || !dc->hotpluggable;
193 }
194
195 static void acpi_pcihp_eject_slot(AcpiPciHpState *s, unsigned bsel, unsigned slots)
196 {
197 HotplugHandler *hotplug_ctrl;
198 BusChild *kid, *next;
199 int slot = ctz32(slots);
200 PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
201
202 trace_acpi_pci_eject_slot(bsel, slot);
203
204 if (!bus || slot > 31) {
205 return;
206 }
207
208 /* Mark request as complete */
209 s->acpi_pcihp_pci_status[bsel].down &= ~(1U << slot);
210 s->acpi_pcihp_pci_status[bsel].up &= ~(1U << slot);
211
212 QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
213 DeviceState *qdev = kid->child;
214 PCIDevice *dev = PCI_DEVICE(qdev);
215 if (PCI_SLOT(dev->devfn) == slot) {
216 if (!acpi_pcihp_pc_no_hotplug(s, dev)) {
217 hotplug_ctrl = qdev_get_hotplug_handler(qdev);
218 hotplug_handler_unplug(hotplug_ctrl, qdev, &error_abort);
219 object_unparent(OBJECT(qdev));
220 }
221 }
222 }
223 }
224
225 static void acpi_pcihp_update_hotplug_bus(AcpiPciHpState *s, int bsel)
226 {
227 BusChild *kid, *next;
228 PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
229
230 /* Execute any pending removes during reset */
231 while (s->acpi_pcihp_pci_status[bsel].down) {
232 acpi_pcihp_eject_slot(s, bsel, s->acpi_pcihp_pci_status[bsel].down);
233 }
234
235 s->acpi_pcihp_pci_status[bsel].hotplug_enable = ~0;
236
237 if (!bus) {
238 return;
239 }
240 QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
241 DeviceState *qdev = kid->child;
242 PCIDevice *pdev = PCI_DEVICE(qdev);
243 int slot = PCI_SLOT(pdev->devfn);
244
245 if (acpi_pcihp_pc_no_hotplug(s, pdev)) {
246 s->acpi_pcihp_pci_status[bsel].hotplug_enable &= ~(1U << slot);
247 }
248 }
249 }
250
251 static void acpi_pcihp_update(AcpiPciHpState *s)
252 {
253 int i;
254
255 for (i = 0; i < ACPI_PCIHP_MAX_HOTPLUG_BUS; ++i) {
256 acpi_pcihp_update_hotplug_bus(s, i);
257 }
258 }
259
260 void acpi_pcihp_reset(AcpiPciHpState *s, bool acpihp_root_off)
261 {
262 if (acpihp_root_off) {
263 acpi_pcihp_disable_root_bus();
264 }
265 acpi_set_pci_info();
266 acpi_pcihp_update(s);
267 }
268
269 #define ONBOARD_INDEX_MAX (16 * 1024 - 1)
270
271 void acpi_pcihp_device_pre_plug_cb(HotplugHandler *hotplug_dev,
272 DeviceState *dev, Error **errp)
273 {
274 PCIDevice *pdev = PCI_DEVICE(dev);
275
276 /* Only hotplugged devices need the hotplug capability. */
277 if (dev->hotplugged &&
278 acpi_pcihp_get_bsel(pci_get_bus(PCI_DEVICE(dev))) < 0) {
279 error_setg(errp, "Unsupported bus. Bus doesn't have property '"
280 ACPI_PCIHP_PROP_BSEL "' set");
281 return;
282 }
283
284 /*
285 * capped by systemd (see: udev-builtin-net_id.c)
286 * as it's the only known user honor it to avoid users
287 * misconfigure QEMU and then wonder why acpi-index doesn't work
288 */
289 if (pdev->acpi_index > ONBOARD_INDEX_MAX) {
290 error_setg(errp, "acpi-index should be less or equal to %u",
291 ONBOARD_INDEX_MAX);
292 return;
293 }
294
295 /*
296 * make sure that acpi-index is unique across all present PCI devices
297 */
298 if (pdev->acpi_index) {
299 GSequence *used_indexes = pci_acpi_index_list();
300
301 if (g_sequence_lookup(used_indexes, GINT_TO_POINTER(pdev->acpi_index),
302 g_cmp_uint32, NULL)) {
303 error_setg(errp, "a PCI device with acpi-index = %" PRIu32
304 " already exist", pdev->acpi_index);
305 return;
306 }
307 g_sequence_insert_sorted(used_indexes,
308 GINT_TO_POINTER(pdev->acpi_index),
309 g_cmp_uint32, NULL);
310 }
311 }
312
313 void acpi_pcihp_device_plug_cb(HotplugHandler *hotplug_dev, AcpiPciHpState *s,
314 DeviceState *dev, Error **errp)
315 {
316 PCIDevice *pdev = PCI_DEVICE(dev);
317 int slot = PCI_SLOT(pdev->devfn);
318 int bsel;
319
320 /* Don't send event when device is enabled during qemu machine creation:
321 * it is present on boot, no hotplug event is necessary. We do send an
322 * event when the device is disabled later. */
323 if (!dev->hotplugged) {
324 /*
325 * Overwrite the default hotplug handler with the ACPI PCI one
326 * for cold plugged bridges only.
327 */
328 if (!s->legacy_piix &&
329 object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
330 PCIBus *sec = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
331
332 qbus_set_hotplug_handler(BUS(sec), OBJECT(hotplug_dev));
333 /* We don't have to overwrite any other hotplug handler yet */
334 assert(QLIST_EMPTY(&sec->child));
335 }
336
337 return;
338 }
339
340 bsel = acpi_pcihp_get_bsel(pci_get_bus(pdev));
341 g_assert(bsel >= 0);
342 s->acpi_pcihp_pci_status[bsel].up |= (1U << slot);
343 acpi_send_event(DEVICE(hotplug_dev), ACPI_PCI_HOTPLUG_STATUS);
344 }
345
346 void acpi_pcihp_device_unplug_cb(HotplugHandler *hotplug_dev, AcpiPciHpState *s,
347 DeviceState *dev, Error **errp)
348 {
349 PCIDevice *pdev = PCI_DEVICE(dev);
350
351 trace_acpi_pci_unplug(PCI_SLOT(PCI_DEVICE(dev)->devfn),
352 acpi_pcihp_get_bsel(pci_get_bus(PCI_DEVICE(dev))));
353
354 /*
355 * clean up acpi-index so it could reused by another device
356 */
357 if (pdev->acpi_index) {
358 GSequence *used_indexes = pci_acpi_index_list();
359
360 g_sequence_remove(g_sequence_lookup(used_indexes,
361 GINT_TO_POINTER(pdev->acpi_index),
362 g_cmp_uint32, NULL));
363 }
364
365 qdev_unrealize(dev);
366 }
367
368 void acpi_pcihp_device_unplug_request_cb(HotplugHandler *hotplug_dev,
369 AcpiPciHpState *s, DeviceState *dev,
370 Error **errp)
371 {
372 PCIDevice *pdev = PCI_DEVICE(dev);
373 int slot = PCI_SLOT(pdev->devfn);
374 int bsel = acpi_pcihp_get_bsel(pci_get_bus(pdev));
375
376 trace_acpi_pci_unplug_request(bsel, slot);
377
378 if (bsel < 0) {
379 error_setg(errp, "Unsupported bus. Bus doesn't have property '"
380 ACPI_PCIHP_PROP_BSEL "' set");
381 return;
382 }
383
384 s->acpi_pcihp_pci_status[bsel].down |= (1U << slot);
385 acpi_send_event(DEVICE(hotplug_dev), ACPI_PCI_HOTPLUG_STATUS);
386 }
387
388 static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size)
389 {
390 AcpiPciHpState *s = opaque;
391 uint32_t val = 0;
392 int bsel = s->hotplug_select;
393
394 if (bsel < 0 || bsel >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
395 return 0;
396 }
397
398 switch (addr) {
399 case PCI_UP_BASE:
400 val = s->acpi_pcihp_pci_status[bsel].up;
401 if (!s->legacy_piix) {
402 s->acpi_pcihp_pci_status[bsel].up = 0;
403 }
404 trace_acpi_pci_up_read(val);
405 break;
406 case PCI_DOWN_BASE:
407 val = s->acpi_pcihp_pci_status[bsel].down;
408 trace_acpi_pci_down_read(val);
409 break;
410 case PCI_EJ_BASE:
411 trace_acpi_pci_features_read(val);
412 break;
413 case PCI_RMV_BASE:
414 val = s->acpi_pcihp_pci_status[bsel].hotplug_enable;
415 trace_acpi_pci_rmv_read(val);
416 break;
417 case PCI_SEL_BASE:
418 val = s->hotplug_select;
419 trace_acpi_pci_sel_read(val);
420 break;
421 case PCI_AIDX_BASE:
422 val = s->acpi_index;
423 s->acpi_index = 0;
424 trace_acpi_pci_acpi_index_read(val);
425 break;
426 default:
427 break;
428 }
429
430 return val;
431 }
432
433 static void pci_write(void *opaque, hwaddr addr, uint64_t data,
434 unsigned int size)
435 {
436 int slot;
437 PCIBus *bus;
438 BusChild *kid, *next;
439 AcpiPciHpState *s = opaque;
440
441 s->acpi_index = 0;
442 switch (addr) {
443 case PCI_AIDX_BASE:
444 /*
445 * fetch acpi-index for specified slot so that follow up read from
446 * PCI_AIDX_BASE can return it to guest
447 */
448 slot = ctz32(data);
449
450 if (s->hotplug_select >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
451 break;
452 }
453
454 bus = acpi_pcihp_find_hotplug_bus(s, s->hotplug_select);
455 QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
456 Object *o = OBJECT(kid->child);
457 PCIDevice *dev = PCI_DEVICE(o);
458 if (PCI_SLOT(dev->devfn) == slot) {
459 s->acpi_index = object_property_get_uint(o, "acpi-index", NULL);
460 break;
461 }
462 }
463 trace_acpi_pci_acpi_index_write(s->hotplug_select, slot, s->acpi_index);
464 break;
465 case PCI_EJ_BASE:
466 if (s->hotplug_select >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
467 break;
468 }
469 acpi_pcihp_eject_slot(s, s->hotplug_select, data);
470 trace_acpi_pci_ej_write(addr, data);
471 break;
472 case PCI_SEL_BASE:
473 s->hotplug_select = s->legacy_piix ? ACPI_PCIHP_BSEL_DEFAULT : data;
474 trace_acpi_pci_sel_write(addr, data);
475 default:
476 break;
477 }
478 }
479
480 static const MemoryRegionOps acpi_pcihp_io_ops = {
481 .read = pci_read,
482 .write = pci_write,
483 .endianness = DEVICE_LITTLE_ENDIAN,
484 .valid = {
485 .min_access_size = 4,
486 .max_access_size = 4,
487 },
488 };
489
490 void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus,
491 MemoryRegion *address_space_io, bool bridges_enabled)
492 {
493 s->io_len = ACPI_PCIHP_SIZE;
494 s->io_base = ACPI_PCIHP_ADDR;
495
496 s->root = root_bus;
497 s->legacy_piix = !bridges_enabled;
498
499 memory_region_init_io(&s->io, owner, &acpi_pcihp_io_ops, s,
500 "acpi-pci-hotplug", s->io_len);
501 memory_region_add_subregion(address_space_io, s->io_base, &s->io);
502
503 object_property_add_uint16_ptr(owner, ACPI_PCIHP_IO_BASE_PROP, &s->io_base,
504 OBJ_PROP_FLAG_READ);
505 object_property_add_uint16_ptr(owner, ACPI_PCIHP_IO_LEN_PROP, &s->io_len,
506 OBJ_PROP_FLAG_READ);
507 }
508
509 bool vmstate_acpi_pcihp_use_acpi_index(void *opaque, int version_id)
510 {
511 AcpiPciHpState *s = opaque;
512 return s->acpi_index;
513 }
514
515 const VMStateDescription vmstate_acpi_pcihp_pci_status = {
516 .name = "acpi_pcihp_pci_status",
517 .version_id = 1,
518 .minimum_version_id = 1,
519 .fields = (VMStateField[]) {
520 VMSTATE_UINT32(up, AcpiPciHpPciStatus),
521 VMSTATE_UINT32(down, AcpiPciHpPciStatus),
522 VMSTATE_END_OF_LIST()
523 }
524 };