hw/acpi_ich9.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  */
  18 /*
  19  *  Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
  20  *                     VA Linux Systems Japan K.K.
  21  *  Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
  22  *
  23  *  This is based on acpi.c.
  24  */
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "pci.h"
  28 #include "qemu-timer.h"
  29 #include "sysemu.h"
  30 #include "acpi.h"
  31 #include "kvm.h"
  32 #include "exec-memory.h"
  33
  34 #include "ich9.h"
  35
  36 //#define DEBUG
  37
  38 #ifdef DEBUG
  39 #define ICH9_DEBUG(fmt, ...) \
  40 do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
  41 #else
  42 #define ICH9_DEBUG(fmt, ...)    do { } while (0)
  43 #endif
  44
  45 static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
  46                                      uint32_t val);
  47 static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len);
  48
  49 static void pm_update_sci(ICH9LPCPMRegs *pm)
  50 {
  51     int sci_level, pm1a_sts;
  52
  53     pm1a_sts = acpi_pm1_evt_get_sts(&pm->acpi_regs);
  54
  55     sci_level = (((pm1a_sts & pm->acpi_regs.pm1.evt.en) &
  56                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
  57                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
  58                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
  59                    ACPI_BITMASK_TIMER_ENABLE)) != 0);
  60     qemu_set_irq(pm->irq, sci_level);
  61
  62     /* schedule a timer interruption if needed */
  63     acpi_pm_tmr_update(&pm->acpi_regs,
  64                        (pm->acpi_regs.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
  65                        !(pm1a_sts & ACPI_BITMASK_TIMER_STATUS));
  66 }
  67
  68 static void ich9_pm_update_sci_fn(ACPIREGS *regs)
  69 {
  70     ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs);
  71     pm_update_sci(pm);
  72 }
  73
  74 static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
  75 {
  76     switch (addr & ICH9_PMIO_MASK) {
  77     default:
  78         break;
  79     }
  80
  81     ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
  82 }
  83
  84 static uint32_t pm_ioport_readb(void *opaque, uint32_t addr)
  85 {
  86     uint32_t val = 0;
  87
  88     switch (addr & ICH9_PMIO_MASK) {
  89     default:
  90         val = 0;
  91         break;
  92     }
  93     ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
  94     return val;
  95 }
  96
  97 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
  98 {
  99     switch (addr & ICH9_PMIO_MASK) {
 100     default:
 101         pm_ioport_write_fallback(opaque, addr, 2, val);
 102         break;
 103     }
 104     ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
 105 }
 106
 107 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 108 {
 109     uint32_t val;
 110
 111     switch (addr & ICH9_PMIO_MASK) {
 112     default:
 113         val = pm_ioport_read_fallback(opaque, addr, 2);
 114         break;
 115     }
 116     ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
 117     return val;
 118 }
 119
 120 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 121 {
 122     ICH9LPCPMRegs *pm = opaque;
 123
 124     switch (addr & ICH9_PMIO_MASK) {
 125     case ICH9_PMIO_SMI_EN:
 126         pm->smi_en = val;
 127         break;
 128     default:
 129         pm_ioport_write_fallback(opaque, addr, 4, val);
 130         break;
 131     }
 132     ICH9_DEBUG("port=0x%04x val=0x%08x\n", addr, val);
 133 }
 134
 135 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 136 {
 137     ICH9LPCPMRegs *pm = opaque;
 138     uint32_t val;
 139
 140     switch (addr & ICH9_PMIO_MASK) {
 141     case ICH9_PMIO_SMI_EN:
 142         val = pm->smi_en;
 143         break;
 144
 145     default:
 146         val = pm_ioport_read_fallback(opaque, addr, 4);
 147         break;
 148     }
 149     ICH9_DEBUG("port=0x%04x val=0x%08x\n", addr, val);
 150     return val;
 151 }
 152
 153 static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
 154                                      uint32_t val)
 155  {
 156     int subsize = (len == 4) ? 2 : 1;
 157     IOPortWriteFunc *ioport_write =
 158         (subsize == 2) ? pm_ioport_writew : pm_ioport_writeb;
 159
 160     int i;
 161
 162     for (i = 0; i < len; i += subsize) {
 163         ioport_write(opaque, addr, val);
 164         val >>= 8 * subsize;
 165     }
 166 }
 167
 168 static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len)
 169 {
 170     int subsize = (len == 4) ? 2 : 1;
 171     IOPortReadFunc *ioport_read =
 172         (subsize == 2) ? pm_ioport_readw : pm_ioport_readb;
 173
 174     uint32_t val;
 175     int i;
 176
 177     val = 0;
 178     for (i = 0; i < len; i += subsize) {
 179         val <<= 8 * subsize;
 180         val |= ioport_read(opaque, addr);
 181     }
 182
 183     return val;
 184 }
 185
 186 static const MemoryRegionOps pm_io_ops = {
 187     .old_portio = (MemoryRegionPortio[]) {
 188         { .offset = 0, .len = ICH9_PMIO_SIZE, .size = 1,
 189           .read = pm_ioport_readb, .write = pm_ioport_writeb },
 190         { .offset = 0, .len = ICH9_PMIO_SIZE, .size = 2,
 191           .read = pm_ioport_readw, .write = pm_ioport_writew },
 192         { .offset = 0, .len = ICH9_PMIO_SIZE, .size = 4,
 193           .read = pm_ioport_readl, .write = pm_ioport_writel },
 194         PORTIO_END_OF_LIST(),
 195     },
 196     .valid.min_access_size = 1,
 197     .valid.max_access_size = 4,
 198     .impl.min_access_size = 1,
 199     .impl.max_access_size = 4,
 200     .endianness = DEVICE_LITTLE_ENDIAN,
 201 };
 202
 203 static uint64_t ich9_gpe_readb(void *opaque, hwaddr addr, unsigned width)
 204 {
 205     ICH9LPCPMRegs *pm = opaque;
 206     return acpi_gpe_ioport_readb(&pm->acpi_regs, addr);
 207 }
 208
 209 static void ich9_gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
 210                             unsigned width)
 211 {
 212     ICH9LPCPMRegs *pm = opaque;
 213     acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
 214 }
 215
 216 static const MemoryRegionOps ich9_gpe_ops = {
 217     .read = ich9_gpe_readb,
 218     .write = ich9_gpe_writeb,
 219     .valid.min_access_size = 1,
 220     .valid.max_access_size = 4,
 221     .impl.min_access_size = 1,
 222     .impl.max_access_size = 1,
 223     .endianness = DEVICE_LITTLE_ENDIAN,
 224 };
 225
 226 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base)
 227 {
 228     ICH9_DEBUG("to 0x%x\n", pm_io_base);
 229
 230     assert((pm_io_base & ICH9_PMIO_MASK) == 0);
 231
 232     pm->pm_io_base = pm_io_base;
 233     memory_region_transaction_begin();
 234     memory_region_set_enabled(&pm->io, pm->pm_io_base != 0);
 235     memory_region_set_address(&pm->io, pm->pm_io_base);
 236     memory_region_transaction_commit();
 237 }
 238
 239 static int ich9_pm_post_load(void *opaque, int version_id)
 240 {
 241     ICH9LPCPMRegs *pm = opaque;
 242     uint32_t pm_io_base = pm->pm_io_base;
 243     pm->pm_io_base = 0;
 244     ich9_pm_iospace_update(pm, pm_io_base);
 245     return 0;
 246 }
 247
 248 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 249  {                                                                   \
 250      .name       = (stringify(_field)),                              \
 251      .version_id = 0,                                                \
 252      .num        = ICH9_PMIO_GPE0_LEN,                               \
 253      .info       = &vmstate_info_uint8,                              \
 254      .size       = sizeof(uint8_t),                                  \
 255      .flags      = VMS_ARRAY | VMS_POINTER,                          \
 256      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 257  }
 258
 259 const VMStateDescription vmstate_ich9_pm = {
 260     .name = "ich9_pm",
 261     .version_id = 1,
 262     .minimum_version_id = 1,
 263     .minimum_version_id_old = 1,
 264     .post_load = ich9_pm_post_load,
 265     .fields = (VMStateField[]) {
 266         VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs),
 267         VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs),
 268         VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs),
 269         VMSTATE_TIMER(acpi_regs.tmr.timer, ICH9LPCPMRegs),
 270         VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs),
 271         VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs),
 272         VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs),
 273         VMSTATE_UINT32(smi_en, ICH9LPCPMRegs),
 274         VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs),
 275         VMSTATE_END_OF_LIST()
 276     }
 277 };
 278
 279 static void pm_reset(void *opaque)
 280 {
 281     ICH9LPCPMRegs *pm = opaque;
 282     ich9_pm_iospace_update(pm, 0);
 283
 284     acpi_pm1_evt_reset(&pm->acpi_regs);
 285     acpi_pm1_cnt_reset(&pm->acpi_regs);
 286     acpi_pm_tmr_reset(&pm->acpi_regs);
 287     acpi_gpe_reset(&pm->acpi_regs);
 288
 289     if (kvm_enabled()) {
 290         /* Mark SMM as already inited to prevent SMM from running. KVM does not
 291          * support SMM mode. */
 292         pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN;
 293     }
 294
 295     pm_update_sci(pm);
 296 }
 297
 298 static void pm_powerdown_req(Notifier *n, void *opaque)
 299 {
 300     ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, powerdown_notifier);
 301
 302     acpi_pm1_evt_power_down(&pm->acpi_regs);
 303 }
 304
 305 void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
 306 {
 307     memory_region_init_io(&pm->io, &pm_io_ops, pm, "ich9-pm", ICH9_PMIO_SIZE);
 308     memory_region_set_enabled(&pm->io, false);
 309     memory_region_add_subregion(get_system_io(), 0, &pm->io);
 310
 311     acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
 312     acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
 313     acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io);
 314
 315     acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
 316     acpi_gpe_blk(&pm->acpi_regs, 0);
 317     memory_region_init_io(&pm->io_gpe, &ich9_gpe_ops, pm, "apci-gpe0",
 318                           ICH9_PMIO_GPE0_LEN);
 319     memory_region_add_subregion(&pm->io, ICH9_PMIO_GPE0_STS, &pm->io_gpe);
 320
 321     pm->irq = sci_irq;
 322     qemu_register_reset(pm_reset, pm);
 323     pm->powerdown_notifier.notify = pm_powerdown_req;
 324     qemu_register_powerdown_notifier(&pm->powerdown_notifier);
 325 }