hw/acpi_ich9.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  */
  18 /*
  19  *  Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
  20  *                     VA Linux Systems Japan K.K.
  21  *  Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
  22  *
  23  *  This is based on acpi.c.
  24  */
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "pci.h"
  28 #include "qemu-timer.h"
  29 #include "sysemu.h"
  30 #include "acpi.h"
  31
  32 #include "ich9.h"
  33
  34 //#define DEBUG
  35
  36 #ifdef DEBUG
  37 #define ICH9_DEBUG(fmt, ...) \
  38 do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
  39 #else
  40 #define ICH9_DEBUG(fmt, ...)    do { } while (0)
  41 #endif
  42
  43 static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
  44                                      uint32_t val);
  45 static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len);
  46
  47 static void pm_update_sci(ICH9LPCPMRegs *pm)
  48 {
  49     int sci_level, pm1a_sts;
  50
  51     pm1a_sts = acpi_pm1_evt_get_sts(&pm->acpi_regs);
  52
  53     sci_level = (((pm1a_sts & pm->acpi_regs.pm1.evt.en) &
  54                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
  55                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
  56                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
  57                    ACPI_BITMASK_TIMER_ENABLE)) != 0);
  58     qemu_set_irq(pm->irq, sci_level);
  59
  60     /* schedule a timer interruption if needed */
  61     acpi_pm_tmr_update(&pm->acpi_regs,
  62                        (pm->acpi_regs.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
  63                        !(pm1a_sts & ACPI_BITMASK_TIMER_STATUS));
  64 }
  65
  66 static void ich9_pm_update_sci_fn(ACPIREGS *regs)
  67 {
  68     ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs);
  69     pm_update_sci(pm);
  70 }
  71
  72 static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
  73 {
  74     ICH9LPCPMRegs *pm = opaque;
  75
  76     switch (addr & ICH9_PMIO_MASK) {
  77     case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
  78         acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
  79         break;
  80     default:
  81         break;
  82     }
  83
  84     ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
  85 }
  86
  87 static uint32_t pm_ioport_readb(void *opaque, uint32_t addr)
  88 {
  89     ICH9LPCPMRegs *pm = opaque;
  90     uint32_t val = 0;
  91
  92     switch (addr & ICH9_PMIO_MASK) {
  93     case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
  94         val = acpi_gpe_ioport_readb(&pm->acpi_regs, addr);
  95         break;
  96     default:
  97         val = 0;
  98         break;
  99     }
 100     ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
 101     return val;
 102 }
 103
 104 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 105 {
 106     ICH9LPCPMRegs *pm = opaque;
 107
 108     switch (addr & ICH9_PMIO_MASK) {
 109     case ICH9_PMIO_PM1_STS:
 110         acpi_pm1_evt_write_sts(&pm->acpi_regs, val);
 111         pm_update_sci(pm);
 112         break;
 113     case ICH9_PMIO_PM1_EN:
 114         pm->acpi_regs.pm1.evt.en = val;
 115         pm_update_sci(pm);
 116         break;
 117     case ICH9_PMIO_PM1_CNT:
 118         acpi_pm1_cnt_write(&pm->acpi_regs, val, 0);
 119         break;
 120     default:
 121         pm_ioport_write_fallback(opaque, addr, 2, val);
 122         break;
 123     }
 124     ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
 125 }
 126
 127 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 128 {
 129     ICH9LPCPMRegs *pm = opaque;
 130     uint32_t val;
 131
 132     switch (addr & ICH9_PMIO_MASK) {
 133     case ICH9_PMIO_PM1_STS:
 134         val = acpi_pm1_evt_get_sts(&pm->acpi_regs);
 135         break;
 136     case ICH9_PMIO_PM1_EN:
 137         val = pm->acpi_regs.pm1.evt.en;
 138         break;
 139     case ICH9_PMIO_PM1_CNT:
 140         val = pm->acpi_regs.pm1.cnt.cnt;
 141         break;
 142     default:
 143         val = pm_ioport_read_fallback(opaque, addr, 2);
 144         break;
 145     }
 146     ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
 147     return val;
 148 }
 149
 150 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 151 {
 152     ICH9LPCPMRegs *pm = opaque;
 153
 154     switch (addr & ICH9_PMIO_MASK) {
 155     case ICH9_PMIO_SMI_EN:
 156         pm->smi_en = val;
 157         break;
 158     default:
 159         pm_ioport_write_fallback(opaque, addr, 4, val);
 160         break;
 161     }
 162     ICH9_DEBUG("port=0x%04x val=0x%08x\n", addr, val);
 163 }
 164
 165 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 166 {
 167     ICH9LPCPMRegs *pm = opaque;
 168     uint32_t val;
 169
 170     switch (addr & ICH9_PMIO_MASK) {
 171     case ICH9_PMIO_PM1_TMR:
 172         val = acpi_pm_tmr_get(&pm->acpi_regs);
 173         break;
 174     case ICH9_PMIO_SMI_EN:
 175         val = pm->smi_en;
 176         break;
 177
 178     default:
 179         val = pm_ioport_read_fallback(opaque, addr, 4);
 180         break;
 181     }
 182     ICH9_DEBUG("port=0x%04x val=0x%08x\n", addr, val);
 183     return val;
 184 }
 185
 186 static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
 187                                      uint32_t val)
 188  {
 189     int subsize = (len == 4) ? 2 : 1;
 190     IOPortWriteFunc *ioport_write =
 191         (subsize == 2) ? pm_ioport_writew : pm_ioport_writeb;
 192
 193     int i;
 194
 195     for (i = 0; i < len; i += subsize) {
 196         ioport_write(opaque, addr, val);
 197         val >>= 8 * subsize;
 198     }
 199 }
 200
 201 static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len)
 202 {
 203     int subsize = (len == 4) ? 2 : 1;
 204     IOPortReadFunc *ioport_read =
 205         (subsize == 2) ? pm_ioport_readw : pm_ioport_readb;
 206
 207     uint32_t val;
 208     int i;
 209
 210     val = 0;
 211     for (i = 0; i < len; i += subsize) {
 212         val <<= 8 * subsize;
 213         val |= ioport_read(opaque, addr);
 214     }
 215
 216     return val;
 217 }
 218
 219 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base)
 220 {
 221     ICH9_DEBUG("to 0x%x\n", pm_io_base);
 222
 223     assert((pm_io_base & ICH9_PMIO_MASK) == 0);
 224
 225     if (pm->pm_io_base != 0) {
 226         isa_unassign_ioport(pm->pm_io_base, ICH9_PMIO_SIZE);
 227     }
 228
 229     /* don't map at 0 */
 230     if (pm_io_base == 0) {
 231         return;
 232     }
 233
 234     register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 1, pm_ioport_writeb, pm);
 235     register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 1, pm_ioport_readb, pm);
 236     register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 2, pm_ioport_writew, pm);
 237     register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 2, pm_ioport_readw, pm);
 238     register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 4, pm_ioport_writel, pm);
 239     register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 4, pm_ioport_readl, pm);
 240
 241     pm->pm_io_base = pm_io_base;
 242     acpi_gpe_blk(&pm->acpi_regs, pm_io_base + ICH9_PMIO_GPE0_STS);
 243 }
 244
 245 static int ich9_pm_post_load(void *opaque, int version_id)
 246 {
 247     ICH9LPCPMRegs *pm = opaque;
 248     uint32_t pm_io_base = pm->pm_io_base;
 249     pm->pm_io_base = 0;
 250     ich9_pm_iospace_update(pm, pm_io_base);
 251     return 0;
 252 }
 253
 254 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 255  {                                                                   \
 256      .name       = (stringify(_field)),                              \
 257      .version_id = 0,                                                \
 258      .num        = ICH9_PMIO_GPE0_LEN,                               \
 259      .info       = &vmstate_info_uint8,                              \
 260      .size       = sizeof(uint8_t),                                  \
 261      .flags      = VMS_ARRAY | VMS_POINTER,                          \
 262      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 263  }
 264
 265 const VMStateDescription vmstate_ich9_pm = {
 266     .name = "ich9_pm",
 267     .version_id = 1,
 268     .minimum_version_id = 1,
 269     .minimum_version_id_old = 1,
 270     .post_load = ich9_pm_post_load,
 271     .fields = (VMStateField[]) {
 272         VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs),
 273         VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs),
 274         VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs),
 275         VMSTATE_TIMER(acpi_regs.tmr.timer, ICH9LPCPMRegs),
 276         VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs),
 277         VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs),
 278         VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs),
 279         VMSTATE_UINT32(smi_en, ICH9LPCPMRegs),
 280         VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs),
 281         VMSTATE_END_OF_LIST()
 282     }
 283 };
 284
 285 static void pm_reset(void *opaque)
 286 {
 287     ICH9LPCPMRegs *pm = opaque;
 288     ich9_pm_iospace_update(pm, 0);
 289
 290     acpi_pm1_evt_reset(&pm->acpi_regs);
 291     acpi_pm1_cnt_reset(&pm->acpi_regs);
 292     acpi_pm_tmr_reset(&pm->acpi_regs);
 293     acpi_gpe_reset(&pm->acpi_regs);
 294
 295     pm_update_sci(pm);
 296 }
 297
 298 static void pm_powerdown_req(Notifier *n, void *opaque)
 299 {
 300     ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, powerdown_notifier);
 301
 302     acpi_pm1_evt_power_down(&pm->acpi_regs);
 303 }
 304
 305 void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
 306 {
 307     acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn);
 308     acpi_pm1_cnt_init(&pm->acpi_regs);
 309     acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
 310
 311     pm->irq = sci_irq;
 312     qemu_register_reset(pm_reset, pm);
 313     pm->powerdown_notifier.notify = pm_powerdown_req;
 314     qemu_register_powerdown_notifier(&pm->powerdown_notifier);
 315 }