hw/acpi_piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  */
  18 #include "hw.h"
  19 #include "pc.h"
  20 #include "apm.h"
  21 #include "pm_smbus.h"
  22 #include "pci.h"
  23 #include "sysemu.h"
  24 #include "i2c.h"
  25 #include "smbus.h"
  26 #include "acpi.h"
  27
  28 //#define DEBUG
  29
  30 #define ACPI_DBG_IO_ADDR  0xb044
  31
  32 typedef struct PIIX4PMState {
  33     PCIDevice dev;
  34     uint16_t pmsts;
  35     uint16_t pmen;
  36     uint16_t pmcntrl;
  37
  38     APMState apm;
  39
  40     QEMUTimer *tmr_timer;
  41     int64_t tmr_overflow_time;
  42
  43     PMSMBus smb;
  44     uint32_t smb_io_base;
  45
  46     qemu_irq irq;
  47     qemu_irq cmos_s3;
  48     qemu_irq smi_irq;
  49     int kvm_enabled;
  50 } PIIX4PMState;
  51
  52 #define ACPI_ENABLE 0xf1
  53 #define ACPI_DISABLE 0xf0
  54
  55 static PIIX4PMState *pm_state;
  56
  57 static uint32_t get_pmtmr(PIIX4PMState *s)
  58 {
  59     uint32_t d;
  60     d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
  61     return d & 0xffffff;
  62 }
  63
  64 static int get_pmsts(PIIX4PMState *s)
  65 {
  66     int64_t d;
  67
  68     d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
  69                  get_ticks_per_sec());
  70     if (d >= s->tmr_overflow_time)
  71         s->pmsts |= ACPI_BITMASK_TIMER_STATUS;
  72     return s->pmsts;
  73 }
  74
  75 static void pm_update_sci(PIIX4PMState *s)
  76 {
  77     int sci_level, pmsts;
  78     int64_t expire_time;
  79
  80     pmsts = get_pmsts(s);
  81     sci_level = (((pmsts & s->pmen) &
  82                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
  83                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
  84                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
  85                    ACPI_BITMASK_TIMER_ENABLE)) != 0);
  86     qemu_set_irq(s->irq, sci_level);
  87     /* schedule a timer interruption if needed */
  88     if ((s->pmen & ACPI_BITMASK_TIMER_ENABLE) &&
  89         !(pmsts & ACPI_BITMASK_TIMER_STATUS)) {
  90         expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(),
  91                                PM_TIMER_FREQUENCY);
  92         qemu_mod_timer(s->tmr_timer, expire_time);
  93     } else {
  94         qemu_del_timer(s->tmr_timer);
  95     }
  96 }
  97
  98 static void pm_tmr_timer(void *opaque)
  99 {
 100     PIIX4PMState *s = opaque;
 101     pm_update_sci(s);
 102 }
 103
 104 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 105 {
 106     PIIX4PMState *s = opaque;
 107     addr &= 0x3f;
 108     switch(addr) {
 109     case 0x00:
 110         {
 111             int64_t d;
 112             int pmsts;
 113             pmsts = get_pmsts(s);
 114             if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) {
 115                 /* if TMRSTS is reset, then compute the new overflow time */
 116                 d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
 117                              get_ticks_per_sec());
 118                 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
 119             }
 120             s->pmsts &= ~val;
 121             pm_update_sci(s);
 122         }
 123         break;
 124     case 0x02:
 125         s->pmen = val;
 126         pm_update_sci(s);
 127         break;
 128     case 0x04:
 129         {
 130             int sus_typ;
 131             s->pmcntrl = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
 132             if (val & ACPI_BITMASK_SLEEP_ENABLE) {
 133                 /* change suspend type */
 134                 sus_typ = (val >> 10) & 7;
 135                 switch(sus_typ) {
 136                 case 0: /* soft power off */
 137                     qemu_system_shutdown_request();
 138                     break;
 139                 case 1:
 140                     /* ACPI_BITMASK_WAKE_STATUS should be set on resume.
 141                        Pretend that resume was caused by power button */
 142                     s->pmsts |= (ACPI_BITMASK_WAKE_STATUS |
 143                                  ACPI_BITMASK_POWER_BUTTON_STATUS);
 144                     qemu_system_reset_request();
 145                     if (s->cmos_s3) {
 146                         qemu_irq_raise(s->cmos_s3);
 147                     }
 148                 default:
 149                     break;
 150                 }
 151             }
 152         }
 153         break;
 154     default:
 155         break;
 156     }
 157 #ifdef DEBUG
 158     printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
 159 #endif
 160 }
 161
 162 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 163 {
 164     PIIX4PMState *s = opaque;
 165     uint32_t val;
 166
 167     addr &= 0x3f;
 168     switch(addr) {
 169     case 0x00:
 170         val = get_pmsts(s);
 171         break;
 172     case 0x02:
 173         val = s->pmen;
 174         break;
 175     case 0x04:
 176         val = s->pmcntrl;
 177         break;
 178     default:
 179         val = 0;
 180         break;
 181     }
 182 #ifdef DEBUG
 183     printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
 184 #endif
 185     return val;
 186 }
 187
 188 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 189 {
 190     //    PIIX4PMState *s = opaque;
 191 #ifdef DEBUG
 192     addr &= 0x3f;
 193     printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
 194 #endif
 195 }
 196
 197 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 198 {
 199     PIIX4PMState *s = opaque;
 200     uint32_t val;
 201
 202     addr &= 0x3f;
 203     switch(addr) {
 204     case 0x08:
 205         val = get_pmtmr(s);
 206         break;
 207     default:
 208         val = 0;
 209         break;
 210     }
 211 #ifdef DEBUG
 212     printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
 213 #endif
 214     return val;
 215 }
 216
 217 static void apm_ctrl_changed(uint32_t val, void *arg)
 218 {
 219     PIIX4PMState *s = arg;
 220
 221     /* ACPI specs 3.0, 4.7.2.5 */
 222     if (val == ACPI_ENABLE) {
 223         s->pmcntrl |= ACPI_BITMASK_SCI_ENABLE;
 224     } else if (val == ACPI_DISABLE) {
 225         s->pmcntrl &= ~ACPI_BITMASK_SCI_ENABLE;
 226     }
 227
 228     if (s->dev.config[0x5b] & (1 << 1)) {
 229         if (s->smi_irq) {
 230             qemu_irq_raise(s->smi_irq);
 231         }
 232     }
 233 }
 234
 235 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 236 {
 237 #if defined(DEBUG)
 238     printf("ACPI: DBG: 0x%08x\n", val);
 239 #endif
 240 }
 241
 242 static void pm_io_space_update(PIIX4PMState *s)
 243 {
 244     uint32_t pm_io_base;
 245
 246     if (s->dev.config[0x80] & 1) {
 247         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 248         pm_io_base &= 0xffc0;
 249
 250         /* XXX: need to improve memory and ioport allocation */
 251 #if defined(DEBUG)
 252         printf("PM: mapping to 0x%x\n", pm_io_base);
 253 #endif
 254         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 255         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 256         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 257         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 258     }
 259 }
 260
 261 static void pm_write_config(PCIDevice *d,
 262                             uint32_t address, uint32_t val, int len)
 263 {
 264     pci_default_write_config(d, address, val, len);
 265     if (range_covers_byte(address, len, 0x80))
 266         pm_io_space_update((PIIX4PMState *)d);
 267 }
 268
 269 static int vmstate_acpi_post_load(void *opaque, int version_id)
 270 {
 271     PIIX4PMState *s = opaque;
 272
 273     pm_io_space_update(s);
 274     return 0;
 275 }
 276
 277 static const VMStateDescription vmstate_acpi = {
 278     .name = "piix4_pm",
 279     .version_id = 1,
 280     .minimum_version_id = 1,
 281     .minimum_version_id_old = 1,
 282     .post_load = vmstate_acpi_post_load,
 283     .fields      = (VMStateField []) {
 284         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
 285         VMSTATE_UINT16(pmsts, PIIX4PMState),
 286         VMSTATE_UINT16(pmen, PIIX4PMState),
 287         VMSTATE_UINT16(pmcntrl, PIIX4PMState),
 288         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 289         VMSTATE_TIMER(tmr_timer, PIIX4PMState),
 290         VMSTATE_INT64(tmr_overflow_time, PIIX4PMState),
 291         VMSTATE_END_OF_LIST()
 292     }
 293 };
 294
 295 static void piix4_reset(void *opaque)
 296 {
 297     PIIX4PMState *s = opaque;
 298     uint8_t *pci_conf = s->dev.config;
 299
 300     pci_conf[0x58] = 0;
 301     pci_conf[0x59] = 0;
 302     pci_conf[0x5a] = 0;
 303     pci_conf[0x5b] = 0;
 304
 305     if (s->kvm_enabled) {
 306         /* Mark SMM as already inited (until KVM supports SMM). */
 307         pci_conf[0x5B] = 0x02;
 308     }
 309 }
 310
 311 static void piix4_powerdown(void *opaque, int irq, int power_failing)
 312 {
 313     PIIX4PMState *s = opaque;
 314
 315     if (!s) {
 316         qemu_system_shutdown_request();
 317     } else if (s->pmen & ACPI_BITMASK_POWER_BUTTON_ENABLE) {
 318         s->pmsts |= ACPI_BITMASK_POWER_BUTTON_STATUS;
 319         pm_update_sci(s);
 320     }
 321 }
 322
 323 static int piix4_pm_initfn(PCIDevice *dev)
 324 {
 325     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
 326     uint8_t *pci_conf;
 327
 328     pm_state = s;
 329     pci_conf = s->dev.config;
 330     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 331     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
 332     pci_conf[0x06] = 0x80;
 333     pci_conf[0x07] = 0x02;
 334     pci_conf[0x08] = 0x03; // revision number
 335     pci_conf[0x09] = 0x00;
 336     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
 337     pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 338     pci_conf[0x3d] = 0x01; // interrupt pin 1
 339
 340     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 341
 342     /* APM */
 343     apm_init(&s->apm, apm_ctrl_changed, s);
 344
 345     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 346
 347     if (s->kvm_enabled) {
 348         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 349          * support SMM mode. */
 350         pci_conf[0x5B] = 0x02;
 351     }
 352
 353     /* XXX: which specification is used ? The i82731AB has different
 354        mappings */
 355     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 356     pci_conf[0x63] = 0x60;
 357     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 358         (serial_hds[1] != NULL ? 0x90 : 0);
 359
 360     pci_conf[0x90] = s->smb_io_base | 1;
 361     pci_conf[0x91] = s->smb_io_base >> 8;
 362     pci_conf[0xd2] = 0x09;
 363     register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
 364     register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
 365
 366     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
 367
 368     qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
 369
 370     pm_smbus_init(&s->dev.qdev, &s->smb);
 371     qemu_register_reset(piix4_reset, s);
 372
 373     return 0;
 374 }
 375
 376 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 377                        qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
 378                        int kvm_enabled)
 379 {
 380     PCIDevice *dev;
 381     PIIX4PMState *s;
 382
 383     dev = pci_create(bus, devfn, "PIIX4_PM");
 384     qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
 385
 386     s = DO_UPCAST(PIIX4PMState, dev, dev);
 387     s->irq = sci_irq;
 388     s->cmos_s3 = cmos_s3;
 389     s->smi_irq = smi_irq;
 390     s->kvm_enabled = kvm_enabled;
 391
 392     qdev_init_nofail(&dev->qdev);
 393
 394     return s->smb.smbus;
 395 }
 396
 397 static PCIDeviceInfo piix4_pm_info = {
 398     .qdev.name          = "PIIX4_PM",
 399     .qdev.desc          = "PM",
 400     .qdev.size          = sizeof(PIIX4PMState),
 401     .qdev.vmsd          = &vmstate_acpi,
 402     .init               = piix4_pm_initfn,
 403     .config_write       = pm_write_config,
 404     .qdev.props         = (Property[]) {
 405         DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 406         DEFINE_PROP_END_OF_LIST(),
 407     }
 408 };
 409
 410 static void piix4_pm_register(void)
 411 {
 412     pci_qdev_register(&piix4_pm_info);
 413 }
 414
 415 device_init(piix4_pm_register);
 416
 417 #define GPE_BASE 0xafe0
 418 #define PCI_BASE 0xae00
 419 #define PCI_EJ_BASE 0xae08
 420
 421 struct gpe_regs {
 422     uint16_t sts; /* status */
 423     uint16_t en;  /* enabled */
 424 };
 425
 426 struct pci_status {
 427     uint32_t up;
 428     uint32_t down;
 429 };
 430
 431 static struct gpe_regs gpe;
 432 static struct pci_status pci0_status;
 433
 434 static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
 435 {
 436     if (addr & 1)
 437         return (val >> 8) & 0xff;
 438     return val & 0xff;
 439 }
 440
 441 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 442 {
 443     uint32_t val = 0;
 444     struct gpe_regs *g = opaque;
 445     switch (addr) {
 446         case GPE_BASE:
 447         case GPE_BASE + 1:
 448             val = gpe_read_val(g->sts, addr);
 449             break;
 450         case GPE_BASE + 2:
 451         case GPE_BASE + 3:
 452             val = gpe_read_val(g->en, addr);
 453             break;
 454         default:
 455             break;
 456     }
 457
 458 #if defined(DEBUG)
 459     printf("gpe read %x == %x\n", addr, val);
 460 #endif
 461     return val;
 462 }
 463
 464 static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
 465 {
 466     if (addr & 1)
 467         *cur = (*cur & 0xff) | (val << 8);
 468     else
 469         *cur = (*cur & 0xff00) | (val & 0xff);
 470 }
 471
 472 static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
 473 {
 474     uint16_t x1, x0 = val & 0xff;
 475     int shift = (addr & 1) ? 8 : 0;
 476
 477     x1 = (*cur >> shift) & 0xff;
 478
 479     x1 = x1 & ~x0;
 480
 481     *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
 482 }
 483
 484 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 485 {
 486     struct gpe_regs *g = opaque;
 487     switch (addr) {
 488         case GPE_BASE:
 489         case GPE_BASE + 1:
 490             gpe_reset_val(&g->sts, addr, val);
 491             break;
 492         case GPE_BASE + 2:
 493         case GPE_BASE + 3:
 494             gpe_write_val(&g->en, addr, val);
 495             break;
 496         default:
 497             break;
 498    }
 499
 500 #if defined(DEBUG)
 501     printf("gpe write %x <== %d\n", addr, val);
 502 #endif
 503 }
 504
 505 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 506 {
 507     uint32_t val = 0;
 508     struct pci_status *g = opaque;
 509     switch (addr) {
 510         case PCI_BASE:
 511             val = g->up;
 512             break;
 513         case PCI_BASE + 4:
 514             val = g->down;
 515             break;
 516         default:
 517             break;
 518     }
 519
 520 #if defined(DEBUG)
 521     printf("pcihotplug read %x == %x\n", addr, val);
 522 #endif
 523     return val;
 524 }
 525
 526 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 527 {
 528     struct pci_status *g = opaque;
 529     switch (addr) {
 530         case PCI_BASE:
 531             g->up = val;
 532             break;
 533         case PCI_BASE + 4:
 534             g->down = val;
 535             break;
 536    }
 537
 538 #if defined(DEBUG)
 539     printf("pcihotplug write %x <== %d\n", addr, val);
 540 #endif
 541 }
 542
 543 static uint32_t pciej_read(void *opaque, uint32_t addr)
 544 {
 545 #if defined(DEBUG)
 546     printf("pciej read %x\n", addr);
 547 #endif
 548     return 0;
 549 }
 550
 551 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 552 {
 553     BusState *bus = opaque;
 554     DeviceState *qdev, *next;
 555     PCIDevice *dev;
 556     int slot = ffs(val) - 1;
 557
 558     QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 559         dev = DO_UPCAST(PCIDevice, qdev, qdev);
 560         if (PCI_SLOT(dev->devfn) == slot) {
 561             qdev_free(qdev);
 562         }
 563     }
 564
 565
 566 #if defined(DEBUG)
 567     printf("pciej write %x <== %d\n", addr, val);
 568 #endif
 569 }
 570
 571 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, int state);
 572
 573 void piix4_acpi_system_hot_add_init(PCIBus *bus)
 574 {
 575     register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe);
 576     register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, &gpe);
 577
 578     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status);
 579     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, &pci0_status);
 580
 581     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
 582     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
 583
 584     pci_bus_hotplug(bus, piix4_device_hotplug, NULL);
 585 }
 586
 587 static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 588 {
 589     g->sts |= 2;
 590     p->up |= (1 << slot);
 591 }
 592
 593 static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 594 {
 595     g->sts |= 2;
 596     p->down |= (1 << slot);
 597 }
 598
 599 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, int state)
 600 {
 601     int slot = PCI_SLOT(dev->devfn);
 602
 603     pci0_status.up = 0;
 604     pci0_status.down = 0;
 605     if (state)
 606         enable_device(&pci0_status, &gpe, slot);
 607     else
 608         disable_device(&pci0_status, &gpe, slot);
 609     if (gpe.en & 2) {
 610         qemu_set_irq(pm_state->irq, 1);
 611         qemu_set_irq(pm_state->irq, 0);
 612     }
 613     return 0;
 614 }