4 * Copyright (c) 2006 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License version 2 as published by the Free Software Foundation.
10 * This library is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with this library; if not, see <http://www.gnu.org/licenses/>
18 * Contributions after 2012-01-13 are licensed under the terms of the
19 * GNU GPL, version 2 or (at your option) any later version.
35 # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
37 # define PIIX4_DPRINTF(format, ...) do { } while (0)
40 #define ACPI_DBG_IO_ADDR 0xb044
42 #define GPE_BASE 0xafe0
44 #define PCI_UP_BASE 0xae00
45 #define PCI_DOWN_BASE 0xae04
46 #define PCI_EJ_BASE 0xae08
47 #define PCI_RMV_BASE 0xae0c
49 #define PIIX4_PCI_HOTPLUG_STATUS 2
52 uint32_t up
; /* deprecated, maintained for migration compatibility */
56 typedef struct PIIX4PMState
{
69 Notifier machine_ready
;
70 Notifier powerdown_notifier
;
73 struct pci_status pci0_status
;
74 uint32_t pci0_hotplug_enable
;
75 uint32_t pci0_slot_device_present
;
82 static void piix4_acpi_system_hot_add_init(PCIBus
*bus
, PIIX4PMState
*s
);
84 #define ACPI_ENABLE 0xf1
85 #define ACPI_DISABLE 0xf0
87 static void pm_update_sci(PIIX4PMState
*s
)
91 pmsts
= acpi_pm1_evt_get_sts(&s
->ar
);
92 sci_level
= (((pmsts
& s
->ar
.pm1
.evt
.en
) &
93 (ACPI_BITMASK_RT_CLOCK_ENABLE
|
94 ACPI_BITMASK_POWER_BUTTON_ENABLE
|
95 ACPI_BITMASK_GLOBAL_LOCK_ENABLE
|
96 ACPI_BITMASK_TIMER_ENABLE
)) != 0) ||
97 (((s
->ar
.gpe
.sts
[0] & s
->ar
.gpe
.en
[0])
98 & PIIX4_PCI_HOTPLUG_STATUS
) != 0);
100 qemu_set_irq(s
->irq
, sci_level
);
101 /* schedule a timer interruption if needed */
102 acpi_pm_tmr_update(&s
->ar
, (s
->ar
.pm1
.evt
.en
& ACPI_BITMASK_TIMER_ENABLE
) &&
103 !(pmsts
& ACPI_BITMASK_TIMER_STATUS
));
106 static void pm_tmr_timer(ACPIREGS
*ar
)
108 PIIX4PMState
*s
= container_of(ar
, PIIX4PMState
, ar
);
112 static void pm_ioport_write(IORange
*ioport
, uint64_t addr
, unsigned width
,
115 PIIX4PMState
*s
= container_of(ioport
, PIIX4PMState
, ioport
);
118 PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
119 (unsigned)addr
, width
, (unsigned)val
);
124 acpi_pm1_evt_write_sts(&s
->ar
, val
);
128 acpi_pm1_evt_write_en(&s
->ar
, val
);
132 acpi_pm1_cnt_write(&s
->ar
, val
, s
->s4_val
);
137 PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr
,
141 static void pm_ioport_read(IORange
*ioport
, uint64_t addr
, unsigned width
,
144 PIIX4PMState
*s
= container_of(ioport
, PIIX4PMState
, ioport
);
149 val
= acpi_pm1_evt_get_sts(&s
->ar
);
152 val
= s
->ar
.pm1
.evt
.en
;
155 val
= s
->ar
.pm1
.cnt
.cnt
;
158 val
= acpi_pm_tmr_get(&s
->ar
);
164 PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr
, val
);
168 static const IORangeOps pm_iorange_ops
= {
169 .read
= pm_ioport_read
,
170 .write
= pm_ioport_write
,
173 static void apm_ctrl_changed(uint32_t val
, void *arg
)
175 PIIX4PMState
*s
= arg
;
177 /* ACPI specs 3.0, 4.7.2.5 */
178 acpi_pm1_cnt_update(&s
->ar
, val
== ACPI_ENABLE
, val
== ACPI_DISABLE
);
180 if (s
->dev
.config
[0x5b] & (1 << 1)) {
182 qemu_irq_raise(s
->smi_irq
);
187 static void acpi_dbg_writel(void *opaque
, uint32_t addr
, uint32_t val
)
189 PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val
);
192 static void pm_io_space_update(PIIX4PMState
*s
)
196 if (s
->dev
.config
[0x80] & 1) {
197 pm_io_base
= le32_to_cpu(*(uint32_t *)(s
->dev
.config
+ 0x40));
198 pm_io_base
&= 0xffc0;
200 /* XXX: need to improve memory and ioport allocation */
201 PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base
);
202 iorange_init(&s
->ioport
, &pm_iorange_ops
, pm_io_base
, 64);
203 ioport_register(&s
->ioport
);
207 static void pm_write_config(PCIDevice
*d
,
208 uint32_t address
, uint32_t val
, int len
)
210 pci_default_write_config(d
, address
, val
, len
);
211 if (range_covers_byte(address
, len
, 0x80))
212 pm_io_space_update((PIIX4PMState
*)d
);
215 static void vmstate_pci_status_pre_save(void *opaque
)
217 struct pci_status
*pci0_status
= opaque
;
218 PIIX4PMState
*s
= container_of(pci0_status
, PIIX4PMState
, pci0_status
);
220 /* We no longer track up, so build a safe value for migrating
221 * to a version that still does... of course these might get lost
222 * by an old buggy implementation, but we try. */
223 pci0_status
->up
= s
->pci0_slot_device_present
& s
->pci0_hotplug_enable
;
226 static int vmstate_acpi_post_load(void *opaque
, int version_id
)
228 PIIX4PMState
*s
= opaque
;
230 pm_io_space_update(s
);
234 #define VMSTATE_GPE_ARRAY(_field, _state) \
236 .name = (stringify(_field)), \
238 .info = &vmstate_info_uint16, \
239 .size = sizeof(uint16_t), \
240 .flags = VMS_SINGLE | VMS_POINTER, \
241 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \
244 static const VMStateDescription vmstate_gpe
= {
247 .minimum_version_id
= 1,
248 .minimum_version_id_old
= 1,
249 .fields
= (VMStateField
[]) {
250 VMSTATE_GPE_ARRAY(sts
, ACPIGPE
),
251 VMSTATE_GPE_ARRAY(en
, ACPIGPE
),
252 VMSTATE_END_OF_LIST()
256 static const VMStateDescription vmstate_pci_status
= {
257 .name
= "pci_status",
259 .minimum_version_id
= 1,
260 .minimum_version_id_old
= 1,
261 .pre_save
= vmstate_pci_status_pre_save
,
262 .fields
= (VMStateField
[]) {
263 VMSTATE_UINT32(up
, struct pci_status
),
264 VMSTATE_UINT32(down
, struct pci_status
),
265 VMSTATE_END_OF_LIST()
269 static int acpi_load_old(QEMUFile
*f
, void *opaque
, int version_id
)
271 PIIX4PMState
*s
= opaque
;
275 ret
= pci_device_load(&s
->dev
, f
);
279 qemu_get_be16s(f
, &s
->ar
.pm1
.evt
.sts
);
280 qemu_get_be16s(f
, &s
->ar
.pm1
.evt
.en
);
281 qemu_get_be16s(f
, &s
->ar
.pm1
.cnt
.cnt
);
283 ret
= vmstate_load_state(f
, &vmstate_apm
, opaque
, 1);
288 qemu_get_timer(f
, s
->ar
.tmr
.timer
);
289 qemu_get_sbe64s(f
, &s
->ar
.tmr
.overflow_time
);
291 qemu_get_be16s(f
, (uint16_t *)s
->ar
.gpe
.sts
);
292 for (i
= 0; i
< 3; i
++) {
293 qemu_get_be16s(f
, &temp
);
296 qemu_get_be16s(f
, (uint16_t *)s
->ar
.gpe
.en
);
297 for (i
= 0; i
< 3; i
++) {
298 qemu_get_be16s(f
, &temp
);
301 ret
= vmstate_load_state(f
, &vmstate_pci_status
, opaque
, 1);
305 /* qemu-kvm 1.2 uses version 3 but advertised as 2
306 * To support incoming qemu-kvm 1.2 migration, change version_id
307 * and minimum_version_id to 2 below (which breaks migration from
311 static const VMStateDescription vmstate_acpi
= {
314 .minimum_version_id
= 3,
315 .minimum_version_id_old
= 1,
316 .load_state_old
= acpi_load_old
,
317 .post_load
= vmstate_acpi_post_load
,
318 .fields
= (VMStateField
[]) {
319 VMSTATE_PCI_DEVICE(dev
, PIIX4PMState
),
320 VMSTATE_UINT16(ar
.pm1
.evt
.sts
, PIIX4PMState
),
321 VMSTATE_UINT16(ar
.pm1
.evt
.en
, PIIX4PMState
),
322 VMSTATE_UINT16(ar
.pm1
.cnt
.cnt
, PIIX4PMState
),
323 VMSTATE_STRUCT(apm
, PIIX4PMState
, 0, vmstate_apm
, APMState
),
324 VMSTATE_TIMER(ar
.tmr
.timer
, PIIX4PMState
),
325 VMSTATE_INT64(ar
.tmr
.overflow_time
, PIIX4PMState
),
326 VMSTATE_STRUCT(ar
.gpe
, PIIX4PMState
, 2, vmstate_gpe
, ACPIGPE
),
327 VMSTATE_STRUCT(pci0_status
, PIIX4PMState
, 2, vmstate_pci_status
,
329 VMSTATE_END_OF_LIST()
333 static void acpi_piix_eject_slot(PIIX4PMState
*s
, unsigned slots
)
335 BusChild
*kid
, *next
;
336 BusState
*bus
= qdev_get_parent_bus(&s
->dev
.qdev
);
337 int slot
= ffs(slots
) - 1;
338 bool slot_free
= true;
340 /* Mark request as complete */
341 s
->pci0_status
.down
&= ~(1U << slot
);
343 QTAILQ_FOREACH_SAFE(kid
, &bus
->children
, sibling
, next
) {
344 DeviceState
*qdev
= kid
->child
;
345 PCIDevice
*dev
= PCI_DEVICE(qdev
);
346 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
347 if (PCI_SLOT(dev
->devfn
) == slot
) {
348 if (pc
->no_hotplug
) {
356 s
->pci0_slot_device_present
&= ~(1U << slot
);
360 static void piix4_update_hotplug(PIIX4PMState
*s
)
362 PCIDevice
*dev
= &s
->dev
;
363 BusState
*bus
= qdev_get_parent_bus(&dev
->qdev
);
364 BusChild
*kid
, *next
;
366 /* Execute any pending removes during reset */
367 while (s
->pci0_status
.down
) {
368 acpi_piix_eject_slot(s
, s
->pci0_status
.down
);
371 s
->pci0_hotplug_enable
= ~0;
372 s
->pci0_slot_device_present
= 0;
374 QTAILQ_FOREACH_SAFE(kid
, &bus
->children
, sibling
, next
) {
375 DeviceState
*qdev
= kid
->child
;
376 PCIDevice
*pdev
= PCI_DEVICE(qdev
);
377 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pdev
);
378 int slot
= PCI_SLOT(pdev
->devfn
);
380 if (pc
->no_hotplug
) {
381 s
->pci0_hotplug_enable
&= ~(1U << slot
);
384 s
->pci0_slot_device_present
|= (1U << slot
);
388 static void piix4_reset(void *opaque
)
390 PIIX4PMState
*s
= opaque
;
391 uint8_t *pci_conf
= s
->dev
.config
;
398 pci_conf
[0x40] = 0x01; /* PM io base read only bit */
401 if (s
->kvm_enabled
) {
402 /* Mark SMM as already inited (until KVM supports SMM). */
403 pci_conf
[0x5B] = 0x02;
405 piix4_update_hotplug(s
);
408 static void piix4_pm_powerdown_req(Notifier
*n
, void *opaque
)
410 PIIX4PMState
*s
= container_of(n
, PIIX4PMState
, powerdown_notifier
);
413 acpi_pm1_evt_power_down(&s
->ar
);
416 static void piix4_pm_machine_ready(Notifier
*n
, void *opaque
)
418 PIIX4PMState
*s
= container_of(n
, PIIX4PMState
, machine_ready
);
421 pci_conf
= s
->dev
.config
;
422 pci_conf
[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10;
423 pci_conf
[0x63] = 0x60;
424 pci_conf
[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) |
425 (isa_is_ioport_assigned(0x2f8) ? 0x90 : 0);
429 static int piix4_pm_initfn(PCIDevice
*dev
)
431 PIIX4PMState
*s
= DO_UPCAST(PIIX4PMState
, dev
, dev
);
434 pci_conf
= s
->dev
.config
;
435 pci_conf
[0x06] = 0x80;
436 pci_conf
[0x07] = 0x02;
437 pci_conf
[0x09] = 0x00;
438 pci_conf
[0x3d] = 0x01; // interrupt pin 1
441 apm_init(&s
->apm
, apm_ctrl_changed
, s
);
443 register_ioport_write(ACPI_DBG_IO_ADDR
, 4, 4, acpi_dbg_writel
, s
);
445 if (s
->kvm_enabled
) {
446 /* Mark SMM as already inited to prevent SMM from running. KVM does not
447 * support SMM mode. */
448 pci_conf
[0x5B] = 0x02;
451 /* XXX: which specification is used ? The i82731AB has different
453 pci_conf
[0x90] = s
->smb_io_base
| 1;
454 pci_conf
[0x91] = s
->smb_io_base
>> 8;
455 pci_conf
[0xd2] = 0x09;
456 register_ioport_write(s
->smb_io_base
, 64, 1, smb_ioport_writeb
, &s
->smb
);
457 register_ioport_read(s
->smb_io_base
, 64, 1, smb_ioport_readb
, &s
->smb
);
459 acpi_pm_tmr_init(&s
->ar
, pm_tmr_timer
);
460 acpi_gpe_init(&s
->ar
, GPE_LEN
);
462 s
->powerdown_notifier
.notify
= piix4_pm_powerdown_req
;
463 qemu_register_powerdown_notifier(&s
->powerdown_notifier
);
465 pm_smbus_init(&s
->dev
.qdev
, &s
->smb
);
466 s
->machine_ready
.notify
= piix4_pm_machine_ready
;
467 qemu_add_machine_init_done_notifier(&s
->machine_ready
);
468 qemu_register_reset(piix4_reset
, s
);
469 piix4_acpi_system_hot_add_init(dev
->bus
, s
);
474 i2c_bus
*piix4_pm_init(PCIBus
*bus
, int devfn
, uint32_t smb_io_base
,
475 qemu_irq sci_irq
, qemu_irq smi_irq
,
476 int kvm_enabled
, void *fw_cfg
)
481 dev
= pci_create(bus
, devfn
, "PIIX4_PM");
482 qdev_prop_set_uint32(&dev
->qdev
, "smb_io_base", smb_io_base
);
484 s
= DO_UPCAST(PIIX4PMState
, dev
, dev
);
486 acpi_pm1_cnt_init(&s
->ar
);
487 s
->smi_irq
= smi_irq
;
488 s
->kvm_enabled
= kvm_enabled
;
490 qdev_init_nofail(&dev
->qdev
);
493 uint8_t suspend
[6] = {128, 0, 0, 129, 128, 128};
494 suspend
[3] = 1 | ((!s
->disable_s3
) << 7);
495 suspend
[4] = s
->s4_val
| ((!s
->disable_s4
) << 7);
497 fw_cfg_add_file(fw_cfg
, "etc/system-states", g_memdup(suspend
, 6), 6);
503 static Property piix4_pm_properties
[] = {
504 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState
, smb_io_base
, 0),
505 DEFINE_PROP_UINT8("disable_s3", PIIX4PMState
, disable_s3
, 0),
506 DEFINE_PROP_UINT8("disable_s4", PIIX4PMState
, disable_s4
, 0),
507 DEFINE_PROP_UINT8("s4_val", PIIX4PMState
, s4_val
, 2),
508 DEFINE_PROP_END_OF_LIST(),
511 static void piix4_pm_class_init(ObjectClass
*klass
, void *data
)
513 DeviceClass
*dc
= DEVICE_CLASS(klass
);
514 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
517 k
->init
= piix4_pm_initfn
;
518 k
->config_write
= pm_write_config
;
519 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
520 k
->device_id
= PCI_DEVICE_ID_INTEL_82371AB_3
;
522 k
->class_id
= PCI_CLASS_BRIDGE_OTHER
;
525 dc
->vmsd
= &vmstate_acpi
;
526 dc
->props
= piix4_pm_properties
;
529 static TypeInfo piix4_pm_info
= {
531 .parent
= TYPE_PCI_DEVICE
,
532 .instance_size
= sizeof(PIIX4PMState
),
533 .class_init
= piix4_pm_class_init
,
536 static void piix4_pm_register_types(void)
538 type_register_static(&piix4_pm_info
);
541 type_init(piix4_pm_register_types
)
543 static uint32_t gpe_readb(void *opaque
, uint32_t addr
)
545 PIIX4PMState
*s
= opaque
;
546 uint32_t val
= acpi_gpe_ioport_readb(&s
->ar
, addr
);
548 PIIX4_DPRINTF("gpe read %x == %x\n", addr
, val
);
552 static void gpe_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
554 PIIX4PMState
*s
= opaque
;
556 acpi_gpe_ioport_writeb(&s
->ar
, addr
, val
);
559 PIIX4_DPRINTF("gpe write %x <== %d\n", addr
, val
);
562 static uint32_t pci_up_read(void *opaque
, uint32_t addr
)
564 PIIX4PMState
*s
= opaque
;
567 /* Manufacture an "up" value to cause a device check on any hotplug
568 * slot with a device. Extra device checks are harmless. */
569 val
= s
->pci0_slot_device_present
& s
->pci0_hotplug_enable
;
571 PIIX4_DPRINTF("pci_up_read %x\n", val
);
575 static uint32_t pci_down_read(void *opaque
, uint32_t addr
)
577 PIIX4PMState
*s
= opaque
;
578 uint32_t val
= s
->pci0_status
.down
;
580 PIIX4_DPRINTF("pci_down_read %x\n", val
);
584 static uint32_t pci_features_read(void *opaque
, uint32_t addr
)
586 /* No feature defined yet */
587 PIIX4_DPRINTF("pci_features_read %x\n", 0);
591 static void pciej_write(void *opaque
, uint32_t addr
, uint32_t val
)
593 acpi_piix_eject_slot(opaque
, val
);
595 PIIX4_DPRINTF("pciej write %x <== %d\n", addr
, val
);
598 static uint32_t pcirmv_read(void *opaque
, uint32_t addr
)
600 PIIX4PMState
*s
= opaque
;
602 return s
->pci0_hotplug_enable
;
605 static int piix4_device_hotplug(DeviceState
*qdev
, PCIDevice
*dev
,
606 PCIHotplugState state
);
608 static void piix4_acpi_system_hot_add_init(PCIBus
*bus
, PIIX4PMState
*s
)
611 register_ioport_write(GPE_BASE
, GPE_LEN
, 1, gpe_writeb
, s
);
612 register_ioport_read(GPE_BASE
, GPE_LEN
, 1, gpe_readb
, s
);
613 acpi_gpe_blk(&s
->ar
, GPE_BASE
);
615 register_ioport_read(PCI_UP_BASE
, 4, 4, pci_up_read
, s
);
616 register_ioport_read(PCI_DOWN_BASE
, 4, 4, pci_down_read
, s
);
618 register_ioport_write(PCI_EJ_BASE
, 4, 4, pciej_write
, s
);
619 register_ioport_read(PCI_EJ_BASE
, 4, 4, pci_features_read
, s
);
621 register_ioport_read(PCI_RMV_BASE
, 4, 4, pcirmv_read
, s
);
623 pci_bus_hotplug(bus
, piix4_device_hotplug
, &s
->dev
.qdev
);
626 static void enable_device(PIIX4PMState
*s
, int slot
)
628 s
->ar
.gpe
.sts
[0] |= PIIX4_PCI_HOTPLUG_STATUS
;
629 s
->pci0_slot_device_present
|= (1U << slot
);
632 static void disable_device(PIIX4PMState
*s
, int slot
)
634 s
->ar
.gpe
.sts
[0] |= PIIX4_PCI_HOTPLUG_STATUS
;
635 s
->pci0_status
.down
|= (1U << slot
);
638 static int piix4_device_hotplug(DeviceState
*qdev
, PCIDevice
*dev
,
639 PCIHotplugState state
)
641 int slot
= PCI_SLOT(dev
->devfn
);
642 PIIX4PMState
*s
= DO_UPCAST(PIIX4PMState
, dev
,
645 /* Don't send event when device is enabled during qemu machine creation:
646 * it is present on boot, no hotplug event is necessary. We do send an
647 * event when the device is disabled later. */
648 if (state
== PCI_COLDPLUG_ENABLED
) {
649 s
->pci0_slot_device_present
|= (1U << slot
);
653 if (state
== PCI_HOTPLUG_ENABLED
) {
654 enable_device(s
, slot
);
656 disable_device(s
, slot
);