hw/acpi_piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  *
  18  * Contributions after 2012-01-13 are licensed under the terms of the
  19  * GNU GPL, version 2 or (at your option) any later version.
  20  */
  21 #include "hw.h"
  22 #include "pc.h"
  23 #include "apm.h"
  24 #include "pm_smbus.h"
  25 #include "pci.h"
  26 #include "acpi.h"
  27 #include "sysemu.h"
  28 #include "range.h"
  29 #include "ioport.h"
  30 #include "fw_cfg.h"
  31 #include "exec-memory.h"
  32
  33 //#define DEBUG
  34
  35 #ifdef DEBUG
  36 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  37 #else
  38 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
  39 #endif
  40
  41 #define ACPI_DBG_IO_ADDR  0xb044
  42
  43 #define GPE_BASE 0xafe0
  44 #define GPE_LEN 4
  45 #define PCI_UP_BASE 0xae00
  46 #define PCI_DOWN_BASE 0xae04
  47 #define PCI_EJ_BASE 0xae08
  48 #define PCI_RMV_BASE 0xae0c
  49
  50 #define PIIX4_PCI_HOTPLUG_STATUS 2
  51
  52 struct pci_status {
  53     uint32_t up; /* deprecated, maintained for migration compatibility */
  54     uint32_t down;
  55 };
  56
  57 typedef struct PIIX4PMState {
  58     PCIDevice dev;
  59     MemoryRegion io;
  60     MemoryRegion io_gpe;
  61     ACPIREGS ar;
  62
  63     APMState apm;
  64
  65     PMSMBus smb;
  66     uint32_t smb_io_base;
  67
  68     qemu_irq irq;
  69     qemu_irq smi_irq;
  70     int kvm_enabled;
  71     Notifier machine_ready;
  72     Notifier powerdown_notifier;
  73
  74     /* for pci hotplug */
  75     struct pci_status pci0_status;
  76     uint32_t pci0_hotplug_enable;
  77     uint32_t pci0_slot_device_present;
  78
  79     uint8_t disable_s3;
  80     uint8_t disable_s4;
  81     uint8_t s4_val;
  82 } PIIX4PMState;
  83
  84 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
  85
  86 #define ACPI_ENABLE 0xf1
  87 #define ACPI_DISABLE 0xf0
  88
  89 static void pm_update_sci(PIIX4PMState *s)
  90 {
  91     int sci_level, pmsts;
  92
  93     pmsts = acpi_pm1_evt_get_sts(&s->ar);
  94     sci_level = (((pmsts & s->ar.pm1.evt.en) &
  95                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
  96                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
  97                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
  98                    ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
  99         (((s->ar.gpe.sts[0] & s->ar.gpe.en[0])
 100           & PIIX4_PCI_HOTPLUG_STATUS) != 0);
 101
 102     qemu_set_irq(s->irq, sci_level);
 103     /* schedule a timer interruption if needed */
 104     acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
 105                        !(pmsts & ACPI_BITMASK_TIMER_STATUS));
 106 }
 107
 108 static void pm_tmr_timer(ACPIREGS *ar)
 109 {
 110     PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
 111     pm_update_sci(s);
 112 }
 113
 114 static void apm_ctrl_changed(uint32_t val, void *arg)
 115 {
 116     PIIX4PMState *s = arg;
 117
 118     /* ACPI specs 3.0, 4.7.2.5 */
 119     acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
 120
 121     if (s->dev.config[0x5b] & (1 << 1)) {
 122         if (s->smi_irq) {
 123             qemu_irq_raise(s->smi_irq);
 124         }
 125     }
 126 }
 127
 128 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 129 {
 130     PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
 131 }
 132
 133 static void pm_io_space_update(PIIX4PMState *s)
 134 {
 135     uint32_t pm_io_base;
 136
 137     pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 138     pm_io_base &= 0xffc0;
 139
 140     memory_region_transaction_begin();
 141     memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1);
 142     memory_region_set_address(&s->io, pm_io_base);
 143     memory_region_transaction_commit();
 144 }
 145
 146 static void smbus_io_space_update(PIIX4PMState *s)
 147 {
 148     s->smb_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x90));
 149     s->smb_io_base &= 0xffc0;
 150
 151     memory_region_transaction_begin();
 152     memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & 1);
 153     memory_region_set_address(&s->smb.io, s->smb_io_base);
 154     memory_region_transaction_commit();
 155 }
 156
 157 static void pm_write_config(PCIDevice *d,
 158                             uint32_t address, uint32_t val, int len)
 159 {
 160     pci_default_write_config(d, address, val, len);
 161     if (range_covers_byte(address, len, 0x80) ||
 162         ranges_overlap(address, len, 0x40, 4)) {
 163         pm_io_space_update((PIIX4PMState *)d);
 164     }
 165     if (range_covers_byte(address, len, 0xd2) ||
 166         ranges_overlap(address, len, 0x90, 4)) {
 167         smbus_io_space_update((PIIX4PMState *)d);
 168     }
 169 }
 170
 171 static void vmstate_pci_status_pre_save(void *opaque)
 172 {
 173     struct pci_status *pci0_status = opaque;
 174     PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci0_status);
 175
 176     /* We no longer track up, so build a safe value for migrating
 177      * to a version that still does... of course these might get lost
 178      * by an old buggy implementation, but we try. */
 179     pci0_status->up = s->pci0_slot_device_present & s->pci0_hotplug_enable;
 180 }
 181
 182 static int vmstate_acpi_post_load(void *opaque, int version_id)
 183 {
 184     PIIX4PMState *s = opaque;
 185
 186     pm_io_space_update(s);
 187     return 0;
 188 }
 189
 190 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 191  {                                                                   \
 192      .name       = (stringify(_field)),                              \
 193      .version_id = 0,                                                \
 194      .info       = &vmstate_info_uint16,                             \
 195      .size       = sizeof(uint16_t),                                 \
 196      .flags      = VMS_SINGLE | VMS_POINTER,                         \
 197      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 198  }
 199
 200 static const VMStateDescription vmstate_gpe = {
 201     .name = "gpe",
 202     .version_id = 1,
 203     .minimum_version_id = 1,
 204     .minimum_version_id_old = 1,
 205     .fields      = (VMStateField []) {
 206         VMSTATE_GPE_ARRAY(sts, ACPIGPE),
 207         VMSTATE_GPE_ARRAY(en, ACPIGPE),
 208         VMSTATE_END_OF_LIST()
 209     }
 210 };
 211
 212 static const VMStateDescription vmstate_pci_status = {
 213     .name = "pci_status",
 214     .version_id = 1,
 215     .minimum_version_id = 1,
 216     .minimum_version_id_old = 1,
 217     .pre_save = vmstate_pci_status_pre_save,
 218     .fields      = (VMStateField []) {
 219         VMSTATE_UINT32(up, struct pci_status),
 220         VMSTATE_UINT32(down, struct pci_status),
 221         VMSTATE_END_OF_LIST()
 222     }
 223 };
 224
 225 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
 226 {
 227     PIIX4PMState *s = opaque;
 228     int ret, i;
 229     uint16_t temp;
 230
 231     ret = pci_device_load(&s->dev, f);
 232     if (ret < 0) {
 233         return ret;
 234     }
 235     qemu_get_be16s(f, &s->ar.pm1.evt.sts);
 236     qemu_get_be16s(f, &s->ar.pm1.evt.en);
 237     qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
 238
 239     ret = vmstate_load_state(f, &vmstate_apm, opaque, 1);
 240     if (ret) {
 241         return ret;
 242     }
 243
 244     qemu_get_timer(f, s->ar.tmr.timer);
 245     qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
 246
 247     qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
 248     for (i = 0; i < 3; i++) {
 249         qemu_get_be16s(f, &temp);
 250     }
 251
 252     qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
 253     for (i = 0; i < 3; i++) {
 254         qemu_get_be16s(f, &temp);
 255     }
 256
 257     ret = vmstate_load_state(f, &vmstate_pci_status, opaque, 1);
 258     return ret;
 259 }
 260
 261 /* qemu-kvm 1.2 uses version 3 but advertised as 2
 262  * To support incoming qemu-kvm 1.2 migration, change version_id
 263  * and minimum_version_id to 2 below (which breaks migration from
 264  * qemu 1.2).
 265  *
 266  */
 267 static const VMStateDescription vmstate_acpi = {
 268     .name = "piix4_pm",
 269     .version_id = 3,
 270     .minimum_version_id = 3,
 271     .minimum_version_id_old = 1,
 272     .load_state_old = acpi_load_old,
 273     .post_load = vmstate_acpi_post_load,
 274     .fields      = (VMStateField []) {
 275         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
 276         VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
 277         VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
 278         VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
 279         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 280         VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState),
 281         VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
 282         VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
 283         VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
 284                        struct pci_status),
 285         VMSTATE_END_OF_LIST()
 286     }
 287 };
 288
 289 static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots)
 290 {
 291     BusChild *kid, *next;
 292     BusState *bus = qdev_get_parent_bus(&s->dev.qdev);
 293     int slot = ffs(slots) - 1;
 294     bool slot_free = true;
 295
 296     /* Mark request as complete */
 297     s->pci0_status.down &= ~(1U << slot);
 298
 299     QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
 300         DeviceState *qdev = kid->child;
 301         PCIDevice *dev = PCI_DEVICE(qdev);
 302         PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
 303         if (PCI_SLOT(dev->devfn) == slot) {
 304             if (pc->no_hotplug) {
 305                 slot_free = false;
 306             } else {
 307                 qdev_free(qdev);
 308             }
 309         }
 310     }
 311     if (slot_free) {
 312         s->pci0_slot_device_present &= ~(1U << slot);
 313     }
 314 }
 315
 316 static void piix4_update_hotplug(PIIX4PMState *s)
 317 {
 318     PCIDevice *dev = &s->dev;
 319     BusState *bus = qdev_get_parent_bus(&dev->qdev);
 320     BusChild *kid, *next;
 321
 322     /* Execute any pending removes during reset */
 323     while (s->pci0_status.down) {
 324         acpi_piix_eject_slot(s, s->pci0_status.down);
 325     }
 326
 327     s->pci0_hotplug_enable = ~0;
 328     s->pci0_slot_device_present = 0;
 329
 330     QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
 331         DeviceState *qdev = kid->child;
 332         PCIDevice *pdev = PCI_DEVICE(qdev);
 333         PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev);
 334         int slot = PCI_SLOT(pdev->devfn);
 335
 336         if (pc->no_hotplug) {
 337             s->pci0_hotplug_enable &= ~(1U << slot);
 338         }
 339
 340         s->pci0_slot_device_present |= (1U << slot);
 341     }
 342 }
 343
 344 static void piix4_reset(void *opaque)
 345 {
 346     PIIX4PMState *s = opaque;
 347     uint8_t *pci_conf = s->dev.config;
 348
 349     pci_conf[0x58] = 0;
 350     pci_conf[0x59] = 0;
 351     pci_conf[0x5a] = 0;
 352     pci_conf[0x5b] = 0;
 353
 354     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 355     pci_conf[0x80] = 0;
 356
 357     if (s->kvm_enabled) {
 358         /* Mark SMM as already inited (until KVM supports SMM). */
 359         pci_conf[0x5B] = 0x02;
 360     }
 361     piix4_update_hotplug(s);
 362 }
 363
 364 static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
 365 {
 366     PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);
 367
 368     assert(s != NULL);
 369     acpi_pm1_evt_power_down(&s->ar);
 370 }
 371
 372 static void piix4_pm_machine_ready(Notifier *n, void *opaque)
 373 {
 374     PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
 375     uint8_t *pci_conf;
 376
 377     pci_conf = s->dev.config;
 378     pci_conf[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10;
 379     pci_conf[0x63] = 0x60;
 380     pci_conf[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) |
 381         (isa_is_ioport_assigned(0x2f8) ? 0x90 : 0);
 382
 383 }
 384
 385 static int piix4_pm_initfn(PCIDevice *dev)
 386 {
 387     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
 388     uint8_t *pci_conf;
 389
 390     pci_conf = s->dev.config;
 391     pci_conf[0x06] = 0x80;
 392     pci_conf[0x07] = 0x02;
 393     pci_conf[0x09] = 0x00;
 394     pci_conf[0x3d] = 0x01; // interrupt pin 1
 395
 396     /* APM */
 397     apm_init(&s->apm, apm_ctrl_changed, s);
 398
 399     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 400
 401     if (s->kvm_enabled) {
 402         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 403          * support SMM mode. */
 404         pci_conf[0x5B] = 0x02;
 405     }
 406
 407     /* XXX: which specification is used ? The i82731AB has different
 408        mappings */
 409     pci_conf[0x90] = s->smb_io_base | 1;
 410     pci_conf[0x91] = s->smb_io_base >> 8;
 411     pci_conf[0xd2] = 0x09;
 412     pm_smbus_init(&s->dev.qdev, &s->smb);
 413     memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
 414     memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io);
 415
 416     memory_region_init(&s->io, "piix4-pm", 64);
 417     memory_region_set_enabled(&s->io, false);
 418     memory_region_add_subregion(get_system_io(), 0, &s->io);
 419
 420     acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
 421     acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
 422     acpi_pm1_cnt_init(&s->ar, &s->io);
 423     acpi_gpe_init(&s->ar, GPE_LEN);
 424
 425     s->powerdown_notifier.notify = piix4_pm_powerdown_req;
 426     qemu_register_powerdown_notifier(&s->powerdown_notifier);
 427
 428     s->machine_ready.notify = piix4_pm_machine_ready;
 429     qemu_add_machine_init_done_notifier(&s->machine_ready);
 430     qemu_register_reset(piix4_reset, s);
 431     piix4_acpi_system_hot_add_init(dev->bus, s);
 432
 433     return 0;
 434 }
 435
 436 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 437                        qemu_irq sci_irq, qemu_irq smi_irq,
 438                        int kvm_enabled, void *fw_cfg)
 439 {
 440     PCIDevice *dev;
 441     PIIX4PMState *s;
 442
 443     dev = pci_create(bus, devfn, "PIIX4_PM");
 444     qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
 445
 446     s = DO_UPCAST(PIIX4PMState, dev, dev);
 447     s->irq = sci_irq;
 448     s->smi_irq = smi_irq;
 449     s->kvm_enabled = kvm_enabled;
 450
 451     qdev_init_nofail(&dev->qdev);
 452
 453     if (fw_cfg) {
 454         uint8_t suspend[6] = {128, 0, 0, 129, 128, 128};
 455         suspend[3] = 1 | ((!s->disable_s3) << 7);
 456         suspend[4] = s->s4_val | ((!s->disable_s4) << 7);
 457
 458         fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6);
 459     }
 460
 461     return s->smb.smbus;
 462 }
 463
 464 static Property piix4_pm_properties[] = {
 465     DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 466     DEFINE_PROP_UINT8("disable_s3", PIIX4PMState, disable_s3, 0),
 467     DEFINE_PROP_UINT8("disable_s4", PIIX4PMState, disable_s4, 0),
 468     DEFINE_PROP_UINT8("s4_val", PIIX4PMState, s4_val, 2),
 469     DEFINE_PROP_END_OF_LIST(),
 470 };
 471
 472 static void piix4_pm_class_init(ObjectClass *klass, void *data)
 473 {
 474     DeviceClass *dc = DEVICE_CLASS(klass);
 475     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 476
 477     k->no_hotplug = 1;
 478     k->init = piix4_pm_initfn;
 479     k->config_write = pm_write_config;
 480     k->vendor_id = PCI_VENDOR_ID_INTEL;
 481     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
 482     k->revision = 0x03;
 483     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 484     dc->desc = "PM";
 485     dc->no_user = 1;
 486     dc->vmsd = &vmstate_acpi;
 487     dc->props = piix4_pm_properties;
 488 }
 489
 490 static TypeInfo piix4_pm_info = {
 491     .name          = "PIIX4_PM",
 492     .parent        = TYPE_PCI_DEVICE,
 493     .instance_size = sizeof(PIIX4PMState),
 494     .class_init    = piix4_pm_class_init,
 495 };
 496
 497 static void piix4_pm_register_types(void)
 498 {
 499     type_register_static(&piix4_pm_info);
 500 }
 501
 502 type_init(piix4_pm_register_types)
 503
 504 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
 505 {
 506     PIIX4PMState *s = opaque;
 507     uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
 508
 509     PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
 510     return val;
 511 }
 512
 513 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
 514                        unsigned width)
 515 {
 516     PIIX4PMState *s = opaque;
 517
 518     acpi_gpe_ioport_writeb(&s->ar, addr, val);
 519     pm_update_sci(s);
 520
 521     PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
 522 }
 523
 524 static const MemoryRegionOps piix4_gpe_ops = {
 525     .read = gpe_readb,
 526     .write = gpe_writeb,
 527     .valid.min_access_size = 1,
 528     .valid.max_access_size = 4,
 529     .impl.min_access_size = 1,
 530     .impl.max_access_size = 1,
 531     .endianness = DEVICE_LITTLE_ENDIAN,
 532 };
 533
 534 static uint32_t pci_up_read(void *opaque, uint32_t addr)
 535 {
 536     PIIX4PMState *s = opaque;
 537     uint32_t val;
 538
 539     /* Manufacture an "up" value to cause a device check on any hotplug
 540      * slot with a device.  Extra device checks are harmless. */
 541     val = s->pci0_slot_device_present & s->pci0_hotplug_enable;
 542
 543     PIIX4_DPRINTF("pci_up_read %x\n", val);
 544     return val;
 545 }
 546
 547 static uint32_t pci_down_read(void *opaque, uint32_t addr)
 548 {
 549     PIIX4PMState *s = opaque;
 550     uint32_t val = s->pci0_status.down;
 551
 552     PIIX4_DPRINTF("pci_down_read %x\n", val);
 553     return val;
 554 }
 555
 556 static uint32_t pci_features_read(void *opaque, uint32_t addr)
 557 {
 558     /* No feature defined yet */
 559     PIIX4_DPRINTF("pci_features_read %x\n", 0);
 560     return 0;
 561 }
 562
 563 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 564 {
 565     acpi_piix_eject_slot(opaque, val);
 566
 567     PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
 568 }
 569
 570 static uint32_t pcirmv_read(void *opaque, uint32_t addr)
 571 {
 572     PIIX4PMState *s = opaque;
 573
 574     return s->pci0_hotplug_enable;
 575 }
 576
 577 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 578                                 PCIHotplugState state);
 579
 580 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
 581 {
 582     memory_region_init_io(&s->io_gpe, &piix4_gpe_ops, s, "apci-gpe0",
 583                           GPE_LEN);
 584     memory_region_add_subregion(get_system_io(), GPE_BASE, &s->io_gpe);
 585     acpi_gpe_blk(&s->ar, 0);
 586
 587     register_ioport_read(PCI_UP_BASE, 4, 4, pci_up_read, s);
 588     register_ioport_read(PCI_DOWN_BASE, 4, 4, pci_down_read, s);
 589
 590     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, s);
 591     register_ioport_read(PCI_EJ_BASE, 4, 4,  pci_features_read, s);
 592
 593     register_ioport_read(PCI_RMV_BASE, 4, 4,  pcirmv_read, s);
 594
 595     pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
 596 }
 597
 598 static void enable_device(PIIX4PMState *s, int slot)
 599 {
 600     s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
 601     s->pci0_slot_device_present |= (1U << slot);
 602 }
 603
 604 static void disable_device(PIIX4PMState *s, int slot)
 605 {
 606     s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
 607     s->pci0_status.down |= (1U << slot);
 608 }
 609
 610 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 611                                 PCIHotplugState state)
 612 {
 613     int slot = PCI_SLOT(dev->devfn);
 614     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
 615                                 PCI_DEVICE(qdev));
 616
 617     /* Don't send event when device is enabled during qemu machine creation:
 618      * it is present on boot, no hotplug event is necessary. We do send an
 619      * event when the device is disabled later. */
 620     if (state == PCI_COLDPLUG_ENABLED) {
 621         s->pci0_slot_device_present |= (1U << slot);
 622         return 0;
 623     }
 624
 625     if (state == PCI_HOTPLUG_ENABLED) {
 626         enable_device(s, slot);
 627     } else {
 628         disable_device(s, slot);
 629     }
 630
 631     pm_update_sci(s);
 632
 633     return 0;
 634 }