hw/acpi_piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  */
  18 #include "hw.h"
  19 #include "pc.h"
  20 #include "apm.h"
  21 #include "pm_smbus.h"
  22 #include "pci.h"
  23 #include "acpi.h"
  24 #include "sysemu.h"
  25 #include "range.h"
  26
  27 //#define DEBUG
  28
  29 #ifdef DEBUG
  30 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  31 #else
  32 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
  33 #endif
  34
  35 #define ACPI_DBG_IO_ADDR  0xb044
  36
  37 #define GPE_BASE 0xafe0
  38 #define PCI_BASE 0xae00
  39 #define PCI_EJ_BASE 0xae08
  40 #define PCI_RMV_BASE 0xae0c
  41
  42 #define PIIX4_PCI_HOTPLUG_STATUS 2
  43
  44 struct gpe_regs {
  45     uint16_t sts; /* status */
  46     uint16_t en;  /* enabled */
  47 };
  48
  49 struct pci_status {
  50     uint32_t up;
  51     uint32_t down;
  52 };
  53
  54 typedef struct PIIX4PMState {
  55     PCIDevice dev;
  56     IORange ioport;
  57     ACPIPM1EVT pm1a;
  58     ACPIPM1CNT pm1_cnt;
  59
  60     APMState apm;
  61
  62     ACPIPMTimer tmr;
  63
  64     PMSMBus smb;
  65     uint32_t smb_io_base;
  66
  67     qemu_irq irq;
  68     qemu_irq smi_irq;
  69     int kvm_enabled;
  70
  71     /* for pci hotplug */
  72     struct gpe_regs gpe;
  73     struct pci_status pci0_status;
  74     uint32_t pci0_hotplug_enable;
  75 } PIIX4PMState;
  76
  77 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
  78
  79 #define ACPI_ENABLE 0xf1
  80 #define ACPI_DISABLE 0xf0
  81
  82 static void pm_update_sci(PIIX4PMState *s)
  83 {
  84     int sci_level, pmsts;
  85
  86     pmsts = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
  87     sci_level = (((pmsts & s->pm1a.en) &
  88                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
  89                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
  90                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
  91                    ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
  92         (((s->gpe.sts & s->gpe.en) & PIIX4_PCI_HOTPLUG_STATUS) != 0);
  93
  94     qemu_set_irq(s->irq, sci_level);
  95     /* schedule a timer interruption if needed */
  96     acpi_pm_tmr_update(&s->tmr, (s->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) &&
  97                        !(pmsts & ACPI_BITMASK_TIMER_STATUS));
  98 }
  99
 100 static void pm_tmr_timer(ACPIPMTimer *tmr)
 101 {
 102     PIIX4PMState *s = container_of(tmr, PIIX4PMState, tmr);
 103     pm_update_sci(s);
 104 }
 105
 106 static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
 107                             uint64_t val)
 108 {
 109     PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
 110
 111     if (width != 2) {
 112         PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
 113                       (unsigned)addr, width, (unsigned)val);
 114     }
 115
 116     switch(addr) {
 117     case 0x00:
 118         acpi_pm1_evt_write_sts(&s->pm1a, &s->tmr, val);
 119         pm_update_sci(s);
 120         break;
 121     case 0x02:
 122         s->pm1a.en = val;
 123         pm_update_sci(s);
 124         break;
 125     case 0x04:
 126         acpi_pm1_cnt_write(&s->pm1a, &s->pm1_cnt, val);
 127         break;
 128     default:
 129         break;
 130     }
 131     PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr,
 132                   (unsigned int)val);
 133 }
 134
 135 static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width,
 136                             uint64_t *data)
 137 {
 138     PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
 139     uint32_t val;
 140
 141     switch(addr) {
 142     case 0x00:
 143         val = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
 144         break;
 145     case 0x02:
 146         val = s->pm1a.en;
 147         break;
 148     case 0x04:
 149         val = s->pm1_cnt.cnt;
 150         break;
 151     case 0x08:
 152         val = acpi_pm_tmr_get(&s->tmr);
 153         break;
 154     default:
 155         val = 0;
 156         break;
 157     }
 158     PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr, val);
 159     *data = val;
 160 }
 161
 162 static const IORangeOps pm_iorange_ops = {
 163     .read = pm_ioport_read,
 164     .write = pm_ioport_write,
 165 };
 166
 167 static void apm_ctrl_changed(uint32_t val, void *arg)
 168 {
 169     PIIX4PMState *s = arg;
 170
 171     /* ACPI specs 3.0, 4.7.2.5 */
 172     acpi_pm1_cnt_update(&s->pm1_cnt, val == ACPI_ENABLE, val == ACPI_DISABLE);
 173
 174     if (s->dev.config[0x5b] & (1 << 1)) {
 175         if (s->smi_irq) {
 176             qemu_irq_raise(s->smi_irq);
 177         }
 178     }
 179 }
 180
 181 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 182 {
 183     PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
 184 }
 185
 186 static void pm_io_space_update(PIIX4PMState *s)
 187 {
 188     uint32_t pm_io_base;
 189
 190     if (s->dev.config[0x80] & 1) {
 191         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 192         pm_io_base &= 0xffc0;
 193
 194         /* XXX: need to improve memory and ioport allocation */
 195         PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
 196         iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64);
 197         ioport_register(&s->ioport);
 198     }
 199 }
 200
 201 static void pm_write_config(PCIDevice *d,
 202                             uint32_t address, uint32_t val, int len)
 203 {
 204     pci_default_write_config(d, address, val, len);
 205     if (range_covers_byte(address, len, 0x80))
 206         pm_io_space_update((PIIX4PMState *)d);
 207 }
 208
 209 static int vmstate_acpi_post_load(void *opaque, int version_id)
 210 {
 211     PIIX4PMState *s = opaque;
 212
 213     pm_io_space_update(s);
 214     return 0;
 215 }
 216
 217 static const VMStateDescription vmstate_gpe = {
 218     .name = "gpe",
 219     .version_id = 1,
 220     .minimum_version_id = 1,
 221     .minimum_version_id_old = 1,
 222     .fields      = (VMStateField []) {
 223         VMSTATE_UINT16(sts, struct gpe_regs),
 224         VMSTATE_UINT16(en, struct gpe_regs),
 225         VMSTATE_END_OF_LIST()
 226     }
 227 };
 228
 229 static const VMStateDescription vmstate_pci_status = {
 230     .name = "pci_status",
 231     .version_id = 1,
 232     .minimum_version_id = 1,
 233     .minimum_version_id_old = 1,
 234     .fields      = (VMStateField []) {
 235         VMSTATE_UINT32(up, struct pci_status),
 236         VMSTATE_UINT32(down, struct pci_status),
 237         VMSTATE_END_OF_LIST()
 238     }
 239 };
 240
 241 static const VMStateDescription vmstate_acpi = {
 242     .name = "piix4_pm",
 243     .version_id = 2,
 244     .minimum_version_id = 1,
 245     .minimum_version_id_old = 1,
 246     .post_load = vmstate_acpi_post_load,
 247     .fields      = (VMStateField []) {
 248         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
 249         VMSTATE_UINT16(pm1a.sts, PIIX4PMState),
 250         VMSTATE_UINT16(pm1a.en, PIIX4PMState),
 251         VMSTATE_UINT16(pm1_cnt.cnt, PIIX4PMState),
 252         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 253         VMSTATE_TIMER(tmr.timer, PIIX4PMState),
 254         VMSTATE_INT64(tmr.overflow_time, PIIX4PMState),
 255         VMSTATE_STRUCT(gpe, PIIX4PMState, 2, vmstate_gpe, struct gpe_regs),
 256         VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
 257                        struct pci_status),
 258         VMSTATE_END_OF_LIST()
 259     }
 260 };
 261
 262 static void piix4_update_hotplug(PIIX4PMState *s)
 263 {
 264     PCIDevice *dev = &s->dev;
 265     BusState *bus = qdev_get_parent_bus(&dev->qdev);
 266     DeviceState *qdev, *next;
 267
 268     s->pci0_hotplug_enable = ~0;
 269
 270     QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 271         PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev);
 272         PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, qdev);
 273         int slot = PCI_SLOT(pdev->devfn);
 274
 275         if (info->no_hotplug) {
 276             s->pci0_hotplug_enable &= ~(1 << slot);
 277         }
 278     }
 279 }
 280
 281 static void piix4_reset(void *opaque)
 282 {
 283     PIIX4PMState *s = opaque;
 284     uint8_t *pci_conf = s->dev.config;
 285
 286     pci_conf[0x58] = 0;
 287     pci_conf[0x59] = 0;
 288     pci_conf[0x5a] = 0;
 289     pci_conf[0x5b] = 0;
 290
 291     if (s->kvm_enabled) {
 292         /* Mark SMM as already inited (until KVM supports SMM). */
 293         pci_conf[0x5B] = 0x02;
 294     }
 295     piix4_update_hotplug(s);
 296 }
 297
 298 static void piix4_powerdown(void *opaque, int irq, int power_failing)
 299 {
 300     PIIX4PMState *s = opaque;
 301     ACPIPM1EVT *pm1a = s? &s->pm1a: NULL;
 302     ACPIPMTimer *tmr = s? &s->tmr: NULL;
 303
 304     acpi_pm1_evt_power_down(pm1a, tmr);
 305 }
 306
 307 static int piix4_pm_initfn(PCIDevice *dev)
 308 {
 309     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
 310     uint8_t *pci_conf;
 311
 312     pci_conf = s->dev.config;
 313     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 314     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
 315     pci_conf[0x06] = 0x80;
 316     pci_conf[0x07] = 0x02;
 317     pci_conf[0x08] = 0x03; // revision number
 318     pci_conf[0x09] = 0x00;
 319     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
 320     pci_conf[0x3d] = 0x01; // interrupt pin 1
 321
 322     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 323
 324     /* APM */
 325     apm_init(&s->apm, apm_ctrl_changed, s);
 326
 327     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 328
 329     if (s->kvm_enabled) {
 330         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 331          * support SMM mode. */
 332         pci_conf[0x5B] = 0x02;
 333     }
 334
 335     /* XXX: which specification is used ? The i82731AB has different
 336        mappings */
 337     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 338     pci_conf[0x63] = 0x60;
 339     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 340         (serial_hds[1] != NULL ? 0x90 : 0);
 341
 342     pci_conf[0x90] = s->smb_io_base | 1;
 343     pci_conf[0x91] = s->smb_io_base >> 8;
 344     pci_conf[0xd2] = 0x09;
 345     register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
 346     register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
 347
 348     acpi_pm_tmr_init(&s->tmr, pm_tmr_timer);
 349
 350     qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
 351
 352     pm_smbus_init(&s->dev.qdev, &s->smb);
 353     qemu_register_reset(piix4_reset, s);
 354     piix4_acpi_system_hot_add_init(dev->bus, s);
 355
 356     return 0;
 357 }
 358
 359 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 360                        qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
 361                        int kvm_enabled)
 362 {
 363     PCIDevice *dev;
 364     PIIX4PMState *s;
 365
 366     dev = pci_create(bus, devfn, "PIIX4_PM");
 367     qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
 368
 369     s = DO_UPCAST(PIIX4PMState, dev, dev);
 370     s->irq = sci_irq;
 371     acpi_pm1_cnt_init(&s->pm1_cnt, cmos_s3);
 372     s->smi_irq = smi_irq;
 373     s->kvm_enabled = kvm_enabled;
 374
 375     qdev_init_nofail(&dev->qdev);
 376
 377     return s->smb.smbus;
 378 }
 379
 380 static PCIDeviceInfo piix4_pm_info = {
 381     .qdev.name          = "PIIX4_PM",
 382     .qdev.desc          = "PM",
 383     .qdev.size          = sizeof(PIIX4PMState),
 384     .qdev.vmsd          = &vmstate_acpi,
 385     .qdev.no_user       = 1,
 386     .no_hotplug         = 1,
 387     .init               = piix4_pm_initfn,
 388     .config_write       = pm_write_config,
 389     .qdev.props         = (Property[]) {
 390         DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 391         DEFINE_PROP_END_OF_LIST(),
 392     }
 393 };
 394
 395 static void piix4_pm_register(void)
 396 {
 397     pci_qdev_register(&piix4_pm_info);
 398 }
 399
 400 device_init(piix4_pm_register);
 401
 402 static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
 403 {
 404     if (addr & 1)
 405         return (val >> 8) & 0xff;
 406     return val & 0xff;
 407 }
 408
 409 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 410 {
 411     uint32_t val = 0;
 412     PIIX4PMState *s = opaque;
 413     struct gpe_regs *g = &s->gpe;
 414
 415     switch (addr) {
 416         case GPE_BASE:
 417         case GPE_BASE + 1:
 418             val = gpe_read_val(g->sts, addr);
 419             break;
 420         case GPE_BASE + 2:
 421         case GPE_BASE + 3:
 422             val = gpe_read_val(g->en, addr);
 423             break;
 424         default:
 425             break;
 426     }
 427
 428     PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
 429     return val;
 430 }
 431
 432 static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
 433 {
 434     if (addr & 1)
 435         *cur = (*cur & 0xff) | (val << 8);
 436     else
 437         *cur = (*cur & 0xff00) | (val & 0xff);
 438 }
 439
 440 static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
 441 {
 442     uint16_t x1, x0 = val & 0xff;
 443     int shift = (addr & 1) ? 8 : 0;
 444
 445     x1 = (*cur >> shift) & 0xff;
 446
 447     x1 = x1 & ~x0;
 448
 449     *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
 450 }
 451
 452 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 453 {
 454     PIIX4PMState *s = opaque;
 455     struct gpe_regs *g = &s->gpe;
 456
 457     switch (addr) {
 458         case GPE_BASE:
 459         case GPE_BASE + 1:
 460             gpe_reset_val(&g->sts, addr, val);
 461             break;
 462         case GPE_BASE + 2:
 463         case GPE_BASE + 3:
 464             gpe_write_val(&g->en, addr, val);
 465             break;
 466         default:
 467             break;
 468     }
 469
 470     pm_update_sci(s);
 471
 472     PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
 473 }
 474
 475 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 476 {
 477     uint32_t val = 0;
 478     struct pci_status *g = opaque;
 479     switch (addr) {
 480         case PCI_BASE:
 481             val = g->up;
 482             break;
 483         case PCI_BASE + 4:
 484             val = g->down;
 485             break;
 486         default:
 487             break;
 488     }
 489
 490     PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
 491     return val;
 492 }
 493
 494 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 495 {
 496     struct pci_status *g = opaque;
 497     switch (addr) {
 498         case PCI_BASE:
 499             g->up = val;
 500             break;
 501         case PCI_BASE + 4:
 502             g->down = val;
 503             break;
 504    }
 505
 506     PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
 507 }
 508
 509 static uint32_t pciej_read(void *opaque, uint32_t addr)
 510 {
 511     PIIX4_DPRINTF("pciej read %x\n", addr);
 512     return 0;
 513 }
 514
 515 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 516 {
 517     BusState *bus = opaque;
 518     DeviceState *qdev, *next;
 519     PCIDevice *dev;
 520     int slot = ffs(val) - 1;
 521
 522     QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 523         dev = DO_UPCAST(PCIDevice, qdev, qdev);
 524         if (PCI_SLOT(dev->devfn) == slot) {
 525             qdev_free(qdev);
 526         }
 527     }
 528
 529
 530     PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
 531 }
 532
 533 static uint32_t pcirmv_read(void *opaque, uint32_t addr)
 534 {
 535     PIIX4PMState *s = opaque;
 536
 537     return s->pci0_hotplug_enable;
 538 }
 539
 540 static void pcirmv_write(void *opaque, uint32_t addr, uint32_t val)
 541 {
 542     return;
 543 }
 544
 545 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 546                                 PCIHotplugState state);
 547
 548 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
 549 {
 550     struct pci_status *pci0_status = &s->pci0_status;
 551
 552     register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, s);
 553     register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, s);
 554
 555     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
 556     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, pci0_status);
 557
 558     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
 559     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
 560
 561     register_ioport_write(PCI_RMV_BASE, 4, 4, pcirmv_write, s);
 562     register_ioport_read(PCI_RMV_BASE, 4, 4,  pcirmv_read, s);
 563
 564     pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
 565 }
 566
 567 static void enable_device(PIIX4PMState *s, int slot)
 568 {
 569     s->gpe.sts |= PIIX4_PCI_HOTPLUG_STATUS;
 570     s->pci0_status.up |= (1 << slot);
 571 }
 572
 573 static void disable_device(PIIX4PMState *s, int slot)
 574 {
 575     s->gpe.sts |= PIIX4_PCI_HOTPLUG_STATUS;
 576     s->pci0_status.down |= (1 << slot);
 577 }
 578
 579 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 580                                 PCIHotplugState state)
 581 {
 582     int slot = PCI_SLOT(dev->devfn);
 583     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
 584                                 DO_UPCAST(PCIDevice, qdev, qdev));
 585
 586     /* Don't send event when device is enabled during qemu machine creation:
 587      * it is present on boot, no hotplug event is necessary. We do send an
 588      * event when the device is disabled later. */
 589     if (state == PCI_COLDPLUG_ENABLED) {
 590         return 0;
 591     }
 592
 593     s->pci0_status.up = 0;
 594     s->pci0_status.down = 0;
 595     if (state == PCI_HOTPLUG_ENABLED) {
 596         enable_device(s, slot);
 597     } else {
 598         disable_device(s, slot);
 599     }
 600
 601     pm_update_sci(s);
 602
 603     return 0;
 604 }