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4 * Copyright (c) 2004-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include "qemu-timer.h"
25 //#define DEBUG_IOAPIC
27 /* APIC Local Vector Table */
28 #define APIC_LVT_TIMER 0
29 #define APIC_LVT_THERMAL 1
30 #define APIC_LVT_PERFORM 2
31 #define APIC_LVT_LINT0 3
32 #define APIC_LVT_LINT1 4
33 #define APIC_LVT_ERROR 5
36 /* APIC delivery modes */
37 #define APIC_DM_FIXED 0
38 #define APIC_DM_LOWPRI 1
41 #define APIC_DM_INIT 5
42 #define APIC_DM_SIPI 6
43 #define APIC_DM_EXTINT 7
45 /* APIC destination mode */
46 #define APIC_DESTMODE_FLAT 0xf
47 #define APIC_DESTMODE_CLUSTER 1
49 #define APIC_TRIGGER_EDGE 0
50 #define APIC_TRIGGER_LEVEL 1
52 #define APIC_LVT_TIMER_PERIODIC (1<<17)
53 #define APIC_LVT_MASKED (1<<16)
54 #define APIC_LVT_LEVEL_TRIGGER (1<<15)
55 #define APIC_LVT_REMOTE_IRR (1<<14)
56 #define APIC_INPUT_POLARITY (1<<13)
57 #define APIC_SEND_PENDING (1<<12)
59 #define IOAPIC_NUM_PINS 0x18
61 #define ESR_ILLEGAL_ADDRESS (1 << 7)
63 #define APIC_SV_ENABLE (1 << 8)
66 #define MAX_APIC_WORDS 8
68 typedef struct APICState
{
74 uint32_t spurious_vec
;
77 uint32_t isr
[8]; /* in service register */
78 uint32_t tmr
[8]; /* trigger mode register */
79 uint32_t irr
[8]; /* interrupt request register */
80 uint32_t lvt
[APIC_LVT_NB
];
81 uint32_t esr
; /* error register */
86 uint32_t initial_count
;
87 int64_t initial_count_load_time
, next_time
;
96 uint64_t ioredtbl
[IOAPIC_NUM_PINS
];
99 static int apic_io_memory
;
100 static APICState
*local_apics
[MAX_APICS
+ 1];
101 static int last_apic_id
= 0;
103 static void apic_init_ipi(APICState
*s
);
104 static void apic_set_irq(APICState
*s
, int vector_num
, int trigger_mode
);
105 static void apic_update_irq(APICState
*s
);
107 /* Find first bit starting from msb. Return 0 if value = 0 */
108 static int fls_bit(uint32_t value
)
110 unsigned int ret
= 0;
112 #if defined(HOST_I386)
113 __asm__
__volatile__ ("bsr %1, %0\n" : "+r" (ret
) : "rm" (value
));
117 value
>>= 16, ret
= 16;
119 value
>>= 8, ret
+= 8;
121 value
>>= 4, ret
+= 4;
123 value
>>= 2, ret
+= 2;
124 return ret
+ (value
>> 1);
128 /* Find first bit starting from lsb. Return 0 if value = 0 */
129 static int ffs_bit(uint32_t value
)
131 unsigned int ret
= 0;
133 #if defined(HOST_I386)
134 __asm__
__volatile__ ("bsf %1, %0\n" : "+r" (ret
) : "rm" (value
));
139 if (!(value
& 0xffff))
140 value
>>= 16, ret
= 16;
142 value
>>= 8, ret
+= 8;
144 value
>>= 4, ret
+= 4;
146 value
>>= 2, ret
+= 2;
153 static inline void set_bit(uint32_t *tab
, int index
)
157 mask
= 1 << (index
& 0x1f);
161 static inline void reset_bit(uint32_t *tab
, int index
)
165 mask
= 1 << (index
& 0x1f);
169 #define foreach_apic(apic, deliver_bitmask, code) \
171 int __i, __j, __mask;\
172 for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
173 __mask = deliver_bitmask[__i];\
175 for(__j = 0; __j < 32; __j++) {\
176 if (__mask & (1 << __j)) {\
177 apic = local_apics[__i * 32 + __j];\
187 static void apic_bus_deliver(const uint32_t *deliver_bitmask
,
188 uint8_t delivery_mode
,
189 uint8_t vector_num
, uint8_t polarity
,
190 uint8_t trigger_mode
)
192 APICState
*apic_iter
;
194 switch (delivery_mode
) {
196 /* XXX: search for focus processor, arbitration */
200 for(i
= 0; i
< MAX_APIC_WORDS
; i
++) {
201 if (deliver_bitmask
[i
]) {
202 d
= i
* 32 + ffs_bit(deliver_bitmask
[i
]);
207 apic_iter
= local_apics
[d
];
209 apic_set_irq(apic_iter
, vector_num
, trigger_mode
);
223 /* normal INIT IPI sent to processors */
224 foreach_apic(apic_iter
, deliver_bitmask
,
225 apic_init_ipi(apic_iter
) );
229 /* handled in I/O APIC code */
236 foreach_apic(apic_iter
, deliver_bitmask
,
237 apic_set_irq(apic_iter
, vector_num
, trigger_mode
) );
240 void cpu_set_apic_base(CPUState
*env
, uint64_t val
)
242 APICState
*s
= env
->apic_state
;
244 printf("cpu_set_apic_base: %016" PRIx64
"\n", val
);
246 s
->apicbase
= (val
& 0xfffff000) |
247 (s
->apicbase
& (MSR_IA32_APICBASE_BSP
| MSR_IA32_APICBASE_ENABLE
));
248 /* if disabled, cannot be enabled again */
249 if (!(val
& MSR_IA32_APICBASE_ENABLE
)) {
250 s
->apicbase
&= ~MSR_IA32_APICBASE_ENABLE
;
251 env
->cpuid_features
&= ~CPUID_APIC
;
252 s
->spurious_vec
&= ~APIC_SV_ENABLE
;
256 uint64_t cpu_get_apic_base(CPUState
*env
)
258 APICState
*s
= env
->apic_state
;
260 printf("cpu_get_apic_base: %016" PRIx64
"\n", (uint64_t)s
->apicbase
);
265 void cpu_set_apic_tpr(CPUX86State
*env
, uint8_t val
)
267 APICState
*s
= env
->apic_state
;
268 s
->tpr
= (val
& 0x0f) << 4;
272 uint8_t cpu_get_apic_tpr(CPUX86State
*env
)
274 APICState
*s
= env
->apic_state
;
278 /* return -1 if no bit is set */
279 static int get_highest_priority_int(uint32_t *tab
)
282 for(i
= 7; i
>= 0; i
--) {
284 return i
* 32 + fls_bit(tab
[i
]);
290 static int apic_get_ppr(APICState
*s
)
295 isrv
= get_highest_priority_int(s
->isr
);
306 static int apic_get_arb_pri(APICState
*s
)
308 /* XXX: arbitration */
312 /* signal the CPU if an irq is pending */
313 static void apic_update_irq(APICState
*s
)
316 if (!(s
->spurious_vec
& APIC_SV_ENABLE
))
318 irrv
= get_highest_priority_int(s
->irr
);
321 ppr
= apic_get_ppr(s
);
322 if (ppr
&& (irrv
& 0xf0) <= (ppr
& 0xf0))
324 cpu_interrupt(s
->cpu_env
, CPU_INTERRUPT_HARD
);
327 static void apic_set_irq(APICState
*s
, int vector_num
, int trigger_mode
)
329 set_bit(s
->irr
, vector_num
);
331 set_bit(s
->tmr
, vector_num
);
333 reset_bit(s
->tmr
, vector_num
);
337 static void apic_eoi(APICState
*s
)
340 isrv
= get_highest_priority_int(s
->isr
);
343 reset_bit(s
->isr
, isrv
);
344 /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
345 set the remote IRR bit for level triggered interrupts. */
349 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask
,
350 uint8_t dest
, uint8_t dest_mode
)
352 APICState
*apic_iter
;
355 if (dest_mode
== 0) {
357 memset(deliver_bitmask
, 0xff, MAX_APIC_WORDS
* sizeof(uint32_t));
359 memset(deliver_bitmask
, 0x00, MAX_APIC_WORDS
* sizeof(uint32_t));
360 set_bit(deliver_bitmask
, dest
);
363 /* XXX: cluster mode */
364 memset(deliver_bitmask
, 0x00, MAX_APIC_WORDS
* sizeof(uint32_t));
365 for(i
= 0; i
< MAX_APICS
; i
++) {
366 apic_iter
= local_apics
[i
];
368 if (apic_iter
->dest_mode
== 0xf) {
369 if (dest
& apic_iter
->log_dest
)
370 set_bit(deliver_bitmask
, i
);
371 } else if (apic_iter
->dest_mode
== 0x0) {
372 if ((dest
& 0xf0) == (apic_iter
->log_dest
& 0xf0) &&
373 (dest
& apic_iter
->log_dest
& 0x0f)) {
374 set_bit(deliver_bitmask
, i
);
383 static void apic_init_ipi(APICState
*s
)
388 s
->spurious_vec
= 0xff;
391 memset(s
->isr
, 0, sizeof(s
->isr
));
392 memset(s
->tmr
, 0, sizeof(s
->tmr
));
393 memset(s
->irr
, 0, sizeof(s
->irr
));
394 for(i
= 0; i
< APIC_LVT_NB
; i
++)
395 s
->lvt
[i
] = 1 << 16; /* mask LVT */
397 memset(s
->icr
, 0, sizeof(s
->icr
));
400 s
->initial_count
= 0;
401 s
->initial_count_load_time
= 0;
405 /* send a SIPI message to the CPU to start it */
406 static void apic_startup(APICState
*s
, int vector_num
)
408 CPUState
*env
= s
->cpu_env
;
409 if (!(env
->hflags
& HF_HALTED_MASK
))
412 cpu_x86_load_seg_cache(env
, R_CS
, vector_num
<< 8, vector_num
<< 12,
414 env
->hflags
&= ~HF_HALTED_MASK
;
417 static void apic_deliver(APICState
*s
, uint8_t dest
, uint8_t dest_mode
,
418 uint8_t delivery_mode
, uint8_t vector_num
,
419 uint8_t polarity
, uint8_t trigger_mode
)
421 uint32_t deliver_bitmask
[MAX_APIC_WORDS
];
422 int dest_shorthand
= (s
->icr
[0] >> 18) & 3;
423 APICState
*apic_iter
;
425 switch (dest_shorthand
) {
427 apic_get_delivery_bitmask(deliver_bitmask
, dest
, dest_mode
);
430 memset(deliver_bitmask
, 0x00, sizeof(deliver_bitmask
));
431 set_bit(deliver_bitmask
, s
->id
);
434 memset(deliver_bitmask
, 0xff, sizeof(deliver_bitmask
));
437 memset(deliver_bitmask
, 0xff, sizeof(deliver_bitmask
));
438 reset_bit(deliver_bitmask
, s
->id
);
442 switch (delivery_mode
) {
445 int trig_mode
= (s
->icr
[0] >> 15) & 1;
446 int level
= (s
->icr
[0] >> 14) & 1;
447 if (level
== 0 && trig_mode
== 1) {
448 foreach_apic(apic_iter
, deliver_bitmask
,
449 apic_iter
->arb_id
= apic_iter
->id
);
456 foreach_apic(apic_iter
, deliver_bitmask
,
457 apic_startup(apic_iter
, vector_num
) );
461 apic_bus_deliver(deliver_bitmask
, delivery_mode
, vector_num
, polarity
,
465 int apic_get_interrupt(CPUState
*env
)
467 APICState
*s
= env
->apic_state
;
470 /* if the APIC is installed or enabled, we let the 8259 handle the
474 if (!(s
->spurious_vec
& APIC_SV_ENABLE
))
477 /* XXX: spurious IRQ handling */
478 intno
= get_highest_priority_int(s
->irr
);
481 if (s
->tpr
&& intno
<= s
->tpr
)
482 return s
->spurious_vec
& 0xff;
483 reset_bit(s
->irr
, intno
);
484 set_bit(s
->isr
, intno
);
489 int apic_accept_pic_intr(CPUState
*env
)
491 APICState
*s
= env
->apic_state
;
497 lvt0
= s
->lvt
[APIC_LVT_LINT0
];
500 ((s
->apicbase
& MSR_IA32_APICBASE_ENABLE
) == 0 ||
501 ((lvt0
& APIC_LVT_MASKED
) == 0 &&
502 ((lvt0
>> 8) & 0x7) == APIC_DM_EXTINT
)))
508 static uint32_t apic_get_current_count(APICState
*s
)
512 d
= (qemu_get_clock(vm_clock
) - s
->initial_count_load_time
) >>
514 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_TIMER_PERIODIC
) {
516 val
= s
->initial_count
- (d
% ((uint64_t)s
->initial_count
+ 1));
518 if (d
>= s
->initial_count
)
521 val
= s
->initial_count
- d
;
526 static void apic_timer_update(APICState
*s
, int64_t current_time
)
528 int64_t next_time
, d
;
530 if (!(s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_MASKED
)) {
531 d
= (current_time
- s
->initial_count_load_time
) >>
533 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_TIMER_PERIODIC
) {
534 d
= ((d
/ ((uint64_t)s
->initial_count
+ 1)) + 1) * ((uint64_t)s
->initial_count
+ 1);
536 if (d
>= s
->initial_count
)
538 d
= (uint64_t)s
->initial_count
+ 1;
540 next_time
= s
->initial_count_load_time
+ (d
<< s
->count_shift
);
541 qemu_mod_timer(s
->timer
, next_time
);
542 s
->next_time
= next_time
;
545 qemu_del_timer(s
->timer
);
549 static void apic_timer(void *opaque
)
551 APICState
*s
= opaque
;
553 if (!(s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_MASKED
)) {
554 apic_set_irq(s
, s
->lvt
[APIC_LVT_TIMER
] & 0xff, APIC_TRIGGER_EDGE
);
556 apic_timer_update(s
, s
->next_time
);
559 static uint32_t apic_mem_readb(void *opaque
, target_phys_addr_t addr
)
564 static uint32_t apic_mem_readw(void *opaque
, target_phys_addr_t addr
)
569 static void apic_mem_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
573 static void apic_mem_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
577 static uint32_t apic_mem_readl(void *opaque
, target_phys_addr_t addr
)
584 env
= cpu_single_env
;
589 index
= (addr
>> 4) & 0xff;
594 case 0x03: /* version */
595 val
= 0x11 | ((APIC_LVT_NB
- 1) << 16); /* version 0x11 */
601 val
= apic_get_arb_pri(s
);
605 val
= apic_get_ppr(s
);
608 val
= s
->log_dest
<< 24;
611 val
= s
->dest_mode
<< 28;
614 val
= s
->spurious_vec
;
617 val
= s
->isr
[index
& 7];
620 val
= s
->tmr
[index
& 7];
623 val
= s
->irr
[index
& 7];
630 val
= s
->icr
[index
& 1];
633 val
= s
->lvt
[index
- 0x32];
636 val
= s
->initial_count
;
639 val
= apic_get_current_count(s
);
642 val
= s
->divide_conf
;
645 s
->esr
|= ESR_ILLEGAL_ADDRESS
;
650 printf("APIC read: %08x = %08x\n", (uint32_t)addr
, val
);
655 static void apic_mem_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
661 env
= cpu_single_env
;
667 printf("APIC write: %08x = %08x\n", (uint32_t)addr
, val
);
670 index
= (addr
>> 4) & 0xff;
688 s
->log_dest
= val
>> 24;
691 s
->dest_mode
= val
>> 28;
694 s
->spurious_vec
= val
& 0x1ff;
704 apic_deliver(s
, (s
->icr
[1] >> 24) & 0xff, (s
->icr
[0] >> 11) & 1,
705 (s
->icr
[0] >> 8) & 7, (s
->icr
[0] & 0xff),
706 (s
->icr
[0] >> 14) & 1, (s
->icr
[0] >> 15) & 1);
713 int n
= index
- 0x32;
715 if (n
== APIC_LVT_TIMER
)
716 apic_timer_update(s
, qemu_get_clock(vm_clock
));
720 s
->initial_count
= val
;
721 s
->initial_count_load_time
= qemu_get_clock(vm_clock
);
722 apic_timer_update(s
, s
->initial_count_load_time
);
729 s
->divide_conf
= val
& 0xb;
730 v
= (s
->divide_conf
& 3) | ((s
->divide_conf
>> 1) & 4);
731 s
->count_shift
= (v
+ 1) & 7;
735 s
->esr
|= ESR_ILLEGAL_ADDRESS
;
740 static void apic_save(QEMUFile
*f
, void *opaque
)
742 APICState
*s
= opaque
;
745 qemu_put_be32s(f
, &s
->apicbase
);
746 qemu_put_8s(f
, &s
->id
);
747 qemu_put_8s(f
, &s
->arb_id
);
748 qemu_put_8s(f
, &s
->tpr
);
749 qemu_put_be32s(f
, &s
->spurious_vec
);
750 qemu_put_8s(f
, &s
->log_dest
);
751 qemu_put_8s(f
, &s
->dest_mode
);
752 for (i
= 0; i
< 8; i
++) {
753 qemu_put_be32s(f
, &s
->isr
[i
]);
754 qemu_put_be32s(f
, &s
->tmr
[i
]);
755 qemu_put_be32s(f
, &s
->irr
[i
]);
757 for (i
= 0; i
< APIC_LVT_NB
; i
++) {
758 qemu_put_be32s(f
, &s
->lvt
[i
]);
760 qemu_put_be32s(f
, &s
->esr
);
761 qemu_put_be32s(f
, &s
->icr
[0]);
762 qemu_put_be32s(f
, &s
->icr
[1]);
763 qemu_put_be32s(f
, &s
->divide_conf
);
764 qemu_put_be32(f
, s
->count_shift
);
765 qemu_put_be32s(f
, &s
->initial_count
);
766 qemu_put_be64(f
, s
->initial_count_load_time
);
767 qemu_put_be64(f
, s
->next_time
);
769 qemu_put_timer(f
, s
->timer
);
772 static int apic_load(QEMUFile
*f
, void *opaque
, int version_id
)
774 APICState
*s
= opaque
;
780 /* XXX: what if the base changes? (registered memory regions) */
781 qemu_get_be32s(f
, &s
->apicbase
);
782 qemu_get_8s(f
, &s
->id
);
783 qemu_get_8s(f
, &s
->arb_id
);
784 qemu_get_8s(f
, &s
->tpr
);
785 qemu_get_be32s(f
, &s
->spurious_vec
);
786 qemu_get_8s(f
, &s
->log_dest
);
787 qemu_get_8s(f
, &s
->dest_mode
);
788 for (i
= 0; i
< 8; i
++) {
789 qemu_get_be32s(f
, &s
->isr
[i
]);
790 qemu_get_be32s(f
, &s
->tmr
[i
]);
791 qemu_get_be32s(f
, &s
->irr
[i
]);
793 for (i
= 0; i
< APIC_LVT_NB
; i
++) {
794 qemu_get_be32s(f
, &s
->lvt
[i
]);
796 qemu_get_be32s(f
, &s
->esr
);
797 qemu_get_be32s(f
, &s
->icr
[0]);
798 qemu_get_be32s(f
, &s
->icr
[1]);
799 qemu_get_be32s(f
, &s
->divide_conf
);
800 s
->count_shift
=qemu_get_be32(f
);
801 qemu_get_be32s(f
, &s
->initial_count
);
802 s
->initial_count_load_time
=qemu_get_be64(f
);
803 s
->next_time
=qemu_get_be64(f
);
806 qemu_get_timer(f
, s
->timer
);
810 static void apic_reset(void *opaque
)
812 APICState
*s
= opaque
;
816 * LINT0 delivery mode is set to ExtInt at initialization time
817 * typically by BIOS, so PIC interrupt can be delivered to the
818 * processor when local APIC is enabled.
820 s
->lvt
[APIC_LVT_LINT0
] = 0x700;
823 static CPUReadMemoryFunc
*apic_mem_read
[3] = {
829 static CPUWriteMemoryFunc
*apic_mem_write
[3] = {
835 int apic_init(CPUState
*env
)
839 if (last_apic_id
>= MAX_APICS
)
841 s
= qemu_mallocz(sizeof(APICState
));
846 s
->id
= last_apic_id
++;
847 env
->cpuid_apic_id
= s
->id
;
849 s
->apicbase
= 0xfee00000 |
850 (s
->id
? 0 : MSR_IA32_APICBASE_BSP
) | MSR_IA32_APICBASE_ENABLE
;
853 * LINT0 delivery mode is set to ExtInt at initialization time
854 * typically by BIOS, so PIC interrupt can be delivered to the
855 * processor when local APIC is enabled.
857 s
->lvt
[APIC_LVT_LINT0
] = 0x700;
859 /* XXX: mapping more APICs at the same memory location */
860 if (apic_io_memory
== 0) {
861 /* NOTE: the APIC is directly connected to the CPU - it is not
862 on the global memory bus. */
863 apic_io_memory
= cpu_register_io_memory(0, apic_mem_read
,
864 apic_mem_write
, NULL
);
865 cpu_register_physical_memory(s
->apicbase
& ~0xfff, 0x1000,
868 s
->timer
= qemu_new_timer(vm_clock
, apic_timer
, s
);
870 register_savevm("apic", s
->id
, 2, apic_save
, apic_load
, s
);
871 qemu_register_reset(apic_reset
, s
);
873 local_apics
[s
->id
] = s
;
877 static void ioapic_service(IOAPICState
*s
)
882 uint8_t delivery_mode
;
888 uint32_t deliver_bitmask
[MAX_APIC_WORDS
];
890 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
893 entry
= s
->ioredtbl
[i
];
894 if (!(entry
& APIC_LVT_MASKED
)) {
895 trig_mode
= ((entry
>> 15) & 1);
897 dest_mode
= (entry
>> 11) & 1;
898 delivery_mode
= (entry
>> 8) & 7;
899 polarity
= (entry
>> 13) & 1;
900 if (trig_mode
== APIC_TRIGGER_EDGE
)
902 if (delivery_mode
== APIC_DM_EXTINT
)
903 vector
= pic_read_irq(isa_pic
);
905 vector
= entry
& 0xff;
907 apic_get_delivery_bitmask(deliver_bitmask
, dest
, dest_mode
);
908 apic_bus_deliver(deliver_bitmask
, delivery_mode
,
909 vector
, polarity
, trig_mode
);
915 void ioapic_set_irq(void *opaque
, int vector
, int level
)
917 IOAPICState
*s
= opaque
;
919 if (vector
>= 0 && vector
< IOAPIC_NUM_PINS
) {
920 uint32_t mask
= 1 << vector
;
921 uint64_t entry
= s
->ioredtbl
[vector
];
923 if ((entry
>> 15) & 1) {
924 /* level triggered */
941 static uint32_t ioapic_mem_readl(void *opaque
, target_phys_addr_t addr
)
943 IOAPICState
*s
= opaque
;
950 } else if (addr
== 0x10) {
951 switch (s
->ioregsel
) {
956 val
= 0x11 | ((IOAPIC_NUM_PINS
- 1) << 16); /* version 0x11 */
962 index
= (s
->ioregsel
- 0x10) >> 1;
963 if (index
>= 0 && index
< IOAPIC_NUM_PINS
) {
965 val
= s
->ioredtbl
[index
] >> 32;
967 val
= s
->ioredtbl
[index
] & 0xffffffff;
971 printf("I/O APIC read: %08x = %08x\n", s
->ioregsel
, val
);
977 static void ioapic_mem_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
979 IOAPICState
*s
= opaque
;
986 } else if (addr
== 0x10) {
988 printf("I/O APIC write: %08x = %08x\n", s
->ioregsel
, val
);
990 switch (s
->ioregsel
) {
992 s
->id
= (val
>> 24) & 0xff;
998 index
= (s
->ioregsel
- 0x10) >> 1;
999 if (index
>= 0 && index
< IOAPIC_NUM_PINS
) {
1000 if (s
->ioregsel
& 1) {
1001 s
->ioredtbl
[index
] &= 0xffffffff;
1002 s
->ioredtbl
[index
] |= (uint64_t)val
<< 32;
1004 s
->ioredtbl
[index
] &= ~0xffffffffULL
;
1005 s
->ioredtbl
[index
] |= val
;
1013 static void ioapic_save(QEMUFile
*f
, void *opaque
)
1015 IOAPICState
*s
= opaque
;
1018 qemu_put_8s(f
, &s
->id
);
1019 qemu_put_8s(f
, &s
->ioregsel
);
1020 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
1021 qemu_put_be64s(f
, &s
->ioredtbl
[i
]);
1025 static int ioapic_load(QEMUFile
*f
, void *opaque
, int version_id
)
1027 IOAPICState
*s
= opaque
;
1030 if (version_id
!= 1)
1033 qemu_get_8s(f
, &s
->id
);
1034 qemu_get_8s(f
, &s
->ioregsel
);
1035 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
1036 qemu_get_be64s(f
, &s
->ioredtbl
[i
]);
1041 static void ioapic_reset(void *opaque
)
1043 IOAPICState
*s
= opaque
;
1046 memset(s
, 0, sizeof(*s
));
1047 for(i
= 0; i
< IOAPIC_NUM_PINS
; i
++)
1048 s
->ioredtbl
[i
] = 1 << 16; /* mask LVT */
1051 static CPUReadMemoryFunc
*ioapic_mem_read
[3] = {
1057 static CPUWriteMemoryFunc
*ioapic_mem_write
[3] = {
1063 IOAPICState
*ioapic_init(void)
1068 s
= qemu_mallocz(sizeof(IOAPICState
));
1072 s
->id
= last_apic_id
++;
1074 io_memory
= cpu_register_io_memory(0, ioapic_mem_read
,
1075 ioapic_mem_write
, s
);
1076 cpu_register_physical_memory(0xfec00000, 0x1000, io_memory
);
1078 register_savevm("ioapic", 0, 1, ioapic_save
, ioapic_load
, s
);
1079 qemu_register_reset(ioapic_reset
, s
);