hw/apic_common.c

   1 /*
   2  *  APIC support - common bits of emulated and KVM kernel model
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *  Copyright (c) 2011      Jan Kiszka, Siemens AG
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  19  */
  20 #include "apic.h"
  21 #include "apic_internal.h"
  22 #include "trace.h"
  23
  24 static int apic_irq_delivered;
  25
  26 void cpu_set_apic_base(DeviceState *d, uint64_t val)
  27 {
  28     trace_cpu_set_apic_base(val);
  29
  30     if (d) {
  31         APICCommonState *s = APIC_COMMON(d);
  32         APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
  33         info->set_base(s, val);
  34     }
  35 }
  36
  37 uint64_t cpu_get_apic_base(DeviceState *d)
  38 {
  39     if (d) {
  40         APICCommonState *s = APIC_COMMON(d);
  41         trace_cpu_get_apic_base((uint64_t)s->apicbase);
  42         return s->apicbase;
  43     } else {
  44         trace_cpu_get_apic_base(0);
  45         return 0;
  46     }
  47 }
  48
  49 void cpu_set_apic_tpr(DeviceState *d, uint8_t val)
  50 {
  51     APICCommonState *s;
  52     APICCommonClass *info;
  53
  54     if (!d) {
  55         return;
  56     }
  57
  58     s = APIC_COMMON(d);
  59     info = APIC_COMMON_GET_CLASS(s);
  60
  61     info->set_tpr(s, val);
  62 }
  63
  64 uint8_t cpu_get_apic_tpr(DeviceState *d)
  65 {
  66     APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
  67
  68     return s ? s->tpr >> 4 : 0;
  69 }
  70
  71 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
  72                                    TPRAccess access)
  73 {
  74 }
  75
  76 void apic_report_irq_delivered(int delivered)
  77 {
  78     apic_irq_delivered += delivered;
  79
  80     trace_apic_report_irq_delivered(apic_irq_delivered);
  81 }
  82
  83 void apic_reset_irq_delivered(void)
  84 {
  85     trace_apic_reset_irq_delivered(apic_irq_delivered);
  86
  87     apic_irq_delivered = 0;
  88 }
  89
  90 int apic_get_irq_delivered(void)
  91 {
  92     trace_apic_get_irq_delivered(apic_irq_delivered);
  93
  94     return apic_irq_delivered;
  95 }
  96
  97 void apic_deliver_nmi(DeviceState *d)
  98 {
  99     APICCommonState *s = APIC_COMMON(d);
 100     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 101
 102     info->external_nmi(s);
 103 }
 104
 105 bool apic_next_timer(APICCommonState *s, int64_t current_time)
 106 {
 107     int64_t d;
 108
 109     /* We need to store the timer state separately to support APIC
 110      * implementations that maintain a non-QEMU timer, e.g. inside the
 111      * host kernel. This open-coded state allows us to migrate between
 112      * both models. */
 113     s->timer_expiry = -1;
 114
 115     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
 116         return false;
 117     }
 118
 119     d = (current_time - s->initial_count_load_time) >> s->count_shift;
 120
 121     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 122         if (!s->initial_count) {
 123             return false;
 124         }
 125         d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
 126             ((uint64_t)s->initial_count + 1);
 127     } else {
 128         if (d >= s->initial_count) {
 129             return false;
 130         }
 131         d = (uint64_t)s->initial_count + 1;
 132     }
 133     s->next_time = s->initial_count_load_time + (d << s->count_shift);
 134     s->timer_expiry = s->next_time;
 135     return true;
 136 }
 137
 138 void apic_init_reset(DeviceState *d)
 139 {
 140     APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
 141     int i;
 142
 143     if (!s) {
 144         return;
 145     }
 146     s->tpr = 0;
 147     s->spurious_vec = 0xff;
 148     s->log_dest = 0;
 149     s->dest_mode = 0xf;
 150     memset(s->isr, 0, sizeof(s->isr));
 151     memset(s->tmr, 0, sizeof(s->tmr));
 152     memset(s->irr, 0, sizeof(s->irr));
 153     for (i = 0; i < APIC_LVT_NB; i++) {
 154         s->lvt[i] = APIC_LVT_MASKED;
 155     }
 156     s->esr = 0;
 157     memset(s->icr, 0, sizeof(s->icr));
 158     s->divide_conf = 0;
 159     s->count_shift = 0;
 160     s->initial_count = 0;
 161     s->initial_count_load_time = 0;
 162     s->next_time = 0;
 163     s->wait_for_sipi = 1;
 164
 165     if (s->timer) {
 166         qemu_del_timer(s->timer);
 167     }
 168     s->timer_expiry = -1;
 169 }
 170
 171 static void apic_reset_common(DeviceState *d)
 172 {
 173     APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
 174     bool bsp;
 175
 176     bsp = cpu_is_bsp(s->cpu_env);
 177     s->apicbase = 0xfee00000 |
 178         (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
 179
 180     apic_init_reset(d);
 181
 182     if (bsp) {
 183         /*
 184          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
 185          * time typically by BIOS, so PIC interrupt can be delivered to the
 186          * processor when local APIC is enabled.
 187          */
 188         s->lvt[APIC_LVT_LINT0] = 0x700;
 189     }
 190 }
 191
 192 /* This function is only used for old state version 1 and 2 */
 193 static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
 194 {
 195     APICCommonState *s = opaque;
 196     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 197     int i;
 198
 199     if (version_id > 2) {
 200         return -EINVAL;
 201     }
 202
 203     /* XXX: what if the base changes? (registered memory regions) */
 204     qemu_get_be32s(f, &s->apicbase);
 205     qemu_get_8s(f, &s->id);
 206     qemu_get_8s(f, &s->arb_id);
 207     qemu_get_8s(f, &s->tpr);
 208     qemu_get_be32s(f, &s->spurious_vec);
 209     qemu_get_8s(f, &s->log_dest);
 210     qemu_get_8s(f, &s->dest_mode);
 211     for (i = 0; i < 8; i++) {
 212         qemu_get_be32s(f, &s->isr[i]);
 213         qemu_get_be32s(f, &s->tmr[i]);
 214         qemu_get_be32s(f, &s->irr[i]);
 215     }
 216     for (i = 0; i < APIC_LVT_NB; i++) {
 217         qemu_get_be32s(f, &s->lvt[i]);
 218     }
 219     qemu_get_be32s(f, &s->esr);
 220     qemu_get_be32s(f, &s->icr[0]);
 221     qemu_get_be32s(f, &s->icr[1]);
 222     qemu_get_be32s(f, &s->divide_conf);
 223     s->count_shift = qemu_get_be32(f);
 224     qemu_get_be32s(f, &s->initial_count);
 225     s->initial_count_load_time = qemu_get_be64(f);
 226     s->next_time = qemu_get_be64(f);
 227
 228     if (version_id >= 2) {
 229         s->timer_expiry = qemu_get_be64(f);
 230     }
 231
 232     if (info->post_load) {
 233         info->post_load(s);
 234     }
 235     return 0;
 236 }
 237
 238 static int apic_init_common(SysBusDevice *dev)
 239 {
 240     APICCommonState *s = APIC_COMMON(dev);
 241     APICCommonClass *info;
 242     static int apic_no;
 243
 244     if (apic_no >= MAX_APICS) {
 245         return -1;
 246     }
 247     s->idx = apic_no++;
 248
 249     info = APIC_COMMON_GET_CLASS(s);
 250     info->init(s);
 251
 252     sysbus_init_mmio(&s->busdev, &s->io_memory);
 253     return 0;
 254 }
 255
 256 static int apic_dispatch_post_load(void *opaque, int version_id)
 257 {
 258     APICCommonState *s = APIC_COMMON(opaque);
 259     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 260
 261     if (info->post_load) {
 262         info->post_load(s);
 263     }
 264     return 0;
 265 }
 266
 267 static const VMStateDescription vmstate_apic_common = {
 268     .name = "apic",
 269     .version_id = 3,
 270     .minimum_version_id = 3,
 271     .minimum_version_id_old = 1,
 272     .load_state_old = apic_load_old,
 273     .post_load = apic_dispatch_post_load,
 274     .fields = (VMStateField[]) {
 275         VMSTATE_UINT32(apicbase, APICCommonState),
 276         VMSTATE_UINT8(id, APICCommonState),
 277         VMSTATE_UINT8(arb_id, APICCommonState),
 278         VMSTATE_UINT8(tpr, APICCommonState),
 279         VMSTATE_UINT32(spurious_vec, APICCommonState),
 280         VMSTATE_UINT8(log_dest, APICCommonState),
 281         VMSTATE_UINT8(dest_mode, APICCommonState),
 282         VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8),
 283         VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8),
 284         VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
 285         VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
 286         VMSTATE_UINT32(esr, APICCommonState),
 287         VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
 288         VMSTATE_UINT32(divide_conf, APICCommonState),
 289         VMSTATE_INT32(count_shift, APICCommonState),
 290         VMSTATE_UINT32(initial_count, APICCommonState),
 291         VMSTATE_INT64(initial_count_load_time, APICCommonState),
 292         VMSTATE_INT64(next_time, APICCommonState),
 293         VMSTATE_INT64(timer_expiry,
 294                       APICCommonState), /* open-coded timer state */
 295         VMSTATE_END_OF_LIST()
 296     }
 297 };
 298
 299 static Property apic_properties_common[] = {
 300     DEFINE_PROP_UINT8("id", APICCommonState, id, -1),
 301     DEFINE_PROP_PTR("cpu_env", APICCommonState, cpu_env),
 302     DEFINE_PROP_END_OF_LIST(),
 303 };
 304
 305 static void apic_common_class_init(ObjectClass *klass, void *data)
 306 {
 307     SysBusDeviceClass *sc = SYS_BUS_DEVICE_CLASS(klass);
 308     DeviceClass *dc = DEVICE_CLASS(klass);
 309
 310     dc->vmsd = &vmstate_apic_common;
 311     dc->reset = apic_reset_common;
 312     dc->no_user = 1;
 313     dc->props = apic_properties_common;
 314     sc->init = apic_init_common;
 315 }
 316
 317 static TypeInfo apic_common_type = {
 318     .name = TYPE_APIC_COMMON,
 319     .parent = TYPE_SYS_BUS_DEVICE,
 320     .instance_size = sizeof(APICCommonState),
 321     .class_size = sizeof(APICCommonClass),
 322     .class_init = apic_common_class_init,
 323     .abstract = true,
 324 };
 325
 326 static void register_types(void)
 327 {
 328     type_register_static(&apic_common_type);
 329 }
 330
 331 type_init(register_types)