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hw/arm: Add watchdog timer to Allwinner H40 and Bananapi board
[mirror_qemu.git] / hw / arm / allwinner-r40.c
1 /*
2 * Allwinner R40/A40i/T3 System on Chip emulation
3 *
4 * Copyright (C) 2023 qianfan Zhao <qianfanguijin@163.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "qemu/error-report.h"
23 #include "qemu/bswap.h"
24 #include "qemu/module.h"
25 #include "qemu/units.h"
26 #include "hw/boards.h"
27 #include "hw/qdev-core.h"
28 #include "hw/sysbus.h"
29 #include "hw/char/serial.h"
30 #include "hw/misc/unimp.h"
31 #include "hw/usb/hcd-ehci.h"
32 #include "hw/loader.h"
33 #include "sysemu/sysemu.h"
34 #include "hw/arm/allwinner-r40.h"
35 #include "hw/misc/allwinner-r40-dramc.h"
36
37 /* Memory map */
38 const hwaddr allwinner_r40_memmap[] = {
39 [AW_R40_DEV_SRAM_A1] = 0x00000000,
40 [AW_R40_DEV_SRAM_A2] = 0x00004000,
41 [AW_R40_DEV_SRAM_A3] = 0x00008000,
42 [AW_R40_DEV_SRAM_A4] = 0x0000b400,
43 [AW_R40_DEV_SRAMC] = 0x01c00000,
44 [AW_R40_DEV_EMAC] = 0x01c0b000,
45 [AW_R40_DEV_MMC0] = 0x01c0f000,
46 [AW_R40_DEV_MMC1] = 0x01c10000,
47 [AW_R40_DEV_MMC2] = 0x01c11000,
48 [AW_R40_DEV_MMC3] = 0x01c12000,
49 [AW_R40_DEV_AHCI] = 0x01c18000,
50 [AW_R40_DEV_EHCI1] = 0x01c19000,
51 [AW_R40_DEV_OHCI1] = 0x01c19400,
52 [AW_R40_DEV_EHCI2] = 0x01c1c000,
53 [AW_R40_DEV_OHCI2] = 0x01c1c400,
54 [AW_R40_DEV_CCU] = 0x01c20000,
55 [AW_R40_DEV_PIT] = 0x01c20c00,
56 [AW_R40_DEV_WDT] = 0x01c20c90,
57 [AW_R40_DEV_UART0] = 0x01c28000,
58 [AW_R40_DEV_UART1] = 0x01c28400,
59 [AW_R40_DEV_UART2] = 0x01c28800,
60 [AW_R40_DEV_UART3] = 0x01c28c00,
61 [AW_R40_DEV_UART4] = 0x01c29000,
62 [AW_R40_DEV_UART5] = 0x01c29400,
63 [AW_R40_DEV_UART6] = 0x01c29800,
64 [AW_R40_DEV_UART7] = 0x01c29c00,
65 [AW_R40_DEV_TWI0] = 0x01c2ac00,
66 [AW_R40_DEV_GMAC] = 0x01c50000,
67 [AW_R40_DEV_DRAMCOM] = 0x01c62000,
68 [AW_R40_DEV_DRAMCTL] = 0x01c63000,
69 [AW_R40_DEV_DRAMPHY] = 0x01c65000,
70 [AW_R40_DEV_GIC_DIST] = 0x01c81000,
71 [AW_R40_DEV_GIC_CPU] = 0x01c82000,
72 [AW_R40_DEV_GIC_HYP] = 0x01c84000,
73 [AW_R40_DEV_GIC_VCPU] = 0x01c86000,
74 [AW_R40_DEV_SDRAM] = 0x40000000
75 };
76
77 /* List of unimplemented devices */
78 struct AwR40Unimplemented {
79 const char *device_name;
80 hwaddr base;
81 hwaddr size;
82 };
83
84 static struct AwR40Unimplemented r40_unimplemented[] = {
85 { "d-engine", 0x01000000, 4 * MiB },
86 { "d-inter", 0x01400000, 128 * KiB },
87 { "dma", 0x01c02000, 4 * KiB },
88 { "nfdc", 0x01c03000, 4 * KiB },
89 { "ts", 0x01c04000, 4 * KiB },
90 { "spi0", 0x01c05000, 4 * KiB },
91 { "spi1", 0x01c06000, 4 * KiB },
92 { "cs0", 0x01c09000, 4 * KiB },
93 { "keymem", 0x01c0a000, 4 * KiB },
94 { "usb0-otg", 0x01c13000, 4 * KiB },
95 { "usb0-host", 0x01c14000, 4 * KiB },
96 { "crypto", 0x01c15000, 4 * KiB },
97 { "spi2", 0x01c17000, 4 * KiB },
98 { "usb1-phy", 0x01c19800, 2 * KiB },
99 { "sid", 0x01c1b000, 4 * KiB },
100 { "usb2-phy", 0x01c1c800, 2 * KiB },
101 { "cs1", 0x01c1d000, 4 * KiB },
102 { "spi3", 0x01c1f000, 4 * KiB },
103 { "rtc", 0x01c20400, 1 * KiB },
104 { "pio", 0x01c20800, 1 * KiB },
105 { "owa", 0x01c21000, 1 * KiB },
106 { "ac97", 0x01c21400, 1 * KiB },
107 { "cir0", 0x01c21800, 1 * KiB },
108 { "cir1", 0x01c21c00, 1 * KiB },
109 { "pcm0", 0x01c22000, 1 * KiB },
110 { "pcm1", 0x01c22400, 1 * KiB },
111 { "pcm2", 0x01c22800, 1 * KiB },
112 { "audio", 0x01c22c00, 1 * KiB },
113 { "keypad", 0x01c23000, 1 * KiB },
114 { "pwm", 0x01c23400, 1 * KiB },
115 { "keyadc", 0x01c24400, 1 * KiB },
116 { "ths", 0x01c24c00, 1 * KiB },
117 { "rtp", 0x01c25000, 1 * KiB },
118 { "pmu", 0x01c25400, 1 * KiB },
119 { "cpu-cfg", 0x01c25c00, 1 * KiB },
120 { "uart0", 0x01c28000, 1 * KiB },
121 { "uart1", 0x01c28400, 1 * KiB },
122 { "uart2", 0x01c28800, 1 * KiB },
123 { "uart3", 0x01c28c00, 1 * KiB },
124 { "uart4", 0x01c29000, 1 * KiB },
125 { "uart5", 0x01c29400, 1 * KiB },
126 { "uart6", 0x01c29800, 1 * KiB },
127 { "uart7", 0x01c29c00, 1 * KiB },
128 { "ps20", 0x01c2a000, 1 * KiB },
129 { "ps21", 0x01c2a400, 1 * KiB },
130 { "twi1", 0x01c2b000, 1 * KiB },
131 { "twi2", 0x01c2b400, 1 * KiB },
132 { "twi3", 0x01c2b800, 1 * KiB },
133 { "twi4", 0x01c2c000, 1 * KiB },
134 { "scr", 0x01c2c400, 1 * KiB },
135 { "tvd-top", 0x01c30000, 4 * KiB },
136 { "tvd0", 0x01c31000, 4 * KiB },
137 { "tvd1", 0x01c32000, 4 * KiB },
138 { "tvd2", 0x01c33000, 4 * KiB },
139 { "tvd3", 0x01c34000, 4 * KiB },
140 { "gpu", 0x01c40000, 64 * KiB },
141 { "hstmr", 0x01c60000, 4 * KiB },
142 { "tcon-top", 0x01c70000, 4 * KiB },
143 { "lcd0", 0x01c71000, 4 * KiB },
144 { "lcd1", 0x01c72000, 4 * KiB },
145 { "tv0", 0x01c73000, 4 * KiB },
146 { "tv1", 0x01c74000, 4 * KiB },
147 { "tve-top", 0x01c90000, 16 * KiB },
148 { "tve0", 0x01c94000, 16 * KiB },
149 { "tve1", 0x01c98000, 16 * KiB },
150 { "mipi_dsi", 0x01ca0000, 4 * KiB },
151 { "mipi_dphy", 0x01ca1000, 4 * KiB },
152 { "ve", 0x01d00000, 1024 * KiB },
153 { "mp", 0x01e80000, 128 * KiB },
154 { "hdmi", 0x01ee0000, 128 * KiB },
155 { "prcm", 0x01f01400, 1 * KiB },
156 { "debug", 0x3f500000, 64 * KiB },
157 { "cpubist", 0x3f501000, 4 * KiB },
158 { "dcu", 0x3fff0000, 64 * KiB },
159 { "hstmr", 0x01c60000, 4 * KiB },
160 { "brom", 0xffff0000, 36 * KiB }
161 };
162
163 /* Per Processor Interrupts */
164 enum {
165 AW_R40_GIC_PPI_MAINT = 9,
166 AW_R40_GIC_PPI_HYPTIMER = 10,
167 AW_R40_GIC_PPI_VIRTTIMER = 11,
168 AW_R40_GIC_PPI_SECTIMER = 13,
169 AW_R40_GIC_PPI_PHYSTIMER = 14
170 };
171
172 /* Shared Processor Interrupts */
173 enum {
174 AW_R40_GIC_SPI_UART0 = 1,
175 AW_R40_GIC_SPI_UART1 = 2,
176 AW_R40_GIC_SPI_UART2 = 3,
177 AW_R40_GIC_SPI_UART3 = 4,
178 AW_R40_GIC_SPI_TWI0 = 7,
179 AW_R40_GIC_SPI_UART4 = 17,
180 AW_R40_GIC_SPI_UART5 = 18,
181 AW_R40_GIC_SPI_UART6 = 19,
182 AW_R40_GIC_SPI_UART7 = 20,
183 AW_R40_GIC_SPI_TIMER0 = 22,
184 AW_R40_GIC_SPI_TIMER1 = 23,
185 AW_R40_GIC_SPI_MMC0 = 32,
186 AW_R40_GIC_SPI_MMC1 = 33,
187 AW_R40_GIC_SPI_MMC2 = 34,
188 AW_R40_GIC_SPI_MMC3 = 35,
189 AW_R40_GIC_SPI_EMAC = 55,
190 AW_R40_GIC_SPI_AHCI = 56,
191 AW_R40_GIC_SPI_OHCI1 = 64,
192 AW_R40_GIC_SPI_OHCI2 = 65,
193 AW_R40_GIC_SPI_EHCI1 = 76,
194 AW_R40_GIC_SPI_EHCI2 = 78,
195 AW_R40_GIC_SPI_GMAC = 85,
196 };
197
198 /* Allwinner R40 general constants */
199 enum {
200 AW_R40_GIC_NUM_SPI = 128
201 };
202
203 #define BOOT0_MAGIC "eGON.BT0"
204
205 /* The low 8-bits of the 'boot_media' field in the SPL header */
206 #define SUNXI_BOOTED_FROM_MMC0 0
207 #define SUNXI_BOOTED_FROM_NAND 1
208 #define SUNXI_BOOTED_FROM_MMC2 2
209 #define SUNXI_BOOTED_FROM_SPI 3
210
211 struct boot_file_head {
212 uint32_t b_instruction;
213 uint8_t magic[8];
214 uint32_t check_sum;
215 uint32_t length;
216 uint32_t pub_head_size;
217 uint32_t fel_script_address;
218 uint32_t fel_uEnv_length;
219 uint32_t dt_name_offset;
220 uint32_t dram_size;
221 uint32_t boot_media;
222 uint32_t string_pool[13];
223 };
224
225 bool allwinner_r40_bootrom_setup(AwR40State *s, BlockBackend *blk, int unit)
226 {
227 const int64_t rom_size = 32 * KiB;
228 g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
229 struct boot_file_head *head = (struct boot_file_head *)buffer;
230
231 if (blk_pread(blk, 8 * KiB, rom_size, buffer, 0) < 0) {
232 error_setg(&error_fatal, "%s: failed to read BlockBackend data",
233 __func__);
234 return false;
235 }
236
237 /* we only check the magic string here. */
238 if (memcmp(head->magic, BOOT0_MAGIC, sizeof(head->magic))) {
239 return false;
240 }
241
242 /*
243 * Simulate the behavior of the bootROM, it will change the boot_media
244 * flag to indicate where the chip is booting from. R40 can boot from
245 * mmc0 or mmc2, the default value of boot_media is zero
246 * (SUNXI_BOOTED_FROM_MMC0), let's fix this flag when it is booting from
247 * the others.
248 */
249 if (unit == 2) {
250 head->boot_media = cpu_to_le32(SUNXI_BOOTED_FROM_MMC2);
251 } else {
252 head->boot_media = cpu_to_le32(SUNXI_BOOTED_FROM_MMC0);
253 }
254
255 rom_add_blob("allwinner-r40.bootrom", buffer, rom_size,
256 rom_size, s->memmap[AW_R40_DEV_SRAM_A1],
257 NULL, NULL, NULL, NULL, false);
258 return true;
259 }
260
261 static void allwinner_r40_init(Object *obj)
262 {
263 static const char *mmc_names[AW_R40_NUM_MMCS] = {
264 "mmc0", "mmc1", "mmc2", "mmc3"
265 };
266 AwR40State *s = AW_R40(obj);
267
268 s->memmap = allwinner_r40_memmap;
269
270 for (int i = 0; i < AW_R40_NUM_CPUS; i++) {
271 object_initialize_child(obj, "cpu[*]", &s->cpus[i],
272 ARM_CPU_TYPE_NAME("cortex-a7"));
273 }
274
275 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
276
277 object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
278 object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
279 "clk0-freq");
280 object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
281 "clk1-freq");
282
283 object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN4I);
284
285 object_initialize_child(obj, "ccu", &s->ccu, TYPE_AW_R40_CCU);
286
287 for (int i = 0; i < AW_R40_NUM_MMCS; i++) {
288 object_initialize_child(obj, mmc_names[i], &s->mmc[i],
289 TYPE_AW_SDHOST_SUN50I_A64);
290 }
291
292 object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
293
294 for (size_t i = 0; i < AW_R40_NUM_USB; i++) {
295 object_initialize_child(obj, "ehci[*]", &s->ehci[i],
296 TYPE_PLATFORM_EHCI);
297 object_initialize_child(obj, "ohci[*]", &s->ohci[i],
298 TYPE_SYSBUS_OHCI);
299 }
300
301 object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I);
302
303 object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
304 object_initialize_child(obj, "gmac", &s->gmac, TYPE_AW_SUN8I_EMAC);
305 object_property_add_alias(obj, "gmac-phy-addr",
306 OBJECT(&s->gmac), "phy-addr");
307
308 object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_R40_DRAMC);
309 object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
310 "ram-addr");
311 object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
312 "ram-size");
313
314 object_initialize_child(obj, "sramc", &s->sramc, TYPE_AW_SRAMC_SUN8I_R40);
315 }
316
317 static void allwinner_r40_realize(DeviceState *dev, Error **errp)
318 {
319 const char *r40_nic_models[] = { "gmac", "emac", NULL };
320 AwR40State *s = AW_R40(dev);
321
322 /* CPUs */
323 for (unsigned i = 0; i < AW_R40_NUM_CPUS; i++) {
324
325 /*
326 * Disable secondary CPUs. Guest EL3 firmware will start
327 * them via CPU reset control registers.
328 */
329 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
330 i > 0);
331
332 /* All exception levels required */
333 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true);
334 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
335
336 /* Mark realized */
337 qdev_realize(DEVICE(&s->cpus[i]), NULL, &error_fatal);
338 }
339
340 /* Generic Interrupt Controller */
341 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_R40_GIC_NUM_SPI +
342 GIC_INTERNAL);
343 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
344 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_R40_NUM_CPUS);
345 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
346 qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
347 sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal);
348
349 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_R40_DEV_GIC_DIST]);
350 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_R40_DEV_GIC_CPU]);
351 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_R40_DEV_GIC_HYP]);
352 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_R40_DEV_GIC_VCPU]);
353
354 /*
355 * Wire the outputs from each CPU's generic timer and the GICv2
356 * maintenance interrupt signal to the appropriate GIC PPI inputs,
357 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
358 */
359 for (unsigned i = 0; i < AW_R40_NUM_CPUS; i++) {
360 DeviceState *cpudev = DEVICE(&s->cpus[i]);
361 int ppibase = AW_R40_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS;
362 int irq;
363 /*
364 * Mapping from the output timer irq lines from the CPU to the
365 * GIC PPI inputs used for this board.
366 */
367 const int timer_irq[] = {
368 [GTIMER_PHYS] = AW_R40_GIC_PPI_PHYSTIMER,
369 [GTIMER_VIRT] = AW_R40_GIC_PPI_VIRTTIMER,
370 [GTIMER_HYP] = AW_R40_GIC_PPI_HYPTIMER,
371 [GTIMER_SEC] = AW_R40_GIC_PPI_SECTIMER,
372 };
373
374 /* Connect CPU timer outputs to GIC PPI inputs */
375 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
376 qdev_connect_gpio_out(cpudev, irq,
377 qdev_get_gpio_in(DEVICE(&s->gic),
378 ppibase + timer_irq[irq]));
379 }
380
381 /* Connect GIC outputs to CPU interrupt inputs */
382 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
383 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
384 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_R40_NUM_CPUS,
385 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
386 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_R40_NUM_CPUS),
387 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
388 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_R40_NUM_CPUS),
389 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
390
391 /* GIC maintenance signal */
392 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_R40_NUM_CPUS),
393 qdev_get_gpio_in(DEVICE(&s->gic),
394 ppibase + AW_R40_GIC_PPI_MAINT));
395 }
396
397 /* Timer */
398 sysbus_realize(SYS_BUS_DEVICE(&s->timer), &error_fatal);
399 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_R40_DEV_PIT]);
400 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
401 qdev_get_gpio_in(DEVICE(&s->gic),
402 AW_R40_GIC_SPI_TIMER0));
403 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
404 qdev_get_gpio_in(DEVICE(&s->gic),
405 AW_R40_GIC_SPI_TIMER1));
406
407 /* SRAM */
408 sysbus_realize(SYS_BUS_DEVICE(&s->sramc), &error_fatal);
409 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sramc), 0, s->memmap[AW_R40_DEV_SRAMC]);
410
411 memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1",
412 16 * KiB, &error_abort);
413 memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2",
414 16 * KiB, &error_abort);
415 memory_region_init_ram(&s->sram_a3, OBJECT(dev), "sram A3",
416 13 * KiB, &error_abort);
417 memory_region_init_ram(&s->sram_a4, OBJECT(dev), "sram A4",
418 3 * KiB, &error_abort);
419 memory_region_add_subregion(get_system_memory(),
420 s->memmap[AW_R40_DEV_SRAM_A1], &s->sram_a1);
421 memory_region_add_subregion(get_system_memory(),
422 s->memmap[AW_R40_DEV_SRAM_A2], &s->sram_a2);
423 memory_region_add_subregion(get_system_memory(),
424 s->memmap[AW_R40_DEV_SRAM_A3], &s->sram_a3);
425 memory_region_add_subregion(get_system_memory(),
426 s->memmap[AW_R40_DEV_SRAM_A4], &s->sram_a4);
427
428 /* Clock Control Unit */
429 sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal);
430 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_R40_DEV_CCU]);
431
432 /* SATA / AHCI */
433 sysbus_realize(SYS_BUS_DEVICE(&s->sata), &error_fatal);
434 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0,
435 allwinner_r40_memmap[AW_R40_DEV_AHCI]);
436 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0,
437 qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_AHCI));
438
439 /* USB */
440 for (size_t i = 0; i < AW_R40_NUM_USB; i++) {
441 g_autofree char *bus = g_strdup_printf("usb-bus.%zu", i);
442
443 object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", true,
444 &error_fatal);
445 sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal);
446 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
447 allwinner_r40_memmap[i ? AW_R40_DEV_EHCI2
448 : AW_R40_DEV_EHCI1]);
449 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
450 qdev_get_gpio_in(DEVICE(&s->gic),
451 i ? AW_R40_GIC_SPI_EHCI2
452 : AW_R40_GIC_SPI_EHCI1));
453
454 object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus,
455 &error_fatal);
456 sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal);
457 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0,
458 allwinner_r40_memmap[i ? AW_R40_DEV_OHCI2
459 : AW_R40_DEV_OHCI1]);
460 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0,
461 qdev_get_gpio_in(DEVICE(&s->gic),
462 i ? AW_R40_GIC_SPI_OHCI2
463 : AW_R40_GIC_SPI_OHCI1));
464 }
465
466 /* SD/MMC */
467 for (int i = 0; i < AW_R40_NUM_MMCS; i++) {
468 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->gic),
469 AW_R40_GIC_SPI_MMC0 + i);
470 const hwaddr addr = s->memmap[AW_R40_DEV_MMC0 + i];
471
472 object_property_set_link(OBJECT(&s->mmc[i]), "dma-memory",
473 OBJECT(get_system_memory()), &error_fatal);
474 sysbus_realize(SYS_BUS_DEVICE(&s->mmc[i]), &error_fatal);
475 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc[i]), 0, addr);
476 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc[i]), 0, irq);
477 }
478
479 /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
480 for (int i = 0; i < AW_R40_NUM_UARTS; i++) {
481 static const int uart_irqs[AW_R40_NUM_UARTS] = {
482 AW_R40_GIC_SPI_UART0,
483 AW_R40_GIC_SPI_UART1,
484 AW_R40_GIC_SPI_UART2,
485 AW_R40_GIC_SPI_UART3,
486 AW_R40_GIC_SPI_UART4,
487 AW_R40_GIC_SPI_UART5,
488 AW_R40_GIC_SPI_UART6,
489 AW_R40_GIC_SPI_UART7,
490 };
491 const hwaddr addr = s->memmap[AW_R40_DEV_UART0 + i];
492
493 serial_mm_init(get_system_memory(), addr, 2,
494 qdev_get_gpio_in(DEVICE(&s->gic), uart_irqs[i]),
495 115200, serial_hd(i), DEVICE_NATIVE_ENDIAN);
496 }
497
498 /* I2C */
499 sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
500 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, s->memmap[AW_R40_DEV_TWI0]);
501 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0,
502 qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_TWI0));
503
504 /* DRAMC */
505 sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
506 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0,
507 s->memmap[AW_R40_DEV_DRAMCOM]);
508 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1,
509 s->memmap[AW_R40_DEV_DRAMCTL]);
510 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2,
511 s->memmap[AW_R40_DEV_DRAMPHY]);
512
513 /* nic support gmac and emac */
514 for (int i = 0; i < ARRAY_SIZE(r40_nic_models) - 1; i++) {
515 NICInfo *nic = &nd_table[i];
516
517 if (!nic->used) {
518 continue;
519 }
520 if (qemu_show_nic_models(nic->model, r40_nic_models)) {
521 exit(0);
522 }
523
524 switch (qemu_find_nic_model(nic, r40_nic_models, r40_nic_models[0])) {
525 case 0: /* gmac */
526 qdev_set_nic_properties(DEVICE(&s->gmac), nic);
527 break;
528 case 1: /* emac */
529 qdev_set_nic_properties(DEVICE(&s->emac), nic);
530 break;
531 default:
532 exit(1);
533 break;
534 }
535 }
536
537 /* GMAC */
538 object_property_set_link(OBJECT(&s->gmac), "dma-memory",
539 OBJECT(get_system_memory()), &error_fatal);
540 sysbus_realize(SYS_BUS_DEVICE(&s->gmac), &error_fatal);
541 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gmac), 0, s->memmap[AW_R40_DEV_GMAC]);
542 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gmac), 0,
543 qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_GMAC));
544
545 /* EMAC */
546 sysbus_realize(SYS_BUS_DEVICE(&s->emac), &error_fatal);
547 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_R40_DEV_EMAC]);
548 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
549 qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_EMAC));
550
551 /* WDT */
552 sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_fatal);
553 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->wdt), 0,
554 allwinner_r40_memmap[AW_R40_DEV_WDT], 1);
555
556 /* Unimplemented devices */
557 for (unsigned i = 0; i < ARRAY_SIZE(r40_unimplemented); i++) {
558 create_unimplemented_device(r40_unimplemented[i].device_name,
559 r40_unimplemented[i].base,
560 r40_unimplemented[i].size);
561 }
562 }
563
564 static void allwinner_r40_class_init(ObjectClass *oc, void *data)
565 {
566 DeviceClass *dc = DEVICE_CLASS(oc);
567
568 dc->realize = allwinner_r40_realize;
569 /* Reason: uses serial_hd() in realize function */
570 dc->user_creatable = false;
571 }
572
573 static const TypeInfo allwinner_r40_type_info = {
574 .name = TYPE_AW_R40,
575 .parent = TYPE_DEVICE,
576 .instance_size = sizeof(AwR40State),
577 .instance_init = allwinner_r40_init,
578 .class_init = allwinner_r40_class_init,
579 };
580
581 static void allwinner_r40_register_types(void)
582 {
583 type_register_static(&allwinner_r40_type_info);
584 }
585
586 type_init(allwinner_r40_register_types)
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