2 * Arm SSE (Subsystems for Embedded): IoTKit
4 * Copyright (c) 2018 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
12 #include "qemu/osdep.h"
14 #include "qemu/module.h"
15 #include "qemu/bitops.h"
16 #include "qapi/error.h"
18 #include "hw/sysbus.h"
19 #include "migration/vmstate.h"
20 #include "hw/registerfields.h"
21 #include "hw/arm/armsse.h"
22 #include "hw/arm/boot.h"
25 /* Format of the System Information block SYS_CONFIG register */
26 typedef enum SysConfigFormat
{
37 SysConfigFormat sys_config_format
;
46 static Property iotkit_properties
[] = {
47 DEFINE_PROP_LINK("memory", ARMSSE
, board_memory
, TYPE_MEMORY_REGION
,
49 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE
, exp_numirq
, 64),
50 DEFINE_PROP_UINT32("MAINCLK", ARMSSE
, mainclk_frq
, 0),
51 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE
, sram_addr_width
, 15),
52 DEFINE_PROP_UINT32("init-svtor", ARMSSE
, init_svtor
, 0x10000000),
53 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE
, cpu_fpu
[0], true),
54 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE
, cpu_dsp
[0], true),
55 DEFINE_PROP_END_OF_LIST()
58 static Property armsse_properties
[] = {
59 DEFINE_PROP_LINK("memory", ARMSSE
, board_memory
, TYPE_MEMORY_REGION
,
61 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE
, exp_numirq
, 64),
62 DEFINE_PROP_UINT32("MAINCLK", ARMSSE
, mainclk_frq
, 0),
63 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE
, sram_addr_width
, 15),
64 DEFINE_PROP_UINT32("init-svtor", ARMSSE
, init_svtor
, 0x10000000),
65 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE
, cpu_fpu
[0], false),
66 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE
, cpu_dsp
[0], false),
67 DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE
, cpu_fpu
[1], true),
68 DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE
, cpu_dsp
[1], true),
69 DEFINE_PROP_END_OF_LIST()
72 static const ARMSSEInfo armsse_variants
[] = {
77 .sys_version
= 0x41743,
79 .sys_config_format
= IoTKitFormat
,
82 .has_cachectrl
= false,
83 .has_cpusecctrl
= false,
85 .props
= iotkit_properties
,
91 .sys_version
= 0x22041743,
93 .sys_config_format
= SSE200Format
,
96 .has_cachectrl
= true,
97 .has_cpusecctrl
= true,
99 .props
= armsse_properties
,
103 static uint32_t armsse_sys_config_value(ARMSSE
*s
, const ARMSSEInfo
*info
)
105 /* Return the SYS_CONFIG value for this SSE */
108 switch (info
->sys_config_format
) {
111 sys_config
= deposit32(sys_config
, 0, 4, info
->sram_banks
);
112 sys_config
= deposit32(sys_config
, 4, 4, s
->sram_addr_width
- 12);
116 sys_config
= deposit32(sys_config
, 0, 4, info
->sram_banks
);
117 sys_config
= deposit32(sys_config
, 4, 5, s
->sram_addr_width
);
118 sys_config
= deposit32(sys_config
, 24, 4, 2);
119 if (info
->num_cpus
> 1) {
120 sys_config
= deposit32(sys_config
, 10, 1, 1);
121 sys_config
= deposit32(sys_config
, 20, 4, info
->sram_banks
- 1);
122 sys_config
= deposit32(sys_config
, 28, 4, 2);
126 g_assert_not_reached();
131 /* Clock frequency in HZ of the 32KHz "slow clock" */
132 #define S32KCLK (32 * 1000)
134 /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */
135 static bool irq_is_common
[32] = {
137 /* 6, 7: per-CPU MHU interrupts */
139 /* 13: per-CPU icache interrupt */
145 /* 28, 29: per-CPU CTI interrupts */
146 /* 30, 31: reserved */
150 * Create an alias region in @container of @size bytes starting at @base
151 * which mirrors the memory starting at @orig.
153 static void make_alias(ARMSSE
*s
, MemoryRegion
*mr
, MemoryRegion
*container
,
154 const char *name
, hwaddr base
, hwaddr size
, hwaddr orig
)
156 memory_region_init_alias(mr
, NULL
, name
, container
, orig
, size
);
157 /* The alias is even lower priority than unimplemented_device regions */
158 memory_region_add_subregion_overlap(container
, base
, mr
, -1500);
161 static void irq_status_forwarder(void *opaque
, int n
, int level
)
163 qemu_irq destirq
= opaque
;
165 qemu_set_irq(destirq
, level
);
168 static void nsccfg_handler(void *opaque
, int n
, int level
)
170 ARMSSE
*s
= ARMSSE(opaque
);
175 static void armsse_forward_ppc(ARMSSE
*s
, const char *ppcname
, int ppcnum
)
177 /* Each of the 4 AHB and 4 APB PPCs that might be present in a
178 * system using the ARMSSE has a collection of control lines which
179 * are provided by the security controller and which we want to
180 * expose as control lines on the ARMSSE device itself, so the
181 * code using the ARMSSE can wire them up to the PPCs.
183 SplitIRQ
*splitter
= &s
->ppc_irq_splitter
[ppcnum
];
184 DeviceState
*armssedev
= DEVICE(s
);
185 DeviceState
*dev_secctl
= DEVICE(&s
->secctl
);
186 DeviceState
*dev_splitter
= DEVICE(splitter
);
189 name
= g_strdup_printf("%s_nonsec", ppcname
);
190 qdev_pass_gpios(dev_secctl
, armssedev
, name
);
192 name
= g_strdup_printf("%s_ap", ppcname
);
193 qdev_pass_gpios(dev_secctl
, armssedev
, name
);
195 name
= g_strdup_printf("%s_irq_enable", ppcname
);
196 qdev_pass_gpios(dev_secctl
, armssedev
, name
);
198 name
= g_strdup_printf("%s_irq_clear", ppcname
);
199 qdev_pass_gpios(dev_secctl
, armssedev
, name
);
202 /* irq_status is a little more tricky, because we need to
203 * split it so we can send it both to the security controller
204 * and to our OR gate for the NVIC interrupt line.
205 * Connect up the splitter's outputs, and create a GPIO input
206 * which will pass the line state to the input splitter.
208 name
= g_strdup_printf("%s_irq_status", ppcname
);
209 qdev_connect_gpio_out(dev_splitter
, 0,
210 qdev_get_gpio_in_named(dev_secctl
,
212 qdev_connect_gpio_out(dev_splitter
, 1,
213 qdev_get_gpio_in(DEVICE(&s
->ppc_irq_orgate
), ppcnum
));
214 s
->irq_status_in
[ppcnum
] = qdev_get_gpio_in(dev_splitter
, 0);
215 qdev_init_gpio_in_named_with_opaque(armssedev
, irq_status_forwarder
,
216 s
->irq_status_in
[ppcnum
], name
, 1);
220 static void armsse_forward_sec_resp_cfg(ARMSSE
*s
)
222 /* Forward the 3rd output from the splitter device as a
223 * named GPIO output of the armsse object.
225 DeviceState
*dev
= DEVICE(s
);
226 DeviceState
*dev_splitter
= DEVICE(&s
->sec_resp_splitter
);
228 qdev_init_gpio_out_named(dev
, &s
->sec_resp_cfg
, "sec_resp_cfg", 1);
229 s
->sec_resp_cfg_in
= qemu_allocate_irq(irq_status_forwarder
,
231 qdev_connect_gpio_out(dev_splitter
, 2, s
->sec_resp_cfg_in
);
234 static void armsse_init(Object
*obj
)
236 ARMSSE
*s
= ARMSSE(obj
);
237 ARMSSEClass
*asc
= ARMSSE_GET_CLASS(obj
);
238 const ARMSSEInfo
*info
= asc
->info
;
241 assert(info
->sram_banks
<= MAX_SRAM_BANKS
);
242 assert(info
->num_cpus
<= SSE_MAX_CPUS
);
244 memory_region_init(&s
->container
, obj
, "armsse-container", UINT64_MAX
);
246 for (i
= 0; i
< info
->num_cpus
; i
++) {
248 * We put each CPU in its own cluster as they are logically
249 * distinct and may be configured differently.
253 name
= g_strdup_printf("cluster%d", i
);
254 object_initialize_child(obj
, name
, &s
->cluster
[i
], TYPE_CPU_CLUSTER
);
255 qdev_prop_set_uint32(DEVICE(&s
->cluster
[i
]), "cluster-id", i
);
258 name
= g_strdup_printf("armv7m%d", i
);
259 object_initialize_child(OBJECT(&s
->cluster
[i
]), name
, &s
->armv7m
[i
],
261 qdev_prop_set_string(DEVICE(&s
->armv7m
[i
]), "cpu-type",
262 ARM_CPU_TYPE_NAME("cortex-m33"));
264 name
= g_strdup_printf("arm-sse-cpu-container%d", i
);
265 memory_region_init(&s
->cpu_container
[i
], obj
, name
, UINT64_MAX
);
268 name
= g_strdup_printf("arm-sse-container-alias%d", i
);
269 memory_region_init_alias(&s
->container_alias
[i
- 1], obj
,
270 name
, &s
->container
, 0, UINT64_MAX
);
275 object_initialize_child(obj
, "secctl", &s
->secctl
, TYPE_IOTKIT_SECCTL
);
276 object_initialize_child(obj
, "apb-ppc0", &s
->apb_ppc0
, TYPE_TZ_PPC
);
277 object_initialize_child(obj
, "apb-ppc1", &s
->apb_ppc1
, TYPE_TZ_PPC
);
278 for (i
= 0; i
< info
->sram_banks
; i
++) {
279 char *name
= g_strdup_printf("mpc%d", i
);
280 object_initialize_child(obj
, name
, &s
->mpc
[i
], TYPE_TZ_MPC
);
283 object_initialize_child(obj
, "mpc-irq-orgate", &s
->mpc_irq_orgate
,
286 for (i
= 0; i
< IOTS_NUM_EXP_MPC
+ info
->sram_banks
; i
++) {
287 char *name
= g_strdup_printf("mpc-irq-splitter-%d", i
);
288 SplitIRQ
*splitter
= &s
->mpc_irq_splitter
[i
];
290 object_initialize_child(obj
, name
, splitter
, TYPE_SPLIT_IRQ
);
293 object_initialize_child(obj
, "timer0", &s
->timer0
, TYPE_CMSDK_APB_TIMER
);
294 object_initialize_child(obj
, "timer1", &s
->timer1
, TYPE_CMSDK_APB_TIMER
);
295 object_initialize_child(obj
, "s32ktimer", &s
->s32ktimer
,
296 TYPE_CMSDK_APB_TIMER
);
297 object_initialize_child(obj
, "dualtimer", &s
->dualtimer
,
298 TYPE_CMSDK_APB_DUALTIMER
);
299 object_initialize_child(obj
, "s32kwatchdog", &s
->s32kwatchdog
,
300 TYPE_CMSDK_APB_WATCHDOG
);
301 object_initialize_child(obj
, "nswatchdog", &s
->nswatchdog
,
302 TYPE_CMSDK_APB_WATCHDOG
);
303 object_initialize_child(obj
, "swatchdog", &s
->swatchdog
,
304 TYPE_CMSDK_APB_WATCHDOG
);
305 object_initialize_child(obj
, "armsse-sysctl", &s
->sysctl
,
307 object_initialize_child(obj
, "armsse-sysinfo", &s
->sysinfo
,
308 TYPE_IOTKIT_SYSINFO
);
309 if (info
->has_mhus
) {
310 object_initialize_child(obj
, "mhu0", &s
->mhu
[0], TYPE_ARMSSE_MHU
);
311 object_initialize_child(obj
, "mhu1", &s
->mhu
[1], TYPE_ARMSSE_MHU
);
313 if (info
->has_ppus
) {
314 for (i
= 0; i
< info
->num_cpus
; i
++) {
315 char *name
= g_strdup_printf("CPU%dCORE_PPU", i
);
316 int ppuidx
= CPU0CORE_PPU
+ i
;
318 object_initialize_child(obj
, name
, &s
->ppu
[ppuidx
],
319 TYPE_UNIMPLEMENTED_DEVICE
);
322 object_initialize_child(obj
, "DBG_PPU", &s
->ppu
[DBG_PPU
],
323 TYPE_UNIMPLEMENTED_DEVICE
);
324 for (i
= 0; i
< info
->sram_banks
; i
++) {
325 char *name
= g_strdup_printf("RAM%d_PPU", i
);
326 int ppuidx
= RAM0_PPU
+ i
;
328 object_initialize_child(obj
, name
, &s
->ppu
[ppuidx
],
329 TYPE_UNIMPLEMENTED_DEVICE
);
333 if (info
->has_cachectrl
) {
334 for (i
= 0; i
< info
->num_cpus
; i
++) {
335 char *name
= g_strdup_printf("cachectrl%d", i
);
337 object_initialize_child(obj
, name
, &s
->cachectrl
[i
],
338 TYPE_UNIMPLEMENTED_DEVICE
);
342 if (info
->has_cpusecctrl
) {
343 for (i
= 0; i
< info
->num_cpus
; i
++) {
344 char *name
= g_strdup_printf("cpusecctrl%d", i
);
346 object_initialize_child(obj
, name
, &s
->cpusecctrl
[i
],
347 TYPE_UNIMPLEMENTED_DEVICE
);
351 if (info
->has_cpuid
) {
352 for (i
= 0; i
< info
->num_cpus
; i
++) {
353 char *name
= g_strdup_printf("cpuid%d", i
);
355 object_initialize_child(obj
, name
, &s
->cpuid
[i
],
360 object_initialize_child(obj
, "nmi-orgate", &s
->nmi_orgate
, TYPE_OR_IRQ
);
361 object_initialize_child(obj
, "ppc-irq-orgate", &s
->ppc_irq_orgate
,
363 object_initialize_child(obj
, "sec-resp-splitter", &s
->sec_resp_splitter
,
365 for (i
= 0; i
< ARRAY_SIZE(s
->ppc_irq_splitter
); i
++) {
366 char *name
= g_strdup_printf("ppc-irq-splitter-%d", i
);
367 SplitIRQ
*splitter
= &s
->ppc_irq_splitter
[i
];
369 object_initialize_child(obj
, name
, splitter
, TYPE_SPLIT_IRQ
);
372 if (info
->num_cpus
> 1) {
373 for (i
= 0; i
< ARRAY_SIZE(s
->cpu_irq_splitter
); i
++) {
374 if (irq_is_common
[i
]) {
375 char *name
= g_strdup_printf("cpu-irq-splitter%d", i
);
376 SplitIRQ
*splitter
= &s
->cpu_irq_splitter
[i
];
378 object_initialize_child(obj
, name
, splitter
, TYPE_SPLIT_IRQ
);
385 static void armsse_exp_irq(void *opaque
, int n
, int level
)
387 qemu_irq
*irqarray
= opaque
;
389 qemu_set_irq(irqarray
[n
], level
);
392 static void armsse_mpcexp_status(void *opaque
, int n
, int level
)
394 ARMSSE
*s
= ARMSSE(opaque
);
395 qemu_set_irq(s
->mpcexp_status_in
[n
], level
);
398 static qemu_irq
armsse_get_common_irq_in(ARMSSE
*s
, int irqno
)
401 * Return a qemu_irq which can be used to signal IRQ n to
402 * all CPUs in the SSE.
404 ARMSSEClass
*asc
= ARMSSE_GET_CLASS(s
);
405 const ARMSSEInfo
*info
= asc
->info
;
407 assert(irq_is_common
[irqno
]);
409 if (info
->num_cpus
== 1) {
410 /* Only one CPU -- just connect directly to it */
411 return qdev_get_gpio_in(DEVICE(&s
->armv7m
[0]), irqno
);
413 /* Connect to the splitter which feeds all CPUs */
414 return qdev_get_gpio_in(DEVICE(&s
->cpu_irq_splitter
[irqno
]), 0);
418 static void map_ppu(ARMSSE
*s
, int ppuidx
, const char *name
, hwaddr addr
)
420 /* Map a PPU unimplemented device stub */
421 DeviceState
*dev
= DEVICE(&s
->ppu
[ppuidx
]);
423 qdev_prop_set_string(dev
, "name", name
);
424 qdev_prop_set_uint64(dev
, "size", 0x1000);
425 sysbus_realize(SYS_BUS_DEVICE(dev
), &error_fatal
);
426 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ppu
[ppuidx
]), 0, addr
);
429 static void armsse_realize(DeviceState
*dev
, Error
**errp
)
431 ARMSSE
*s
= ARMSSE(dev
);
432 ARMSSEClass
*asc
= ARMSSE_GET_CLASS(dev
);
433 const ARMSSEInfo
*info
= asc
->info
;
437 SysBusDevice
*sbd_apb_ppc0
;
438 SysBusDevice
*sbd_secctl
;
439 DeviceState
*dev_apb_ppc0
;
440 DeviceState
*dev_apb_ppc1
;
441 DeviceState
*dev_secctl
;
442 DeviceState
*dev_splitter
;
443 uint32_t addr_width_max
;
445 if (!s
->board_memory
) {
446 error_setg(errp
, "memory property was not set");
450 if (!s
->mainclk_frq
) {
451 error_setg(errp
, "MAINCLK property was not set");
455 /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */
456 assert(is_power_of_2(info
->sram_banks
));
457 addr_width_max
= 24 - ctz32(info
->sram_banks
);
458 if (s
->sram_addr_width
< 1 || s
->sram_addr_width
> addr_width_max
) {
459 error_setg(errp
, "SRAM_ADDR_WIDTH must be between 1 and %d",
464 /* Handling of which devices should be available only to secure
465 * code is usually done differently for M profile than for A profile.
466 * Instead of putting some devices only into the secure address space,
467 * devices exist in both address spaces but with hard-wired security
468 * permissions that will cause the CPU to fault for non-secure accesses.
470 * The ARMSSE has an IDAU (Implementation Defined Access Unit),
471 * which specifies hard-wired security permissions for different
472 * areas of the physical address space. For the ARMSSE IDAU, the
473 * top 4 bits of the physical address are the IDAU region ID, and
474 * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS
475 * region, otherwise it is an S region.
477 * The various devices and RAMs are generally all mapped twice,
478 * once into a region that the IDAU defines as secure and once
479 * into a non-secure region. They sit behind either a Memory
480 * Protection Controller (for RAM) or a Peripheral Protection
481 * Controller (for devices), which allow a more fine grained
482 * configuration of whether non-secure accesses are permitted.
484 * (The other place that guest software can configure security
485 * permissions is in the architected SAU (Security Attribution
486 * Unit), which is entirely inside the CPU. The IDAU can upgrade
487 * the security attributes for a region to more restrictive than
488 * the SAU specifies, but cannot downgrade them.)
490 * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff
491 * 0x20000000..0x2007ffff 32KB FPGA block RAM
492 * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff
493 * 0x40000000..0x4000ffff base peripheral region 1
494 * 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE)
495 * 0x40020000..0x4002ffff system control element peripherals
496 * 0x40080000..0x400fffff base peripheral region 2
497 * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff
500 memory_region_add_subregion_overlap(&s
->container
, 0, s
->board_memory
, -2);
502 for (i
= 0; i
< info
->num_cpus
; i
++) {
503 DeviceState
*cpudev
= DEVICE(&s
->armv7m
[i
]);
504 Object
*cpuobj
= OBJECT(&s
->armv7m
[i
]);
508 qdev_prop_set_uint32(cpudev
, "num-irq", s
->exp_numirq
+ 32);
510 * In real hardware the initial Secure VTOR is set from the INITSVTOR*
511 * registers in the IoT Kit System Control Register block. In QEMU
512 * we set the initial value here, and also the reset value of the
513 * sysctl register, from this object's QOM init-svtor property.
514 * If the guest changes the INITSVTOR* registers at runtime then the
515 * code in iotkit-sysctl.c will update the CPU init-svtor property
516 * (which will then take effect on the next CPU warm-reset).
518 * Note that typically a board using the SSE-200 will have a system
519 * control processor whose boot firmware initializes the INITSVTOR*
520 * registers before powering up the CPUs. QEMU doesn't emulate
521 * the control processor, so instead we behave in the way that the
522 * firmware does: the initial value should be set by the board code
523 * (using the init-svtor property on the ARMSSE object) to match
524 * whatever its firmware does.
526 qdev_prop_set_uint32(cpudev
, "init-svtor", s
->init_svtor
);
528 * CPUs start powered down if the corresponding bit in the CPUWAIT
529 * register is 1. In real hardware the CPUWAIT register reset value is
530 * a configurable property of the SSE-200 (via the CPUWAIT0_RST and
531 * CPUWAIT1_RST parameters), but since all the boards we care about
532 * start CPU0 and leave CPU1 powered off, we hard-code that in
533 * info->cpuwait_rst for now. We can add QOM properties for this
534 * later if necessary.
536 if (extract32(info
->cpuwait_rst
, i
, 1)) {
537 if (!object_property_set_bool(cpuobj
, "start-powered-off", true,
542 if (!s
->cpu_fpu
[i
]) {
543 if (!object_property_set_bool(cpuobj
, "vfp", false, errp
)) {
547 if (!s
->cpu_dsp
[i
]) {
548 if (!object_property_set_bool(cpuobj
, "dsp", false, errp
)) {
554 memory_region_add_subregion_overlap(&s
->cpu_container
[i
], 0,
555 &s
->container_alias
[i
- 1], -1);
557 memory_region_add_subregion_overlap(&s
->cpu_container
[i
], 0,
560 object_property_set_link(cpuobj
, "memory",
561 OBJECT(&s
->cpu_container
[i
]), &error_abort
);
562 object_property_set_link(cpuobj
, "idau", OBJECT(s
), &error_abort
);
563 if (!sysbus_realize(SYS_BUS_DEVICE(cpuobj
), errp
)) {
567 * The cluster must be realized after the armv7m container, as
568 * the container's CPU object is only created on realize, and the
569 * CPU must exist and have been parented into the cluster before
570 * the cluster is realized.
572 if (!qdev_realize(DEVICE(&s
->cluster
[i
]), NULL
, errp
)) {
576 /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */
577 s
->exp_irqs
[i
] = g_new(qemu_irq
, s
->exp_numirq
);
578 for (j
= 0; j
< s
->exp_numirq
; j
++) {
579 s
->exp_irqs
[i
][j
] = qdev_get_gpio_in(cpudev
, j
+ 32);
582 gpioname
= g_strdup("EXP_IRQ");
584 gpioname
= g_strdup_printf("EXP_CPU%d_IRQ", i
);
586 qdev_init_gpio_in_named_with_opaque(dev
, armsse_exp_irq
,
588 gpioname
, s
->exp_numirq
);
592 /* Wire up the splitters that connect common IRQs to all CPUs */
593 if (info
->num_cpus
> 1) {
594 for (i
= 0; i
< ARRAY_SIZE(s
->cpu_irq_splitter
); i
++) {
595 if (irq_is_common
[i
]) {
596 Object
*splitter
= OBJECT(&s
->cpu_irq_splitter
[i
]);
597 DeviceState
*devs
= DEVICE(splitter
);
600 if (!object_property_set_int(splitter
, "num-lines",
601 info
->num_cpus
, errp
)) {
604 if (!qdev_realize(DEVICE(splitter
), NULL
, errp
)) {
607 for (cpunum
= 0; cpunum
< info
->num_cpus
; cpunum
++) {
608 DeviceState
*cpudev
= DEVICE(&s
->armv7m
[cpunum
]);
610 qdev_connect_gpio_out(devs
, cpunum
,
611 qdev_get_gpio_in(cpudev
, i
));
617 /* Set up the big aliases first */
618 make_alias(s
, &s
->alias1
, &s
->container
, "alias 1",
619 0x10000000, 0x10000000, 0x00000000);
620 make_alias(s
, &s
->alias2
, &s
->container
,
621 "alias 2", 0x30000000, 0x10000000, 0x20000000);
622 /* The 0x50000000..0x5fffffff region is not a pure alias: it has
623 * a few extra devices that only appear there (generally the
624 * control interfaces for the protection controllers).
625 * We implement this by mapping those devices over the top of this
626 * alias MR at a higher priority. Some of the devices in this range
627 * are per-CPU, so we must put this alias in the per-cpu containers.
629 for (i
= 0; i
< info
->num_cpus
; i
++) {
630 make_alias(s
, &s
->alias3
[i
], &s
->cpu_container
[i
],
631 "alias 3", 0x50000000, 0x10000000, 0x40000000);
634 /* Security controller */
635 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->secctl
), errp
)) {
638 sbd_secctl
= SYS_BUS_DEVICE(&s
->secctl
);
639 dev_secctl
= DEVICE(&s
->secctl
);
640 sysbus_mmio_map(sbd_secctl
, 0, 0x50080000);
641 sysbus_mmio_map(sbd_secctl
, 1, 0x40080000);
643 s
->nsc_cfg_in
= qemu_allocate_irq(nsccfg_handler
, s
, 1);
644 qdev_connect_gpio_out_named(dev_secctl
, "nsc_cfg", 0, s
->nsc_cfg_in
);
646 /* The sec_resp_cfg output from the security controller must be split into
647 * multiple lines, one for each of the PPCs within the ARMSSE and one
648 * that will be an output from the ARMSSE to the system.
650 if (!object_property_set_int(OBJECT(&s
->sec_resp_splitter
),
651 "num-lines", 3, errp
)) {
654 if (!qdev_realize(DEVICE(&s
->sec_resp_splitter
), NULL
, errp
)) {
657 dev_splitter
= DEVICE(&s
->sec_resp_splitter
);
658 qdev_connect_gpio_out_named(dev_secctl
, "sec_resp_cfg", 0,
659 qdev_get_gpio_in(dev_splitter
, 0));
661 /* Each SRAM bank lives behind its own Memory Protection Controller */
662 for (i
= 0; i
< info
->sram_banks
; i
++) {
663 char *ramname
= g_strdup_printf("armsse.sram%d", i
);
664 SysBusDevice
*sbd_mpc
;
665 uint32_t sram_bank_size
= 1 << s
->sram_addr_width
;
667 memory_region_init_ram(&s
->sram
[i
], NULL
, ramname
,
668 sram_bank_size
, &err
);
671 error_propagate(errp
, err
);
674 object_property_set_link(OBJECT(&s
->mpc
[i
]), "downstream",
675 OBJECT(&s
->sram
[i
]), &error_abort
);
676 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->mpc
[i
]), errp
)) {
679 /* Map the upstream end of the MPC into the right place... */
680 sbd_mpc
= SYS_BUS_DEVICE(&s
->mpc
[i
]);
681 memory_region_add_subregion(&s
->container
,
682 0x20000000 + i
* sram_bank_size
,
683 sysbus_mmio_get_region(sbd_mpc
, 1));
684 /* ...and its register interface */
685 memory_region_add_subregion(&s
->container
, 0x50083000 + i
* 0x1000,
686 sysbus_mmio_get_region(sbd_mpc
, 0));
689 /* We must OR together lines from the MPC splitters to go to the NVIC */
690 if (!object_property_set_int(OBJECT(&s
->mpc_irq_orgate
), "num-lines",
691 IOTS_NUM_EXP_MPC
+ info
->sram_banks
,
695 if (!qdev_realize(DEVICE(&s
->mpc_irq_orgate
), NULL
, errp
)) {
698 qdev_connect_gpio_out(DEVICE(&s
->mpc_irq_orgate
), 0,
699 armsse_get_common_irq_in(s
, 9));
701 /* Devices behind APB PPC0:
704 * 0x40002000: dual timer
705 * 0x40003000: MHU0 (SSE-200 only)
706 * 0x40004000: MHU1 (SSE-200 only)
707 * We must configure and realize each downstream device and connect
708 * it to the appropriate PPC port; then we can realize the PPC and
709 * map its upstream ends to the right place in the container.
711 qdev_prop_set_uint32(DEVICE(&s
->timer0
), "pclk-frq", s
->mainclk_frq
);
712 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->timer0
), errp
)) {
715 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->timer0
), 0,
716 armsse_get_common_irq_in(s
, 3));
717 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->timer0
), 0);
718 object_property_set_link(OBJECT(&s
->apb_ppc0
), "port[0]", OBJECT(mr
),
721 qdev_prop_set_uint32(DEVICE(&s
->timer1
), "pclk-frq", s
->mainclk_frq
);
722 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->timer1
), errp
)) {
725 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->timer1
), 0,
726 armsse_get_common_irq_in(s
, 4));
727 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->timer1
), 0);
728 object_property_set_link(OBJECT(&s
->apb_ppc0
), "port[1]", OBJECT(mr
),
731 qdev_prop_set_uint32(DEVICE(&s
->dualtimer
), "pclk-frq", s
->mainclk_frq
);
732 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->dualtimer
), errp
)) {
735 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->dualtimer
), 0,
736 armsse_get_common_irq_in(s
, 5));
737 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->dualtimer
), 0);
738 object_property_set_link(OBJECT(&s
->apb_ppc0
), "port[2]", OBJECT(mr
),
741 if (info
->has_mhus
) {
743 * An SSE-200 with only one CPU should have only one MHU created,
744 * with the region where the second MHU usually is being RAZ/WI.
745 * We don't implement that SSE-200 config; if we want to support
746 * it then this code needs to be enhanced to handle creating the
747 * RAZ/WI region instead of the second MHU.
749 assert(info
->num_cpus
== ARRAY_SIZE(s
->mhu
));
751 for (i
= 0; i
< ARRAY_SIZE(s
->mhu
); i
++) {
754 SysBusDevice
*mhu_sbd
= SYS_BUS_DEVICE(&s
->mhu
[i
]);
756 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->mhu
[i
]), errp
)) {
759 port
= g_strdup_printf("port[%d]", i
+ 3);
760 mr
= sysbus_mmio_get_region(mhu_sbd
, 0);
761 object_property_set_link(OBJECT(&s
->apb_ppc0
), port
, OBJECT(mr
),
766 * Each MHU has an irq line for each CPU:
767 * MHU 0 irq line 0 -> CPU 0 IRQ 6
768 * MHU 0 irq line 1 -> CPU 1 IRQ 6
769 * MHU 1 irq line 0 -> CPU 0 IRQ 7
770 * MHU 1 irq line 1 -> CPU 1 IRQ 7
772 for (cpunum
= 0; cpunum
< info
->num_cpus
; cpunum
++) {
773 DeviceState
*cpudev
= DEVICE(&s
->armv7m
[cpunum
]);
775 sysbus_connect_irq(mhu_sbd
, cpunum
,
776 qdev_get_gpio_in(cpudev
, 6 + i
));
781 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->apb_ppc0
), errp
)) {
785 sbd_apb_ppc0
= SYS_BUS_DEVICE(&s
->apb_ppc0
);
786 dev_apb_ppc0
= DEVICE(&s
->apb_ppc0
);
788 mr
= sysbus_mmio_get_region(sbd_apb_ppc0
, 0);
789 memory_region_add_subregion(&s
->container
, 0x40000000, mr
);
790 mr
= sysbus_mmio_get_region(sbd_apb_ppc0
, 1);
791 memory_region_add_subregion(&s
->container
, 0x40001000, mr
);
792 mr
= sysbus_mmio_get_region(sbd_apb_ppc0
, 2);
793 memory_region_add_subregion(&s
->container
, 0x40002000, mr
);
794 if (info
->has_mhus
) {
795 mr
= sysbus_mmio_get_region(sbd_apb_ppc0
, 3);
796 memory_region_add_subregion(&s
->container
, 0x40003000, mr
);
797 mr
= sysbus_mmio_get_region(sbd_apb_ppc0
, 4);
798 memory_region_add_subregion(&s
->container
, 0x40004000, mr
);
800 for (i
= 0; i
< IOTS_APB_PPC0_NUM_PORTS
; i
++) {
801 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc0_nonsec", i
,
802 qdev_get_gpio_in_named(dev_apb_ppc0
,
804 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc0_ap", i
,
805 qdev_get_gpio_in_named(dev_apb_ppc0
,
808 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc0_irq_enable", 0,
809 qdev_get_gpio_in_named(dev_apb_ppc0
,
811 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc0_irq_clear", 0,
812 qdev_get_gpio_in_named(dev_apb_ppc0
,
814 qdev_connect_gpio_out(dev_splitter
, 0,
815 qdev_get_gpio_in_named(dev_apb_ppc0
,
818 /* All the PPC irq lines (from the 2 internal PPCs and the 8 external
819 * ones) are sent individually to the security controller, and also
820 * ORed together to give a single combined PPC interrupt to the NVIC.
822 if (!object_property_set_int(OBJECT(&s
->ppc_irq_orgate
),
823 "num-lines", NUM_PPCS
, errp
)) {
826 if (!qdev_realize(DEVICE(&s
->ppc_irq_orgate
), NULL
, errp
)) {
829 qdev_connect_gpio_out(DEVICE(&s
->ppc_irq_orgate
), 0,
830 armsse_get_common_irq_in(s
, 10));
833 * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias):
834 * private per-CPU region (all these devices are SSE-200 only):
835 * 0x50010000: L1 icache control registers
836 * 0x50011000: CPUSECCTRL (CPU local security control registers)
837 * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block
839 if (info
->has_cachectrl
) {
840 for (i
= 0; i
< info
->num_cpus
; i
++) {
841 char *name
= g_strdup_printf("cachectrl%d", i
);
844 qdev_prop_set_string(DEVICE(&s
->cachectrl
[i
]), "name", name
);
846 qdev_prop_set_uint64(DEVICE(&s
->cachectrl
[i
]), "size", 0x1000);
847 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->cachectrl
[i
]), errp
)) {
851 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->cachectrl
[i
]), 0);
852 memory_region_add_subregion(&s
->cpu_container
[i
], 0x50010000, mr
);
855 if (info
->has_cpusecctrl
) {
856 for (i
= 0; i
< info
->num_cpus
; i
++) {
857 char *name
= g_strdup_printf("CPUSECCTRL%d", i
);
860 qdev_prop_set_string(DEVICE(&s
->cpusecctrl
[i
]), "name", name
);
862 qdev_prop_set_uint64(DEVICE(&s
->cpusecctrl
[i
]), "size", 0x1000);
863 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->cpusecctrl
[i
]), errp
)) {
867 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->cpusecctrl
[i
]), 0);
868 memory_region_add_subregion(&s
->cpu_container
[i
], 0x50011000, mr
);
871 if (info
->has_cpuid
) {
872 for (i
= 0; i
< info
->num_cpus
; i
++) {
875 qdev_prop_set_uint32(DEVICE(&s
->cpuid
[i
]), "CPUID", i
);
876 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->cpuid
[i
]), errp
)) {
880 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->cpuid
[i
]), 0);
881 memory_region_add_subregion(&s
->cpu_container
[i
], 0x4001F000, mr
);
885 /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */
886 /* Devices behind APB PPC1:
887 * 0x4002f000: S32K timer
889 qdev_prop_set_uint32(DEVICE(&s
->s32ktimer
), "pclk-frq", S32KCLK
);
890 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->s32ktimer
), errp
)) {
893 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->s32ktimer
), 0,
894 armsse_get_common_irq_in(s
, 2));
895 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->s32ktimer
), 0);
896 object_property_set_link(OBJECT(&s
->apb_ppc1
), "port[0]", OBJECT(mr
),
899 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->apb_ppc1
), errp
)) {
902 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->apb_ppc1
), 0);
903 memory_region_add_subregion(&s
->container
, 0x4002f000, mr
);
905 dev_apb_ppc1
= DEVICE(&s
->apb_ppc1
);
906 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc1_nonsec", 0,
907 qdev_get_gpio_in_named(dev_apb_ppc1
,
909 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc1_ap", 0,
910 qdev_get_gpio_in_named(dev_apb_ppc1
,
912 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc1_irq_enable", 0,
913 qdev_get_gpio_in_named(dev_apb_ppc1
,
915 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc1_irq_clear", 0,
916 qdev_get_gpio_in_named(dev_apb_ppc1
,
918 qdev_connect_gpio_out(dev_splitter
, 1,
919 qdev_get_gpio_in_named(dev_apb_ppc1
,
922 if (!object_property_set_int(OBJECT(&s
->sysinfo
), "SYS_VERSION",
923 info
->sys_version
, errp
)) {
926 if (!object_property_set_int(OBJECT(&s
->sysinfo
), "SYS_CONFIG",
927 armsse_sys_config_value(s
, info
), errp
)) {
930 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->sysinfo
), errp
)) {
933 /* System information registers */
934 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sysinfo
), 0, 0x40020000);
935 /* System control registers */
936 object_property_set_int(OBJECT(&s
->sysctl
), "SYS_VERSION",
937 info
->sys_version
, &error_abort
);
938 object_property_set_int(OBJECT(&s
->sysctl
), "CPUWAIT_RST",
939 info
->cpuwait_rst
, &error_abort
);
940 object_property_set_int(OBJECT(&s
->sysctl
), "INITSVTOR0_RST",
941 s
->init_svtor
, &error_abort
);
942 object_property_set_int(OBJECT(&s
->sysctl
), "INITSVTOR1_RST",
943 s
->init_svtor
, &error_abort
);
944 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->sysctl
), errp
)) {
947 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sysctl
), 0, 0x50021000);
949 if (info
->has_ppus
) {
950 /* CPUnCORE_PPU for each CPU */
951 for (i
= 0; i
< info
->num_cpus
; i
++) {
952 char *name
= g_strdup_printf("CPU%dCORE_PPU", i
);
954 map_ppu(s
, CPU0CORE_PPU
+ i
, name
, 0x50023000 + i
* 0x2000);
956 * We don't support CPU debug so don't create the
957 * CPU0DEBUG_PPU at 0x50024000 and 0x50026000.
961 map_ppu(s
, DBG_PPU
, "DBG_PPU", 0x50029000);
963 for (i
= 0; i
< info
->sram_banks
; i
++) {
964 char *name
= g_strdup_printf("RAM%d_PPU", i
);
966 map_ppu(s
, RAM0_PPU
+ i
, name
, 0x5002a000 + i
* 0x1000);
971 /* This OR gate wires together outputs from the secure watchdogs to NMI */
972 if (!object_property_set_int(OBJECT(&s
->nmi_orgate
), "num-lines", 2,
976 if (!qdev_realize(DEVICE(&s
->nmi_orgate
), NULL
, errp
)) {
979 qdev_connect_gpio_out(DEVICE(&s
->nmi_orgate
), 0,
980 qdev_get_gpio_in_named(DEVICE(&s
->armv7m
), "NMI", 0));
982 qdev_prop_set_uint32(DEVICE(&s
->s32kwatchdog
), "wdogclk-frq", S32KCLK
);
983 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->s32kwatchdog
), errp
)) {
986 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->s32kwatchdog
), 0,
987 qdev_get_gpio_in(DEVICE(&s
->nmi_orgate
), 0));
988 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->s32kwatchdog
), 0, 0x5002e000);
990 /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */
992 qdev_prop_set_uint32(DEVICE(&s
->nswatchdog
), "wdogclk-frq", s
->mainclk_frq
);
993 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->nswatchdog
), errp
)) {
996 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->nswatchdog
), 0,
997 armsse_get_common_irq_in(s
, 1));
998 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->nswatchdog
), 0, 0x40081000);
1000 qdev_prop_set_uint32(DEVICE(&s
->swatchdog
), "wdogclk-frq", s
->mainclk_frq
);
1001 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->swatchdog
), errp
)) {
1004 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->swatchdog
), 0,
1005 qdev_get_gpio_in(DEVICE(&s
->nmi_orgate
), 1));
1006 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->swatchdog
), 0, 0x50081000);
1008 for (i
= 0; i
< ARRAY_SIZE(s
->ppc_irq_splitter
); i
++) {
1009 Object
*splitter
= OBJECT(&s
->ppc_irq_splitter
[i
]);
1011 if (!object_property_set_int(splitter
, "num-lines", 2, errp
)) {
1014 if (!qdev_realize(DEVICE(splitter
), NULL
, errp
)) {
1019 for (i
= 0; i
< IOTS_NUM_AHB_EXP_PPC
; i
++) {
1020 char *ppcname
= g_strdup_printf("ahb_ppcexp%d", i
);
1022 armsse_forward_ppc(s
, ppcname
, i
);
1026 for (i
= 0; i
< IOTS_NUM_APB_EXP_PPC
; i
++) {
1027 char *ppcname
= g_strdup_printf("apb_ppcexp%d", i
);
1029 armsse_forward_ppc(s
, ppcname
, i
+ IOTS_NUM_AHB_EXP_PPC
);
1033 for (i
= NUM_EXTERNAL_PPCS
; i
< NUM_PPCS
; i
++) {
1034 /* Wire up IRQ splitter for internal PPCs */
1035 DeviceState
*devs
= DEVICE(&s
->ppc_irq_splitter
[i
]);
1036 char *gpioname
= g_strdup_printf("apb_ppc%d_irq_status",
1037 i
- NUM_EXTERNAL_PPCS
);
1038 TZPPC
*ppc
= (i
== NUM_EXTERNAL_PPCS
) ? &s
->apb_ppc0
: &s
->apb_ppc1
;
1040 qdev_connect_gpio_out(devs
, 0,
1041 qdev_get_gpio_in_named(dev_secctl
, gpioname
, 0));
1042 qdev_connect_gpio_out(devs
, 1,
1043 qdev_get_gpio_in(DEVICE(&s
->ppc_irq_orgate
), i
));
1044 qdev_connect_gpio_out_named(DEVICE(ppc
), "irq", 0,
1045 qdev_get_gpio_in(devs
, 0));
1049 /* Wire up the splitters for the MPC IRQs */
1050 for (i
= 0; i
< IOTS_NUM_EXP_MPC
+ info
->sram_banks
; i
++) {
1051 SplitIRQ
*splitter
= &s
->mpc_irq_splitter
[i
];
1052 DeviceState
*dev_splitter
= DEVICE(splitter
);
1054 if (!object_property_set_int(OBJECT(splitter
), "num-lines", 2,
1058 if (!qdev_realize(DEVICE(splitter
), NULL
, errp
)) {
1062 if (i
< IOTS_NUM_EXP_MPC
) {
1063 /* Splitter input is from GPIO input line */
1064 s
->mpcexp_status_in
[i
] = qdev_get_gpio_in(dev_splitter
, 0);
1065 qdev_connect_gpio_out(dev_splitter
, 0,
1066 qdev_get_gpio_in_named(dev_secctl
,
1067 "mpcexp_status", i
));
1069 /* Splitter input is from our own MPC */
1070 qdev_connect_gpio_out_named(DEVICE(&s
->mpc
[i
- IOTS_NUM_EXP_MPC
]),
1072 qdev_get_gpio_in(dev_splitter
, 0));
1073 qdev_connect_gpio_out(dev_splitter
, 0,
1074 qdev_get_gpio_in_named(dev_secctl
,
1078 qdev_connect_gpio_out(dev_splitter
, 1,
1079 qdev_get_gpio_in(DEVICE(&s
->mpc_irq_orgate
), i
));
1081 /* Create GPIO inputs which will pass the line state for our
1082 * mpcexp_irq inputs to the correct splitter devices.
1084 qdev_init_gpio_in_named(dev
, armsse_mpcexp_status
, "mpcexp_status",
1087 armsse_forward_sec_resp_cfg(s
);
1089 /* Forward the MSC related signals */
1090 qdev_pass_gpios(dev_secctl
, dev
, "mscexp_status");
1091 qdev_pass_gpios(dev_secctl
, dev
, "mscexp_clear");
1092 qdev_pass_gpios(dev_secctl
, dev
, "mscexp_ns");
1093 qdev_connect_gpio_out_named(dev_secctl
, "msc_irq", 0,
1094 armsse_get_common_irq_in(s
, 11));
1097 * Expose our container region to the board model; this corresponds
1098 * to the AHB Slave Expansion ports which allow bus master devices
1099 * (eg DMA controllers) in the board model to make transactions into
1100 * devices in the ARMSSE.
1102 sysbus_init_mmio(SYS_BUS_DEVICE(s
), &s
->container
);
1104 system_clock_scale
= NANOSECONDS_PER_SECOND
/ s
->mainclk_frq
;
1107 static void armsse_idau_check(IDAUInterface
*ii
, uint32_t address
,
1108 int *iregion
, bool *exempt
, bool *ns
, bool *nsc
)
1111 * For ARMSSE systems the IDAU responses are simple logical functions
1112 * of the address bits. The NSC attribute is guest-adjustable via the
1113 * NSCCFG register in the security controller.
1115 ARMSSE
*s
= ARMSSE(ii
);
1116 int region
= extract32(address
, 28, 4);
1118 *ns
= !(region
& 1);
1119 *nsc
= (region
== 1 && (s
->nsccfg
& 1)) || (region
== 3 && (s
->nsccfg
& 2));
1120 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */
1121 *exempt
= (address
& 0xeff00000) == 0xe0000000;
1125 static const VMStateDescription armsse_vmstate
= {
1128 .minimum_version_id
= 1,
1129 .fields
= (VMStateField
[]) {
1130 VMSTATE_UINT32(nsccfg
, ARMSSE
),
1131 VMSTATE_END_OF_LIST()
1135 static void armsse_reset(DeviceState
*dev
)
1137 ARMSSE
*s
= ARMSSE(dev
);
1142 static void armsse_class_init(ObjectClass
*klass
, void *data
)
1144 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1145 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_CLASS(klass
);
1146 ARMSSEClass
*asc
= ARMSSE_CLASS(klass
);
1147 const ARMSSEInfo
*info
= data
;
1149 dc
->realize
= armsse_realize
;
1150 dc
->vmsd
= &armsse_vmstate
;
1151 device_class_set_props(dc
, info
->props
);
1152 dc
->reset
= armsse_reset
;
1153 iic
->check
= armsse_idau_check
;
1157 static const TypeInfo armsse_info
= {
1158 .name
= TYPE_ARMSSE
,
1159 .parent
= TYPE_SYS_BUS_DEVICE
,
1160 .instance_size
= sizeof(ARMSSE
),
1161 .instance_init
= armsse_init
,
1163 .interfaces
= (InterfaceInfo
[]) {
1164 { TYPE_IDAU_INTERFACE
},
1169 static void armsse_register_types(void)
1173 type_register_static(&armsse_info
);
1175 for (i
= 0; i
< ARRAY_SIZE(armsse_variants
); i
++) {
1177 .name
= armsse_variants
[i
].name
,
1178 .parent
= TYPE_ARMSSE
,
1179 .class_init
= armsse_class_init
,
1180 .class_data
= (void *)&armsse_variants
[i
],
1186 type_init(armsse_register_types
);