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hw/arm/armsse: Convert armsse_realize() to use ERRP_GUARD
[mirror_qemu.git] / hw / arm / armsse.c
1 /*
2 * Arm SSE (Subsystems for Embedded): IoTKit
3 *
4 * Copyright (c) 2018 Linaro Limited
5 * Written by Peter Maydell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qemu/log.h"
14 #include "qemu/module.h"
15 #include "qemu/bitops.h"
16 #include "qapi/error.h"
17 #include "trace.h"
18 #include "hw/sysbus.h"
19 #include "migration/vmstate.h"
20 #include "hw/registerfields.h"
21 #include "hw/arm/armsse.h"
22 #include "hw/arm/armsse-version.h"
23 #include "hw/arm/boot.h"
24 #include "hw/irq.h"
25 #include "hw/qdev-clock.h"
26
27 /*
28 * The SSE-300 puts some devices in different places to the
29 * SSE-200 (and original IoTKit). We use an array of these structs
30 * to define how each variant lays out these devices. (Parts of the
31 * SoC that are the same for all variants aren't handled via these
32 * data structures.)
33 */
34
35 #define NO_IRQ -1
36 #define NO_PPC -1
37 /*
38 * Special values for ARMSSEDeviceInfo::irq to indicate that this
39 * device uses one of the inputs to the OR gate that feeds into the
40 * CPU NMI input.
41 */
42 #define NMI_0 10000
43 #define NMI_1 10001
44
45 typedef struct ARMSSEDeviceInfo {
46 const char *name; /* name to use for the QOM object; NULL terminates list */
47 const char *type; /* QOM type name */
48 unsigned int index; /* Which of the N devices of this type is this ? */
49 hwaddr addr;
50 hwaddr size; /* only needed for TYPE_UNIMPLEMENTED_DEVICE */
51 int ppc; /* Index of APB PPC this device is wired up to, or NO_PPC */
52 int ppc_port; /* Port number of this device on the PPC */
53 int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1, or NMI_0 or NMI_1 */
54 bool slowclk; /* true if device uses the slow 32KHz clock */
55 } ARMSSEDeviceInfo;
56
57 struct ARMSSEInfo {
58 const char *name;
59 const char *cpu_type;
60 uint32_t sse_version;
61 int sram_banks;
62 uint32_t sram_bank_base;
63 int num_cpus;
64 uint32_t sys_version;
65 uint32_t iidr;
66 uint32_t cpuwait_rst;
67 bool has_mhus;
68 bool has_cachectrl;
69 bool has_cpusecctrl;
70 bool has_cpuid;
71 bool has_cpu_pwrctrl;
72 bool has_sse_counter;
73 Property *props;
74 const ARMSSEDeviceInfo *devinfo;
75 const bool *irq_is_common;
76 };
77
78 static Property iotkit_properties[] = {
79 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
80 MemoryRegion *),
81 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
82 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
83 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
84 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
85 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
86 DEFINE_PROP_END_OF_LIST()
87 };
88
89 static Property sse200_properties[] = {
90 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
91 MemoryRegion *),
92 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
93 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
94 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
95 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false),
96 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false),
97 DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true),
98 DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true),
99 DEFINE_PROP_END_OF_LIST()
100 };
101
102 static Property sse300_properties[] = {
103 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
104 MemoryRegion *),
105 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
106 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 18),
107 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
108 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
109 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
110 DEFINE_PROP_END_OF_LIST()
111 };
112
113 static const ARMSSEDeviceInfo iotkit_devices[] = {
114 {
115 .name = "timer0",
116 .type = TYPE_CMSDK_APB_TIMER,
117 .index = 0,
118 .addr = 0x40000000,
119 .ppc = 0,
120 .ppc_port = 0,
121 .irq = 3,
122 },
123 {
124 .name = "timer1",
125 .type = TYPE_CMSDK_APB_TIMER,
126 .index = 1,
127 .addr = 0x40001000,
128 .ppc = 0,
129 .ppc_port = 1,
130 .irq = 4,
131 },
132 {
133 .name = "s32ktimer",
134 .type = TYPE_CMSDK_APB_TIMER,
135 .index = 2,
136 .addr = 0x4002f000,
137 .ppc = 1,
138 .ppc_port = 0,
139 .irq = 2,
140 .slowclk = true,
141 },
142 {
143 .name = "dualtimer",
144 .type = TYPE_CMSDK_APB_DUALTIMER,
145 .index = 0,
146 .addr = 0x40002000,
147 .ppc = 0,
148 .ppc_port = 2,
149 .irq = 5,
150 },
151 {
152 .name = "s32kwatchdog",
153 .type = TYPE_CMSDK_APB_WATCHDOG,
154 .index = 0,
155 .addr = 0x5002e000,
156 .ppc = NO_PPC,
157 .irq = NMI_0,
158 .slowclk = true,
159 },
160 {
161 .name = "nswatchdog",
162 .type = TYPE_CMSDK_APB_WATCHDOG,
163 .index = 1,
164 .addr = 0x40081000,
165 .ppc = NO_PPC,
166 .irq = 1,
167 },
168 {
169 .name = "swatchdog",
170 .type = TYPE_CMSDK_APB_WATCHDOG,
171 .index = 2,
172 .addr = 0x50081000,
173 .ppc = NO_PPC,
174 .irq = NMI_1,
175 },
176 {
177 .name = "armsse-sysinfo",
178 .type = TYPE_IOTKIT_SYSINFO,
179 .index = 0,
180 .addr = 0x40020000,
181 .ppc = NO_PPC,
182 .irq = NO_IRQ,
183 },
184 {
185 .name = "armsse-sysctl",
186 .type = TYPE_IOTKIT_SYSCTL,
187 .index = 0,
188 .addr = 0x50021000,
189 .ppc = NO_PPC,
190 .irq = NO_IRQ,
191 },
192 {
193 .name = NULL,
194 }
195 };
196
197 static const ARMSSEDeviceInfo sse200_devices[] = {
198 {
199 .name = "timer0",
200 .type = TYPE_CMSDK_APB_TIMER,
201 .index = 0,
202 .addr = 0x40000000,
203 .ppc = 0,
204 .ppc_port = 0,
205 .irq = 3,
206 },
207 {
208 .name = "timer1",
209 .type = TYPE_CMSDK_APB_TIMER,
210 .index = 1,
211 .addr = 0x40001000,
212 .ppc = 0,
213 .ppc_port = 1,
214 .irq = 4,
215 },
216 {
217 .name = "s32ktimer",
218 .type = TYPE_CMSDK_APB_TIMER,
219 .index = 2,
220 .addr = 0x4002f000,
221 .ppc = 1,
222 .ppc_port = 0,
223 .irq = 2,
224 .slowclk = true,
225 },
226 {
227 .name = "dualtimer",
228 .type = TYPE_CMSDK_APB_DUALTIMER,
229 .index = 0,
230 .addr = 0x40002000,
231 .ppc = 0,
232 .ppc_port = 2,
233 .irq = 5,
234 },
235 {
236 .name = "s32kwatchdog",
237 .type = TYPE_CMSDK_APB_WATCHDOG,
238 .index = 0,
239 .addr = 0x5002e000,
240 .ppc = NO_PPC,
241 .irq = NMI_0,
242 .slowclk = true,
243 },
244 {
245 .name = "nswatchdog",
246 .type = TYPE_CMSDK_APB_WATCHDOG,
247 .index = 1,
248 .addr = 0x40081000,
249 .ppc = NO_PPC,
250 .irq = 1,
251 },
252 {
253 .name = "swatchdog",
254 .type = TYPE_CMSDK_APB_WATCHDOG,
255 .index = 2,
256 .addr = 0x50081000,
257 .ppc = NO_PPC,
258 .irq = NMI_1,
259 },
260 {
261 .name = "armsse-sysinfo",
262 .type = TYPE_IOTKIT_SYSINFO,
263 .index = 0,
264 .addr = 0x40020000,
265 .ppc = NO_PPC,
266 .irq = NO_IRQ,
267 },
268 {
269 .name = "armsse-sysctl",
270 .type = TYPE_IOTKIT_SYSCTL,
271 .index = 0,
272 .addr = 0x50021000,
273 .ppc = NO_PPC,
274 .irq = NO_IRQ,
275 },
276 {
277 .name = "CPU0CORE_PPU",
278 .type = TYPE_UNIMPLEMENTED_DEVICE,
279 .index = 0,
280 .addr = 0x50023000,
281 .size = 0x1000,
282 .ppc = NO_PPC,
283 .irq = NO_IRQ,
284 },
285 {
286 .name = "CPU1CORE_PPU",
287 .type = TYPE_UNIMPLEMENTED_DEVICE,
288 .index = 1,
289 .addr = 0x50025000,
290 .size = 0x1000,
291 .ppc = NO_PPC,
292 .irq = NO_IRQ,
293 },
294 {
295 .name = "DBG_PPU",
296 .type = TYPE_UNIMPLEMENTED_DEVICE,
297 .index = 2,
298 .addr = 0x50029000,
299 .size = 0x1000,
300 .ppc = NO_PPC,
301 .irq = NO_IRQ,
302 },
303 {
304 .name = "RAM0_PPU",
305 .type = TYPE_UNIMPLEMENTED_DEVICE,
306 .index = 3,
307 .addr = 0x5002a000,
308 .size = 0x1000,
309 .ppc = NO_PPC,
310 .irq = NO_IRQ,
311 },
312 {
313 .name = "RAM1_PPU",
314 .type = TYPE_UNIMPLEMENTED_DEVICE,
315 .index = 4,
316 .addr = 0x5002b000,
317 .size = 0x1000,
318 .ppc = NO_PPC,
319 .irq = NO_IRQ,
320 },
321 {
322 .name = "RAM2_PPU",
323 .type = TYPE_UNIMPLEMENTED_DEVICE,
324 .index = 5,
325 .addr = 0x5002c000,
326 .size = 0x1000,
327 .ppc = NO_PPC,
328 .irq = NO_IRQ,
329 },
330 {
331 .name = "RAM3_PPU",
332 .type = TYPE_UNIMPLEMENTED_DEVICE,
333 .index = 6,
334 .addr = 0x5002d000,
335 .size = 0x1000,
336 .ppc = NO_PPC,
337 .irq = NO_IRQ,
338 },
339 {
340 .name = "SYS_PPU",
341 .type = TYPE_UNIMPLEMENTED_DEVICE,
342 .index = 7,
343 .addr = 0x50022000,
344 .size = 0x1000,
345 .ppc = NO_PPC,
346 .irq = NO_IRQ,
347 },
348 {
349 .name = NULL,
350 }
351 };
352
353 static const ARMSSEDeviceInfo sse300_devices[] = {
354 {
355 .name = "timer0",
356 .type = TYPE_SSE_TIMER,
357 .index = 0,
358 .addr = 0x48000000,
359 .ppc = 0,
360 .ppc_port = 0,
361 .irq = 3,
362 },
363 {
364 .name = "timer1",
365 .type = TYPE_SSE_TIMER,
366 .index = 1,
367 .addr = 0x48001000,
368 .ppc = 0,
369 .ppc_port = 1,
370 .irq = 4,
371 },
372 {
373 .name = "timer2",
374 .type = TYPE_SSE_TIMER,
375 .index = 2,
376 .addr = 0x48002000,
377 .ppc = 0,
378 .ppc_port = 2,
379 .irq = 5,
380 },
381 {
382 .name = "timer3",
383 .type = TYPE_SSE_TIMER,
384 .index = 3,
385 .addr = 0x48003000,
386 .ppc = 0,
387 .ppc_port = 5,
388 .irq = 27,
389 },
390 {
391 .name = "s32ktimer",
392 .type = TYPE_CMSDK_APB_TIMER,
393 .index = 0,
394 .addr = 0x4802f000,
395 .ppc = 1,
396 .ppc_port = 0,
397 .irq = 2,
398 .slowclk = true,
399 },
400 {
401 .name = "s32kwatchdog",
402 .type = TYPE_CMSDK_APB_WATCHDOG,
403 .index = 0,
404 .addr = 0x4802e000,
405 .ppc = NO_PPC,
406 .irq = NMI_0,
407 .slowclk = true,
408 },
409 {
410 .name = "watchdog",
411 .type = TYPE_UNIMPLEMENTED_DEVICE,
412 .index = 0,
413 .addr = 0x48040000,
414 .size = 0x2000,
415 .ppc = NO_PPC,
416 .irq = NO_IRQ,
417 },
418 {
419 .name = "armsse-sysinfo",
420 .type = TYPE_IOTKIT_SYSINFO,
421 .index = 0,
422 .addr = 0x48020000,
423 .ppc = NO_PPC,
424 .irq = NO_IRQ,
425 },
426 {
427 .name = "armsse-sysctl",
428 .type = TYPE_IOTKIT_SYSCTL,
429 .index = 0,
430 .addr = 0x58021000,
431 .ppc = NO_PPC,
432 .irq = NO_IRQ,
433 },
434 {
435 .name = "SYS_PPU",
436 .type = TYPE_UNIMPLEMENTED_DEVICE,
437 .index = 1,
438 .addr = 0x58022000,
439 .size = 0x1000,
440 .ppc = NO_PPC,
441 .irq = NO_IRQ,
442 },
443 {
444 .name = "CPU0CORE_PPU",
445 .type = TYPE_UNIMPLEMENTED_DEVICE,
446 .index = 2,
447 .addr = 0x50023000,
448 .size = 0x1000,
449 .ppc = NO_PPC,
450 .irq = NO_IRQ,
451 },
452 {
453 .name = "MGMT_PPU",
454 .type = TYPE_UNIMPLEMENTED_DEVICE,
455 .index = 3,
456 .addr = 0x50028000,
457 .size = 0x1000,
458 .ppc = NO_PPC,
459 .irq = NO_IRQ,
460 },
461 {
462 .name = "DEBUG_PPU",
463 .type = TYPE_UNIMPLEMENTED_DEVICE,
464 .index = 4,
465 .addr = 0x50029000,
466 .size = 0x1000,
467 .ppc = NO_PPC,
468 .irq = NO_IRQ,
469 },
470 {
471 .name = NULL,
472 }
473 };
474
475 /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */
476 static const bool sse200_irq_is_common[32] = {
477 [0 ... 5] = true,
478 /* 6, 7: per-CPU MHU interrupts */
479 [8 ... 12] = true,
480 /* 13: per-CPU icache interrupt */
481 /* 14: reserved */
482 [15 ... 20] = true,
483 /* 21: reserved */
484 [22 ... 26] = true,
485 /* 27: reserved */
486 /* 28, 29: per-CPU CTI interrupts */
487 /* 30, 31: reserved */
488 };
489
490 static const bool sse300_irq_is_common[32] = {
491 [0 ... 5] = true,
492 /* 6, 7: per-CPU MHU interrupts */
493 [8 ... 12] = true,
494 /* 13: reserved */
495 [14 ... 16] = true,
496 /* 17-25: reserved */
497 [26 ... 27] = true,
498 /* 28, 29: per-CPU CTI interrupts */
499 /* 30, 31: reserved */
500 };
501
502 static const ARMSSEInfo armsse_variants[] = {
503 {
504 .name = TYPE_IOTKIT,
505 .sse_version = ARMSSE_IOTKIT,
506 .cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"),
507 .sram_banks = 1,
508 .sram_bank_base = 0x20000000,
509 .num_cpus = 1,
510 .sys_version = 0x41743,
511 .iidr = 0,
512 .cpuwait_rst = 0,
513 .has_mhus = false,
514 .has_cachectrl = false,
515 .has_cpusecctrl = false,
516 .has_cpuid = false,
517 .has_cpu_pwrctrl = false,
518 .has_sse_counter = false,
519 .props = iotkit_properties,
520 .devinfo = iotkit_devices,
521 .irq_is_common = sse200_irq_is_common,
522 },
523 {
524 .name = TYPE_SSE200,
525 .sse_version = ARMSSE_SSE200,
526 .cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"),
527 .sram_banks = 4,
528 .sram_bank_base = 0x20000000,
529 .num_cpus = 2,
530 .sys_version = 0x22041743,
531 .iidr = 0,
532 .cpuwait_rst = 2,
533 .has_mhus = true,
534 .has_cachectrl = true,
535 .has_cpusecctrl = true,
536 .has_cpuid = true,
537 .has_cpu_pwrctrl = false,
538 .has_sse_counter = false,
539 .props = sse200_properties,
540 .devinfo = sse200_devices,
541 .irq_is_common = sse200_irq_is_common,
542 },
543 {
544 .name = TYPE_SSE300,
545 .sse_version = ARMSSE_SSE300,
546 .cpu_type = ARM_CPU_TYPE_NAME("cortex-m55"),
547 .sram_banks = 2,
548 .sram_bank_base = 0x21000000,
549 .num_cpus = 1,
550 .sys_version = 0x7e00043b,
551 .iidr = 0x74a0043b,
552 .cpuwait_rst = 0,
553 .has_mhus = false,
554 .has_cachectrl = false,
555 .has_cpusecctrl = true,
556 .has_cpuid = true,
557 .has_cpu_pwrctrl = true,
558 .has_sse_counter = true,
559 .props = sse300_properties,
560 .devinfo = sse300_devices,
561 .irq_is_common = sse300_irq_is_common,
562 },
563 };
564
565 static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info)
566 {
567 /* Return the SYS_CONFIG value for this SSE */
568 uint32_t sys_config;
569
570 switch (info->sse_version) {
571 case ARMSSE_IOTKIT:
572 sys_config = 0;
573 sys_config = deposit32(sys_config, 0, 4, info->sram_banks);
574 sys_config = deposit32(sys_config, 4, 4, s->sram_addr_width - 12);
575 break;
576 case ARMSSE_SSE200:
577 sys_config = 0;
578 sys_config = deposit32(sys_config, 0, 4, info->sram_banks);
579 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width);
580 sys_config = deposit32(sys_config, 24, 4, 2);
581 if (info->num_cpus > 1) {
582 sys_config = deposit32(sys_config, 10, 1, 1);
583 sys_config = deposit32(sys_config, 20, 4, info->sram_banks - 1);
584 sys_config = deposit32(sys_config, 28, 4, 2);
585 }
586 break;
587 case ARMSSE_SSE300:
588 sys_config = 0;
589 sys_config = deposit32(sys_config, 0, 4, info->sram_banks);
590 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width);
591 sys_config = deposit32(sys_config, 16, 3, 3); /* CPU0 = Cortex-M55 */
592 break;
593 default:
594 g_assert_not_reached();
595 }
596 return sys_config;
597 }
598
599 /* Clock frequency in HZ of the 32KHz "slow clock" */
600 #define S32KCLK (32 * 1000)
601
602 /*
603 * Create an alias region in @container of @size bytes starting at @base
604 * which mirrors the memory starting at @orig.
605 */
606 static void make_alias(ARMSSE *s, MemoryRegion *mr, MemoryRegion *container,
607 const char *name, hwaddr base, hwaddr size, hwaddr orig)
608 {
609 memory_region_init_alias(mr, NULL, name, container, orig, size);
610 /* The alias is even lower priority than unimplemented_device regions */
611 memory_region_add_subregion_overlap(container, base, mr, -1500);
612 }
613
614 static void irq_status_forwarder(void *opaque, int n, int level)
615 {
616 qemu_irq destirq = opaque;
617
618 qemu_set_irq(destirq, level);
619 }
620
621 static void nsccfg_handler(void *opaque, int n, int level)
622 {
623 ARMSSE *s = ARM_SSE(opaque);
624
625 s->nsccfg = level;
626 }
627
628 static void armsse_forward_ppc(ARMSSE *s, const char *ppcname, int ppcnum)
629 {
630 /* Each of the 4 AHB and 4 APB PPCs that might be present in a
631 * system using the ARMSSE has a collection of control lines which
632 * are provided by the security controller and which we want to
633 * expose as control lines on the ARMSSE device itself, so the
634 * code using the ARMSSE can wire them up to the PPCs.
635 */
636 SplitIRQ *splitter = &s->ppc_irq_splitter[ppcnum];
637 DeviceState *armssedev = DEVICE(s);
638 DeviceState *dev_secctl = DEVICE(&s->secctl);
639 DeviceState *dev_splitter = DEVICE(splitter);
640 char *name;
641
642 name = g_strdup_printf("%s_nonsec", ppcname);
643 qdev_pass_gpios(dev_secctl, armssedev, name);
644 g_free(name);
645 name = g_strdup_printf("%s_ap", ppcname);
646 qdev_pass_gpios(dev_secctl, armssedev, name);
647 g_free(name);
648 name = g_strdup_printf("%s_irq_enable", ppcname);
649 qdev_pass_gpios(dev_secctl, armssedev, name);
650 g_free(name);
651 name = g_strdup_printf("%s_irq_clear", ppcname);
652 qdev_pass_gpios(dev_secctl, armssedev, name);
653 g_free(name);
654
655 /* irq_status is a little more tricky, because we need to
656 * split it so we can send it both to the security controller
657 * and to our OR gate for the NVIC interrupt line.
658 * Connect up the splitter's outputs, and create a GPIO input
659 * which will pass the line state to the input splitter.
660 */
661 name = g_strdup_printf("%s_irq_status", ppcname);
662 qdev_connect_gpio_out(dev_splitter, 0,
663 qdev_get_gpio_in_named(dev_secctl,
664 name, 0));
665 qdev_connect_gpio_out(dev_splitter, 1,
666 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), ppcnum));
667 s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0);
668 qdev_init_gpio_in_named_with_opaque(armssedev, irq_status_forwarder,
669 s->irq_status_in[ppcnum], name, 1);
670 g_free(name);
671 }
672
673 static void armsse_forward_sec_resp_cfg(ARMSSE *s)
674 {
675 /* Forward the 3rd output from the splitter device as a
676 * named GPIO output of the armsse object.
677 */
678 DeviceState *dev = DEVICE(s);
679 DeviceState *dev_splitter = DEVICE(&s->sec_resp_splitter);
680
681 qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1);
682 s->sec_resp_cfg_in = qemu_allocate_irq(irq_status_forwarder,
683 s->sec_resp_cfg, 1);
684 qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in);
685 }
686
687 static void armsse_mainclk_update(void *opaque, ClockEvent event)
688 {
689 ARMSSE *s = ARM_SSE(opaque);
690
691 /*
692 * Set system_clock_scale from our Clock input; this is what
693 * controls the tick rate of the CPU SysTick timer.
694 */
695 system_clock_scale = clock_ticks_to_ns(s->mainclk, 1);
696 }
697
698 static void armsse_init(Object *obj)
699 {
700 ARMSSE *s = ARM_SSE(obj);
701 ARMSSEClass *asc = ARM_SSE_GET_CLASS(obj);
702 const ARMSSEInfo *info = asc->info;
703 const ARMSSEDeviceInfo *devinfo;
704 int i;
705
706 assert(info->sram_banks <= MAX_SRAM_BANKS);
707 assert(info->num_cpus <= SSE_MAX_CPUS);
708
709 s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK",
710 armsse_mainclk_update, s, ClockUpdate);
711 s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL, 0);
712
713 memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX);
714
715 for (i = 0; i < info->num_cpus; i++) {
716 /*
717 * We put each CPU in its own cluster as they are logically
718 * distinct and may be configured differently.
719 */
720 char *name;
721
722 name = g_strdup_printf("cluster%d", i);
723 object_initialize_child(obj, name, &s->cluster[i], TYPE_CPU_CLUSTER);
724 qdev_prop_set_uint32(DEVICE(&s->cluster[i]), "cluster-id", i);
725 g_free(name);
726
727 name = g_strdup_printf("armv7m%d", i);
728 object_initialize_child(OBJECT(&s->cluster[i]), name, &s->armv7m[i],
729 TYPE_ARMV7M);
730 qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", info->cpu_type);
731 g_free(name);
732 name = g_strdup_printf("arm-sse-cpu-container%d", i);
733 memory_region_init(&s->cpu_container[i], obj, name, UINT64_MAX);
734 g_free(name);
735 if (i > 0) {
736 name = g_strdup_printf("arm-sse-container-alias%d", i);
737 memory_region_init_alias(&s->container_alias[i - 1], obj,
738 name, &s->container, 0, UINT64_MAX);
739 g_free(name);
740 }
741 }
742
743 for (devinfo = info->devinfo; devinfo->name; devinfo++) {
744 assert(devinfo->ppc == NO_PPC || devinfo->ppc < ARRAY_SIZE(s->apb_ppc));
745 if (!strcmp(devinfo->type, TYPE_CMSDK_APB_TIMER)) {
746 assert(devinfo->index < ARRAY_SIZE(s->timer));
747 object_initialize_child(obj, devinfo->name,
748 &s->timer[devinfo->index],
749 TYPE_CMSDK_APB_TIMER);
750 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_DUALTIMER)) {
751 assert(devinfo->index == 0);
752 object_initialize_child(obj, devinfo->name, &s->dualtimer,
753 TYPE_CMSDK_APB_DUALTIMER);
754 } else if (!strcmp(devinfo->type, TYPE_SSE_TIMER)) {
755 assert(devinfo->index < ARRAY_SIZE(s->sse_timer));
756 object_initialize_child(obj, devinfo->name,
757 &s->sse_timer[devinfo->index],
758 TYPE_SSE_TIMER);
759 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_WATCHDOG)) {
760 assert(devinfo->index < ARRAY_SIZE(s->cmsdk_watchdog));
761 object_initialize_child(obj, devinfo->name,
762 &s->cmsdk_watchdog[devinfo->index],
763 TYPE_CMSDK_APB_WATCHDOG);
764 } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSINFO)) {
765 assert(devinfo->index == 0);
766 object_initialize_child(obj, devinfo->name, &s->sysinfo,
767 TYPE_IOTKIT_SYSINFO);
768 } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSCTL)) {
769 assert(devinfo->index == 0);
770 object_initialize_child(obj, devinfo->name, &s->sysctl,
771 TYPE_IOTKIT_SYSCTL);
772 } else if (!strcmp(devinfo->type, TYPE_UNIMPLEMENTED_DEVICE)) {
773 assert(devinfo->index < ARRAY_SIZE(s->unimp));
774 object_initialize_child(obj, devinfo->name,
775 &s->unimp[devinfo->index],
776 TYPE_UNIMPLEMENTED_DEVICE);
777 } else {
778 g_assert_not_reached();
779 }
780 }
781
782 object_initialize_child(obj, "secctl", &s->secctl, TYPE_IOTKIT_SECCTL);
783
784 for (i = 0; i < ARRAY_SIZE(s->apb_ppc); i++) {
785 g_autofree char *name = g_strdup_printf("apb-ppc%d", i);
786 object_initialize_child(obj, name, &s->apb_ppc[i], TYPE_TZ_PPC);
787 }
788
789 for (i = 0; i < info->sram_banks; i++) {
790 char *name = g_strdup_printf("mpc%d", i);
791 object_initialize_child(obj, name, &s->mpc[i], TYPE_TZ_MPC);
792 g_free(name);
793 }
794 object_initialize_child(obj, "mpc-irq-orgate", &s->mpc_irq_orgate,
795 TYPE_OR_IRQ);
796
797 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) {
798 char *name = g_strdup_printf("mpc-irq-splitter-%d", i);
799 SplitIRQ *splitter = &s->mpc_irq_splitter[i];
800
801 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ);
802 g_free(name);
803 }
804
805 if (info->has_mhus) {
806 object_initialize_child(obj, "mhu0", &s->mhu[0], TYPE_ARMSSE_MHU);
807 object_initialize_child(obj, "mhu1", &s->mhu[1], TYPE_ARMSSE_MHU);
808 }
809 if (info->has_cachectrl) {
810 for (i = 0; i < info->num_cpus; i++) {
811 char *name = g_strdup_printf("cachectrl%d", i);
812
813 object_initialize_child(obj, name, &s->cachectrl[i],
814 TYPE_UNIMPLEMENTED_DEVICE);
815 g_free(name);
816 }
817 }
818 if (info->has_cpusecctrl) {
819 for (i = 0; i < info->num_cpus; i++) {
820 char *name = g_strdup_printf("cpusecctrl%d", i);
821
822 object_initialize_child(obj, name, &s->cpusecctrl[i],
823 TYPE_UNIMPLEMENTED_DEVICE);
824 g_free(name);
825 }
826 }
827 if (info->has_cpuid) {
828 for (i = 0; i < info->num_cpus; i++) {
829 char *name = g_strdup_printf("cpuid%d", i);
830
831 object_initialize_child(obj, name, &s->cpuid[i],
832 TYPE_ARMSSE_CPUID);
833 g_free(name);
834 }
835 }
836 if (info->has_cpu_pwrctrl) {
837 for (i = 0; i < info->num_cpus; i++) {
838 char *name = g_strdup_printf("cpu_pwrctrl%d", i);
839
840 object_initialize_child(obj, name, &s->cpu_pwrctrl[i],
841 TYPE_ARMSSE_CPU_PWRCTRL);
842 g_free(name);
843 }
844 }
845 if (info->has_sse_counter) {
846 object_initialize_child(obj, "sse-counter", &s->sse_counter,
847 TYPE_SSE_COUNTER);
848 }
849
850 object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, TYPE_OR_IRQ);
851 object_initialize_child(obj, "ppc-irq-orgate", &s->ppc_irq_orgate,
852 TYPE_OR_IRQ);
853 object_initialize_child(obj, "sec-resp-splitter", &s->sec_resp_splitter,
854 TYPE_SPLIT_IRQ);
855 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) {
856 char *name = g_strdup_printf("ppc-irq-splitter-%d", i);
857 SplitIRQ *splitter = &s->ppc_irq_splitter[i];
858
859 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ);
860 g_free(name);
861 }
862 if (info->num_cpus > 1) {
863 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) {
864 if (info->irq_is_common[i]) {
865 char *name = g_strdup_printf("cpu-irq-splitter%d", i);
866 SplitIRQ *splitter = &s->cpu_irq_splitter[i];
867
868 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ);
869 g_free(name);
870 }
871 }
872 }
873 }
874
875 static void armsse_exp_irq(void *opaque, int n, int level)
876 {
877 qemu_irq *irqarray = opaque;
878
879 qemu_set_irq(irqarray[n], level);
880 }
881
882 static void armsse_mpcexp_status(void *opaque, int n, int level)
883 {
884 ARMSSE *s = ARM_SSE(opaque);
885 qemu_set_irq(s->mpcexp_status_in[n], level);
886 }
887
888 static qemu_irq armsse_get_common_irq_in(ARMSSE *s, int irqno)
889 {
890 /*
891 * Return a qemu_irq which can be used to signal IRQ n to
892 * all CPUs in the SSE.
893 */
894 ARMSSEClass *asc = ARM_SSE_GET_CLASS(s);
895 const ARMSSEInfo *info = asc->info;
896
897 assert(info->irq_is_common[irqno]);
898
899 if (info->num_cpus == 1) {
900 /* Only one CPU -- just connect directly to it */
901 return qdev_get_gpio_in(DEVICE(&s->armv7m[0]), irqno);
902 } else {
903 /* Connect to the splitter which feeds all CPUs */
904 return qdev_get_gpio_in(DEVICE(&s->cpu_irq_splitter[irqno]), 0);
905 }
906 }
907
908 static void armsse_realize(DeviceState *dev, Error **errp)
909 {
910 ARMSSE *s = ARM_SSE(dev);
911 ARMSSEClass *asc = ARM_SSE_GET_CLASS(dev);
912 const ARMSSEInfo *info = asc->info;
913 const ARMSSEDeviceInfo *devinfo;
914 int i;
915 MemoryRegion *mr;
916 SysBusDevice *sbd_apb_ppc0;
917 SysBusDevice *sbd_secctl;
918 DeviceState *dev_apb_ppc0;
919 DeviceState *dev_apb_ppc1;
920 DeviceState *dev_secctl;
921 DeviceState *dev_splitter;
922 uint32_t addr_width_max;
923
924 ERRP_GUARD();
925
926 if (!s->board_memory) {
927 error_setg(errp, "memory property was not set");
928 return;
929 }
930
931 if (!clock_has_source(s->mainclk)) {
932 error_setg(errp, "MAINCLK clock was not connected");
933 }
934 if (!clock_has_source(s->s32kclk)) {
935 error_setg(errp, "S32KCLK clock was not connected");
936 }
937
938 assert(info->num_cpus <= SSE_MAX_CPUS);
939
940 /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */
941 assert(is_power_of_2(info->sram_banks));
942 addr_width_max = 24 - ctz32(info->sram_banks);
943 if (s->sram_addr_width < 1 || s->sram_addr_width > addr_width_max) {
944 error_setg(errp, "SRAM_ADDR_WIDTH must be between 1 and %d",
945 addr_width_max);
946 return;
947 }
948
949 /* Handling of which devices should be available only to secure
950 * code is usually done differently for M profile than for A profile.
951 * Instead of putting some devices only into the secure address space,
952 * devices exist in both address spaces but with hard-wired security
953 * permissions that will cause the CPU to fault for non-secure accesses.
954 *
955 * The ARMSSE has an IDAU (Implementation Defined Access Unit),
956 * which specifies hard-wired security permissions for different
957 * areas of the physical address space. For the ARMSSE IDAU, the
958 * top 4 bits of the physical address are the IDAU region ID, and
959 * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS
960 * region, otherwise it is an S region.
961 *
962 * The various devices and RAMs are generally all mapped twice,
963 * once into a region that the IDAU defines as secure and once
964 * into a non-secure region. They sit behind either a Memory
965 * Protection Controller (for RAM) or a Peripheral Protection
966 * Controller (for devices), which allow a more fine grained
967 * configuration of whether non-secure accesses are permitted.
968 *
969 * (The other place that guest software can configure security
970 * permissions is in the architected SAU (Security Attribution
971 * Unit), which is entirely inside the CPU. The IDAU can upgrade
972 * the security attributes for a region to more restrictive than
973 * the SAU specifies, but cannot downgrade them.)
974 *
975 * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff
976 * 0x20000000..0x2007ffff 32KB FPGA block RAM
977 * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff
978 * 0x40000000..0x4000ffff base peripheral region 1
979 * 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE)
980 * 0x40020000..0x4002ffff system control element peripherals
981 * 0x40080000..0x400fffff base peripheral region 2
982 * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff
983 */
984
985 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -2);
986
987 for (i = 0; i < info->num_cpus; i++) {
988 DeviceState *cpudev = DEVICE(&s->armv7m[i]);
989 Object *cpuobj = OBJECT(&s->armv7m[i]);
990 int j;
991 char *gpioname;
992
993 qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + NUM_SSE_IRQS);
994 /*
995 * In real hardware the initial Secure VTOR is set from the INITSVTOR*
996 * registers in the IoT Kit System Control Register block. In QEMU
997 * we set the initial value here, and also the reset value of the
998 * sysctl register, from this object's QOM init-svtor property.
999 * If the guest changes the INITSVTOR* registers at runtime then the
1000 * code in iotkit-sysctl.c will update the CPU init-svtor property
1001 * (which will then take effect on the next CPU warm-reset).
1002 *
1003 * Note that typically a board using the SSE-200 will have a system
1004 * control processor whose boot firmware initializes the INITSVTOR*
1005 * registers before powering up the CPUs. QEMU doesn't emulate
1006 * the control processor, so instead we behave in the way that the
1007 * firmware does: the initial value should be set by the board code
1008 * (using the init-svtor property on the ARMSSE object) to match
1009 * whatever its firmware does.
1010 */
1011 qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor);
1012 /*
1013 * CPUs start powered down if the corresponding bit in the CPUWAIT
1014 * register is 1. In real hardware the CPUWAIT register reset value is
1015 * a configurable property of the SSE-200 (via the CPUWAIT0_RST and
1016 * CPUWAIT1_RST parameters), but since all the boards we care about
1017 * start CPU0 and leave CPU1 powered off, we hard-code that in
1018 * info->cpuwait_rst for now. We can add QOM properties for this
1019 * later if necessary.
1020 */
1021 if (extract32(info->cpuwait_rst, i, 1)) {
1022 if (!object_property_set_bool(cpuobj, "start-powered-off", true,
1023 errp)) {
1024 return;
1025 }
1026 }
1027 if (!s->cpu_fpu[i]) {
1028 if (!object_property_set_bool(cpuobj, "vfp", false, errp)) {
1029 return;
1030 }
1031 }
1032 if (!s->cpu_dsp[i]) {
1033 if (!object_property_set_bool(cpuobj, "dsp", false, errp)) {
1034 return;
1035 }
1036 }
1037
1038 if (i > 0) {
1039 memory_region_add_subregion_overlap(&s->cpu_container[i], 0,
1040 &s->container_alias[i - 1], -1);
1041 } else {
1042 memory_region_add_subregion_overlap(&s->cpu_container[i], 0,
1043 &s->container, -1);
1044 }
1045 object_property_set_link(cpuobj, "memory",
1046 OBJECT(&s->cpu_container[i]), &error_abort);
1047 object_property_set_link(cpuobj, "idau", OBJECT(s), &error_abort);
1048 if (!sysbus_realize(SYS_BUS_DEVICE(cpuobj), errp)) {
1049 return;
1050 }
1051 /*
1052 * The cluster must be realized after the armv7m container, as
1053 * the container's CPU object is only created on realize, and the
1054 * CPU must exist and have been parented into the cluster before
1055 * the cluster is realized.
1056 */
1057 if (!qdev_realize(DEVICE(&s->cluster[i]), NULL, errp)) {
1058 return;
1059 }
1060
1061 /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */
1062 s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq);
1063 for (j = 0; j < s->exp_numirq; j++) {
1064 s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + NUM_SSE_IRQS);
1065 }
1066 if (i == 0) {
1067 gpioname = g_strdup("EXP_IRQ");
1068 } else {
1069 gpioname = g_strdup_printf("EXP_CPU%d_IRQ", i);
1070 }
1071 qdev_init_gpio_in_named_with_opaque(dev, armsse_exp_irq,
1072 s->exp_irqs[i],
1073 gpioname, s->exp_numirq);
1074 g_free(gpioname);
1075 }
1076
1077 /* Wire up the splitters that connect common IRQs to all CPUs */
1078 if (info->num_cpus > 1) {
1079 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) {
1080 if (info->irq_is_common[i]) {
1081 Object *splitter = OBJECT(&s->cpu_irq_splitter[i]);
1082 DeviceState *devs = DEVICE(splitter);
1083 int cpunum;
1084
1085 if (!object_property_set_int(splitter, "num-lines",
1086 info->num_cpus, errp)) {
1087 return;
1088 }
1089 if (!qdev_realize(DEVICE(splitter), NULL, errp)) {
1090 return;
1091 }
1092 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) {
1093 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]);
1094
1095 qdev_connect_gpio_out(devs, cpunum,
1096 qdev_get_gpio_in(cpudev, i));
1097 }
1098 }
1099 }
1100 }
1101
1102 /* Set up the big aliases first */
1103 make_alias(s, &s->alias1, &s->container, "alias 1",
1104 0x10000000, 0x10000000, 0x00000000);
1105 make_alias(s, &s->alias2, &s->container,
1106 "alias 2", 0x30000000, 0x10000000, 0x20000000);
1107 /* The 0x50000000..0x5fffffff region is not a pure alias: it has
1108 * a few extra devices that only appear there (generally the
1109 * control interfaces for the protection controllers).
1110 * We implement this by mapping those devices over the top of this
1111 * alias MR at a higher priority. Some of the devices in this range
1112 * are per-CPU, so we must put this alias in the per-cpu containers.
1113 */
1114 for (i = 0; i < info->num_cpus; i++) {
1115 make_alias(s, &s->alias3[i], &s->cpu_container[i],
1116 "alias 3", 0x50000000, 0x10000000, 0x40000000);
1117 }
1118
1119 /* Security controller */
1120 object_property_set_int(OBJECT(&s->secctl), "sse-version",
1121 info->sse_version, &error_abort);
1122 if (!sysbus_realize(SYS_BUS_DEVICE(&s->secctl), errp)) {
1123 return;
1124 }
1125 sbd_secctl = SYS_BUS_DEVICE(&s->secctl);
1126 dev_secctl = DEVICE(&s->secctl);
1127 sysbus_mmio_map(sbd_secctl, 0, 0x50080000);
1128 sysbus_mmio_map(sbd_secctl, 1, 0x40080000);
1129
1130 s->nsc_cfg_in = qemu_allocate_irq(nsccfg_handler, s, 1);
1131 qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in);
1132
1133 /* The sec_resp_cfg output from the security controller must be split into
1134 * multiple lines, one for each of the PPCs within the ARMSSE and one
1135 * that will be an output from the ARMSSE to the system.
1136 */
1137 if (!object_property_set_int(OBJECT(&s->sec_resp_splitter),
1138 "num-lines", 3, errp)) {
1139 return;
1140 }
1141 if (!qdev_realize(DEVICE(&s->sec_resp_splitter), NULL, errp)) {
1142 return;
1143 }
1144 dev_splitter = DEVICE(&s->sec_resp_splitter);
1145 qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0,
1146 qdev_get_gpio_in(dev_splitter, 0));
1147
1148 /* Each SRAM bank lives behind its own Memory Protection Controller */
1149 for (i = 0; i < info->sram_banks; i++) {
1150 char *ramname = g_strdup_printf("armsse.sram%d", i);
1151 SysBusDevice *sbd_mpc;
1152 uint32_t sram_bank_size = 1 << s->sram_addr_width;
1153
1154 memory_region_init_ram(&s->sram[i], NULL, ramname,
1155 sram_bank_size, errp);
1156 g_free(ramname);
1157 if (*errp) {
1158 return;
1159 }
1160 object_property_set_link(OBJECT(&s->mpc[i]), "downstream",
1161 OBJECT(&s->sram[i]), &error_abort);
1162 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mpc[i]), errp)) {
1163 return;
1164 }
1165 /* Map the upstream end of the MPC into the right place... */
1166 sbd_mpc = SYS_BUS_DEVICE(&s->mpc[i]);
1167 memory_region_add_subregion(&s->container,
1168 info->sram_bank_base + i * sram_bank_size,
1169 sysbus_mmio_get_region(sbd_mpc, 1));
1170 /* ...and its register interface */
1171 memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000,
1172 sysbus_mmio_get_region(sbd_mpc, 0));
1173 }
1174
1175 /* We must OR together lines from the MPC splitters to go to the NVIC */
1176 if (!object_property_set_int(OBJECT(&s->mpc_irq_orgate), "num-lines",
1177 IOTS_NUM_EXP_MPC + info->sram_banks,
1178 errp)) {
1179 return;
1180 }
1181 if (!qdev_realize(DEVICE(&s->mpc_irq_orgate), NULL, errp)) {
1182 return;
1183 }
1184 qdev_connect_gpio_out(DEVICE(&s->mpc_irq_orgate), 0,
1185 armsse_get_common_irq_in(s, 9));
1186
1187 /* This OR gate wires together outputs from the secure watchdogs to NMI */
1188 if (!object_property_set_int(OBJECT(&s->nmi_orgate), "num-lines", 2,
1189 errp)) {
1190 return;
1191 }
1192 if (!qdev_realize(DEVICE(&s->nmi_orgate), NULL, errp)) {
1193 return;
1194 }
1195 qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0,
1196 qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0));
1197
1198 /* The SSE-300 has a System Counter / System Timestamp Generator */
1199 if (info->has_sse_counter) {
1200 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sse_counter);
1201
1202 qdev_connect_clock_in(DEVICE(sbd), "CLK", s->mainclk);
1203 if (!sysbus_realize(sbd, errp)) {
1204 return;
1205 }
1206 /*
1207 * The control frame is only in the Secure region;
1208 * the status frame is in the NS region (and visible in the
1209 * S region via the alias mapping).
1210 */
1211 memory_region_add_subregion(&s->container, 0x58100000,
1212 sysbus_mmio_get_region(sbd, 0));
1213 memory_region_add_subregion(&s->container, 0x48101000,
1214 sysbus_mmio_get_region(sbd, 1));
1215 }
1216
1217 /* Devices behind APB PPC0:
1218 * 0x40000000: timer0
1219 * 0x40001000: timer1
1220 * 0x40002000: dual timer
1221 * 0x40003000: MHU0 (SSE-200 only)
1222 * 0x40004000: MHU1 (SSE-200 only)
1223 * We must configure and realize each downstream device and connect
1224 * it to the appropriate PPC port; then we can realize the PPC and
1225 * map its upstream ends to the right place in the container.
1226 */
1227 for (devinfo = info->devinfo; devinfo->name; devinfo++) {
1228 SysBusDevice *sbd;
1229 qemu_irq irq;
1230
1231 if (!strcmp(devinfo->type, TYPE_CMSDK_APB_TIMER)) {
1232 sbd = SYS_BUS_DEVICE(&s->timer[devinfo->index]);
1233
1234 qdev_connect_clock_in(DEVICE(sbd), "pclk",
1235 devinfo->slowclk ? s->s32kclk : s->mainclk);
1236 if (!sysbus_realize(sbd, errp)) {
1237 return;
1238 }
1239 mr = sysbus_mmio_get_region(sbd, 0);
1240 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_DUALTIMER)) {
1241 sbd = SYS_BUS_DEVICE(&s->dualtimer);
1242
1243 qdev_connect_clock_in(DEVICE(sbd), "TIMCLK", s->mainclk);
1244 if (!sysbus_realize(sbd, errp)) {
1245 return;
1246 }
1247 mr = sysbus_mmio_get_region(sbd, 0);
1248 } else if (!strcmp(devinfo->type, TYPE_SSE_TIMER)) {
1249 sbd = SYS_BUS_DEVICE(&s->sse_timer[devinfo->index]);
1250
1251 assert(info->has_sse_counter);
1252 object_property_set_link(OBJECT(sbd), "counter",
1253 OBJECT(&s->sse_counter), &error_abort);
1254 if (!sysbus_realize(sbd, errp)) {
1255 return;
1256 }
1257 mr = sysbus_mmio_get_region(sbd, 0);
1258 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_WATCHDOG)) {
1259 sbd = SYS_BUS_DEVICE(&s->cmsdk_watchdog[devinfo->index]);
1260
1261 qdev_connect_clock_in(DEVICE(sbd), "WDOGCLK",
1262 devinfo->slowclk ? s->s32kclk : s->mainclk);
1263 if (!sysbus_realize(sbd, errp)) {
1264 return;
1265 }
1266 mr = sysbus_mmio_get_region(sbd, 0);
1267 } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSINFO)) {
1268 sbd = SYS_BUS_DEVICE(&s->sysinfo);
1269
1270 object_property_set_int(OBJECT(&s->sysinfo), "SYS_VERSION",
1271 info->sys_version, &error_abort);
1272 object_property_set_int(OBJECT(&s->sysinfo), "SYS_CONFIG",
1273 armsse_sys_config_value(s, info),
1274 &error_abort);
1275 object_property_set_int(OBJECT(&s->sysinfo), "sse-version",
1276 info->sse_version, &error_abort);
1277 object_property_set_int(OBJECT(&s->sysinfo), "IIDR",
1278 info->iidr, &error_abort);
1279 if (!sysbus_realize(sbd, errp)) {
1280 return;
1281 }
1282 mr = sysbus_mmio_get_region(sbd, 0);
1283 } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSCTL)) {
1284 /* System control registers */
1285 sbd = SYS_BUS_DEVICE(&s->sysctl);
1286
1287 object_property_set_int(OBJECT(&s->sysctl), "sse-version",
1288 info->sse_version, &error_abort);
1289 object_property_set_int(OBJECT(&s->sysctl), "CPUWAIT_RST",
1290 info->cpuwait_rst, &error_abort);
1291 object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR0_RST",
1292 s->init_svtor, &error_abort);
1293 object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR1_RST",
1294 s->init_svtor, &error_abort);
1295 if (!sysbus_realize(sbd, errp)) {
1296 return;
1297 }
1298 mr = sysbus_mmio_get_region(sbd, 0);
1299 } else if (!strcmp(devinfo->type, TYPE_UNIMPLEMENTED_DEVICE)) {
1300 sbd = SYS_BUS_DEVICE(&s->unimp[devinfo->index]);
1301
1302 qdev_prop_set_string(DEVICE(sbd), "name", devinfo->name);
1303 qdev_prop_set_uint64(DEVICE(sbd), "size", devinfo->size);
1304 if (!sysbus_realize(sbd, errp)) {
1305 return;
1306 }
1307 mr = sysbus_mmio_get_region(sbd, 0);
1308 } else {
1309 g_assert_not_reached();
1310 }
1311
1312 switch (devinfo->irq) {
1313 case NO_IRQ:
1314 irq = NULL;
1315 break;
1316 case 0 ... NUM_SSE_IRQS - 1:
1317 irq = armsse_get_common_irq_in(s, devinfo->irq);
1318 break;
1319 case NMI_0:
1320 case NMI_1:
1321 irq = qdev_get_gpio_in(DEVICE(&s->nmi_orgate),
1322 devinfo->irq - NMI_0);
1323 break;
1324 default:
1325 g_assert_not_reached();
1326 }
1327
1328 if (irq) {
1329 sysbus_connect_irq(sbd, 0, irq);
1330 }
1331
1332 /*
1333 * Devices connected to a PPC are connected to the port here;
1334 * we will map the upstream end of that port to the right address
1335 * in the container later after the PPC has been realized.
1336 * Devices not connected to a PPC can be mapped immediately.
1337 */
1338 if (devinfo->ppc != NO_PPC) {
1339 TZPPC *ppc = &s->apb_ppc[devinfo->ppc];
1340 g_autofree char *portname = g_strdup_printf("port[%d]",
1341 devinfo->ppc_port);
1342 object_property_set_link(OBJECT(ppc), portname, OBJECT(mr),
1343 &error_abort);
1344 } else {
1345 memory_region_add_subregion(&s->container, devinfo->addr, mr);
1346 }
1347 }
1348
1349 if (info->has_mhus) {
1350 /*
1351 * An SSE-200 with only one CPU should have only one MHU created,
1352 * with the region where the second MHU usually is being RAZ/WI.
1353 * We don't implement that SSE-200 config; if we want to support
1354 * it then this code needs to be enhanced to handle creating the
1355 * RAZ/WI region instead of the second MHU.
1356 */
1357 assert(info->num_cpus == ARRAY_SIZE(s->mhu));
1358
1359 for (i = 0; i < ARRAY_SIZE(s->mhu); i++) {
1360 char *port;
1361 int cpunum;
1362 SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]);
1363
1364 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mhu[i]), errp)) {
1365 return;
1366 }
1367 port = g_strdup_printf("port[%d]", i + 3);
1368 mr = sysbus_mmio_get_region(mhu_sbd, 0);
1369 object_property_set_link(OBJECT(&s->apb_ppc[0]), port, OBJECT(mr),
1370 &error_abort);
1371 g_free(port);
1372
1373 /*
1374 * Each MHU has an irq line for each CPU:
1375 * MHU 0 irq line 0 -> CPU 0 IRQ 6
1376 * MHU 0 irq line 1 -> CPU 1 IRQ 6
1377 * MHU 1 irq line 0 -> CPU 0 IRQ 7
1378 * MHU 1 irq line 1 -> CPU 1 IRQ 7
1379 */
1380 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) {
1381 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]);
1382
1383 sysbus_connect_irq(mhu_sbd, cpunum,
1384 qdev_get_gpio_in(cpudev, 6 + i));
1385 }
1386 }
1387 }
1388
1389 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[0]), errp)) {
1390 return;
1391 }
1392
1393 sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc[0]);
1394 dev_apb_ppc0 = DEVICE(&s->apb_ppc[0]);
1395
1396 if (info->has_mhus) {
1397 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 3);
1398 memory_region_add_subregion(&s->container, 0x40003000, mr);
1399 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 4);
1400 memory_region_add_subregion(&s->container, 0x40004000, mr);
1401 }
1402 for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) {
1403 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i,
1404 qdev_get_gpio_in_named(dev_apb_ppc0,
1405 "cfg_nonsec", i));
1406 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_ap", i,
1407 qdev_get_gpio_in_named(dev_apb_ppc0,
1408 "cfg_ap", i));
1409 }
1410 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0,
1411 qdev_get_gpio_in_named(dev_apb_ppc0,
1412 "irq_enable", 0));
1413 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0,
1414 qdev_get_gpio_in_named(dev_apb_ppc0,
1415 "irq_clear", 0));
1416 qdev_connect_gpio_out(dev_splitter, 0,
1417 qdev_get_gpio_in_named(dev_apb_ppc0,
1418 "cfg_sec_resp", 0));
1419
1420 /* All the PPC irq lines (from the 2 internal PPCs and the 8 external
1421 * ones) are sent individually to the security controller, and also
1422 * ORed together to give a single combined PPC interrupt to the NVIC.
1423 */
1424 if (!object_property_set_int(OBJECT(&s->ppc_irq_orgate),
1425 "num-lines", NUM_PPCS, errp)) {
1426 return;
1427 }
1428 if (!qdev_realize(DEVICE(&s->ppc_irq_orgate), NULL, errp)) {
1429 return;
1430 }
1431 qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0,
1432 armsse_get_common_irq_in(s, 10));
1433
1434 /*
1435 * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias):
1436 * private per-CPU region (all these devices are SSE-200 only):
1437 * 0x50010000: L1 icache control registers
1438 * 0x50011000: CPUSECCTRL (CPU local security control registers)
1439 * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block
1440 * The SSE-300 has an extra:
1441 * 0x40012000 and 0x50012000: CPU_PWRCTRL register block
1442 */
1443 if (info->has_cachectrl) {
1444 for (i = 0; i < info->num_cpus; i++) {
1445 char *name = g_strdup_printf("cachectrl%d", i);
1446 MemoryRegion *mr;
1447
1448 qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name);
1449 g_free(name);
1450 qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000);
1451 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cachectrl[i]), errp)) {
1452 return;
1453 }
1454
1455 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i]), 0);
1456 memory_region_add_subregion(&s->cpu_container[i], 0x50010000, mr);
1457 }
1458 }
1459 if (info->has_cpusecctrl) {
1460 for (i = 0; i < info->num_cpus; i++) {
1461 char *name = g_strdup_printf("CPUSECCTRL%d", i);
1462 MemoryRegion *mr;
1463
1464 qdev_prop_set_string(DEVICE(&s->cpusecctrl[i]), "name", name);
1465 g_free(name);
1466 qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000);
1467 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpusecctrl[i]), errp)) {
1468 return;
1469 }
1470
1471 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpusecctrl[i]), 0);
1472 memory_region_add_subregion(&s->cpu_container[i], 0x50011000, mr);
1473 }
1474 }
1475 if (info->has_cpuid) {
1476 for (i = 0; i < info->num_cpus; i++) {
1477 MemoryRegion *mr;
1478
1479 qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i);
1480 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpuid[i]), errp)) {
1481 return;
1482 }
1483
1484 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0);
1485 memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, mr);
1486 }
1487 }
1488 if (info->has_cpu_pwrctrl) {
1489 for (i = 0; i < info->num_cpus; i++) {
1490 MemoryRegion *mr;
1491
1492 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu_pwrctrl[i]), errp)) {
1493 return;
1494 }
1495
1496 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpu_pwrctrl[i]), 0);
1497 memory_region_add_subregion(&s->cpu_container[i], 0x40012000, mr);
1498 }
1499 }
1500
1501 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[1]), errp)) {
1502 return;
1503 }
1504
1505 dev_apb_ppc1 = DEVICE(&s->apb_ppc[1]);
1506 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0,
1507 qdev_get_gpio_in_named(dev_apb_ppc1,
1508 "cfg_nonsec", 0));
1509 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0,
1510 qdev_get_gpio_in_named(dev_apb_ppc1,
1511 "cfg_ap", 0));
1512 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0,
1513 qdev_get_gpio_in_named(dev_apb_ppc1,
1514 "irq_enable", 0));
1515 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0,
1516 qdev_get_gpio_in_named(dev_apb_ppc1,
1517 "irq_clear", 0));
1518 qdev_connect_gpio_out(dev_splitter, 1,
1519 qdev_get_gpio_in_named(dev_apb_ppc1,
1520 "cfg_sec_resp", 0));
1521
1522 /*
1523 * Now both PPCs are realized we can map the upstream ends of
1524 * ports which correspond to entries in the devinfo array.
1525 * The ports which are connected to non-devinfo devices have
1526 * already been mapped.
1527 */
1528 for (devinfo = info->devinfo; devinfo->name; devinfo++) {
1529 SysBusDevice *ppc_sbd;
1530
1531 if (devinfo->ppc == NO_PPC) {
1532 continue;
1533 }
1534 ppc_sbd = SYS_BUS_DEVICE(&s->apb_ppc[devinfo->ppc]);
1535 mr = sysbus_mmio_get_region(ppc_sbd, devinfo->ppc_port);
1536 memory_region_add_subregion(&s->container, devinfo->addr, mr);
1537 }
1538
1539 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) {
1540 Object *splitter = OBJECT(&s->ppc_irq_splitter[i]);
1541
1542 if (!object_property_set_int(splitter, "num-lines", 2, errp)) {
1543 return;
1544 }
1545 if (!qdev_realize(DEVICE(splitter), NULL, errp)) {
1546 return;
1547 }
1548 }
1549
1550 for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) {
1551 char *ppcname = g_strdup_printf("ahb_ppcexp%d", i);
1552
1553 armsse_forward_ppc(s, ppcname, i);
1554 g_free(ppcname);
1555 }
1556
1557 for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) {
1558 char *ppcname = g_strdup_printf("apb_ppcexp%d", i);
1559
1560 armsse_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC);
1561 g_free(ppcname);
1562 }
1563
1564 for (i = NUM_EXTERNAL_PPCS; i < NUM_PPCS; i++) {
1565 /* Wire up IRQ splitter for internal PPCs */
1566 DeviceState *devs = DEVICE(&s->ppc_irq_splitter[i]);
1567 char *gpioname = g_strdup_printf("apb_ppc%d_irq_status",
1568 i - NUM_EXTERNAL_PPCS);
1569 TZPPC *ppc = &s->apb_ppc[i - NUM_EXTERNAL_PPCS];
1570
1571 qdev_connect_gpio_out(devs, 0,
1572 qdev_get_gpio_in_named(dev_secctl, gpioname, 0));
1573 qdev_connect_gpio_out(devs, 1,
1574 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), i));
1575 qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0,
1576 qdev_get_gpio_in(devs, 0));
1577 g_free(gpioname);
1578 }
1579
1580 /* Wire up the splitters for the MPC IRQs */
1581 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) {
1582 SplitIRQ *splitter = &s->mpc_irq_splitter[i];
1583 DeviceState *dev_splitter = DEVICE(splitter);
1584
1585 if (!object_property_set_int(OBJECT(splitter), "num-lines", 2,
1586 errp)) {
1587 return;
1588 }
1589 if (!qdev_realize(DEVICE(splitter), NULL, errp)) {
1590 return;
1591 }
1592
1593 if (i < IOTS_NUM_EXP_MPC) {
1594 /* Splitter input is from GPIO input line */
1595 s->mpcexp_status_in[i] = qdev_get_gpio_in(dev_splitter, 0);
1596 qdev_connect_gpio_out(dev_splitter, 0,
1597 qdev_get_gpio_in_named(dev_secctl,
1598 "mpcexp_status", i));
1599 } else {
1600 /* Splitter input is from our own MPC */
1601 qdev_connect_gpio_out_named(DEVICE(&s->mpc[i - IOTS_NUM_EXP_MPC]),
1602 "irq", 0,
1603 qdev_get_gpio_in(dev_splitter, 0));
1604 qdev_connect_gpio_out(dev_splitter, 0,
1605 qdev_get_gpio_in_named(dev_secctl,
1606 "mpc_status",
1607 i - IOTS_NUM_EXP_MPC));
1608 }
1609
1610 qdev_connect_gpio_out(dev_splitter, 1,
1611 qdev_get_gpio_in(DEVICE(&s->mpc_irq_orgate), i));
1612 }
1613 /* Create GPIO inputs which will pass the line state for our
1614 * mpcexp_irq inputs to the correct splitter devices.
1615 */
1616 qdev_init_gpio_in_named(dev, armsse_mpcexp_status, "mpcexp_status",
1617 IOTS_NUM_EXP_MPC);
1618
1619 armsse_forward_sec_resp_cfg(s);
1620
1621 /* Forward the MSC related signals */
1622 qdev_pass_gpios(dev_secctl, dev, "mscexp_status");
1623 qdev_pass_gpios(dev_secctl, dev, "mscexp_clear");
1624 qdev_pass_gpios(dev_secctl, dev, "mscexp_ns");
1625 qdev_connect_gpio_out_named(dev_secctl, "msc_irq", 0,
1626 armsse_get_common_irq_in(s, 11));
1627
1628 /*
1629 * Expose our container region to the board model; this corresponds
1630 * to the AHB Slave Expansion ports which allow bus master devices
1631 * (eg DMA controllers) in the board model to make transactions into
1632 * devices in the ARMSSE.
1633 */
1634 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container);
1635
1636 /* Set initial system_clock_scale from MAINCLK */
1637 armsse_mainclk_update(s, ClockUpdate);
1638 }
1639
1640 static void armsse_idau_check(IDAUInterface *ii, uint32_t address,
1641 int *iregion, bool *exempt, bool *ns, bool *nsc)
1642 {
1643 /*
1644 * For ARMSSE systems the IDAU responses are simple logical functions
1645 * of the address bits. The NSC attribute is guest-adjustable via the
1646 * NSCCFG register in the security controller.
1647 */
1648 ARMSSE *s = ARM_SSE(ii);
1649 int region = extract32(address, 28, 4);
1650
1651 *ns = !(region & 1);
1652 *nsc = (region == 1 && (s->nsccfg & 1)) || (region == 3 && (s->nsccfg & 2));
1653 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */
1654 *exempt = (address & 0xeff00000) == 0xe0000000;
1655 *iregion = region;
1656 }
1657
1658 static const VMStateDescription armsse_vmstate = {
1659 .name = "iotkit",
1660 .version_id = 2,
1661 .minimum_version_id = 2,
1662 .fields = (VMStateField[]) {
1663 VMSTATE_CLOCK(mainclk, ARMSSE),
1664 VMSTATE_CLOCK(s32kclk, ARMSSE),
1665 VMSTATE_UINT32(nsccfg, ARMSSE),
1666 VMSTATE_END_OF_LIST()
1667 }
1668 };
1669
1670 static void armsse_reset(DeviceState *dev)
1671 {
1672 ARMSSE *s = ARM_SSE(dev);
1673
1674 s->nsccfg = 0;
1675 }
1676
1677 static void armsse_class_init(ObjectClass *klass, void *data)
1678 {
1679 DeviceClass *dc = DEVICE_CLASS(klass);
1680 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass);
1681 ARMSSEClass *asc = ARM_SSE_CLASS(klass);
1682 const ARMSSEInfo *info = data;
1683
1684 dc->realize = armsse_realize;
1685 dc->vmsd = &armsse_vmstate;
1686 device_class_set_props(dc, info->props);
1687 dc->reset = armsse_reset;
1688 iic->check = armsse_idau_check;
1689 asc->info = info;
1690 }
1691
1692 static const TypeInfo armsse_info = {
1693 .name = TYPE_ARM_SSE,
1694 .parent = TYPE_SYS_BUS_DEVICE,
1695 .instance_size = sizeof(ARMSSE),
1696 .class_size = sizeof(ARMSSEClass),
1697 .instance_init = armsse_init,
1698 .abstract = true,
1699 .interfaces = (InterfaceInfo[]) {
1700 { TYPE_IDAU_INTERFACE },
1701 { }
1702 }
1703 };
1704
1705 static void armsse_register_types(void)
1706 {
1707 int i;
1708
1709 type_register_static(&armsse_info);
1710
1711 for (i = 0; i < ARRAY_SIZE(armsse_variants); i++) {
1712 TypeInfo ti = {
1713 .name = armsse_variants[i].name,
1714 .parent = TYPE_ARM_SSE,
1715 .class_init = armsse_class_init,
1716 .class_data = (void *)&armsse_variants[i],
1717 };
1718 type_register(&ti);
1719 }
1720 }
1721
1722 type_init(armsse_register_types);
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