2 * Arm SSE (Subsystems for Embedded): IoTKit
4 * Copyright (c) 2018 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
12 #include "qemu/osdep.h"
14 #include "qemu/module.h"
15 #include "qemu/bitops.h"
16 #include "qapi/error.h"
18 #include "hw/sysbus.h"
19 #include "migration/vmstate.h"
20 #include "hw/registerfields.h"
21 #include "hw/arm/armsse.h"
22 #include "hw/arm/boot.h"
25 /* Format of the System Information block SYS_CONFIG register */
26 typedef enum SysConfigFormat
{
37 SysConfigFormat sys_config_format
;
46 static Property iotkit_properties
[] = {
47 DEFINE_PROP_LINK("memory", ARMSSE
, board_memory
, TYPE_MEMORY_REGION
,
49 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE
, exp_numirq
, 64),
50 DEFINE_PROP_UINT32("MAINCLK", ARMSSE
, mainclk_frq
, 0),
51 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE
, sram_addr_width
, 15),
52 DEFINE_PROP_UINT32("init-svtor", ARMSSE
, init_svtor
, 0x10000000),
53 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE
, cpu_fpu
[0], true),
54 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE
, cpu_dsp
[0], true),
55 DEFINE_PROP_END_OF_LIST()
58 static Property armsse_properties
[] = {
59 DEFINE_PROP_LINK("memory", ARMSSE
, board_memory
, TYPE_MEMORY_REGION
,
61 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE
, exp_numirq
, 64),
62 DEFINE_PROP_UINT32("MAINCLK", ARMSSE
, mainclk_frq
, 0),
63 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE
, sram_addr_width
, 15),
64 DEFINE_PROP_UINT32("init-svtor", ARMSSE
, init_svtor
, 0x10000000),
65 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE
, cpu_fpu
[0], false),
66 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE
, cpu_dsp
[0], false),
67 DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE
, cpu_fpu
[1], true),
68 DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE
, cpu_dsp
[1], true),
69 DEFINE_PROP_END_OF_LIST()
72 static const ARMSSEInfo armsse_variants
[] = {
77 .sys_version
= 0x41743,
79 .sys_config_format
= IoTKitFormat
,
82 .has_cachectrl
= false,
83 .has_cpusecctrl
= false,
85 .props
= iotkit_properties
,
91 .sys_version
= 0x22041743,
93 .sys_config_format
= SSE200Format
,
96 .has_cachectrl
= true,
97 .has_cpusecctrl
= true,
99 .props
= armsse_properties
,
103 static uint32_t armsse_sys_config_value(ARMSSE
*s
, const ARMSSEInfo
*info
)
105 /* Return the SYS_CONFIG value for this SSE */
108 switch (info
->sys_config_format
) {
111 sys_config
= deposit32(sys_config
, 0, 4, info
->sram_banks
);
112 sys_config
= deposit32(sys_config
, 4, 4, s
->sram_addr_width
- 12);
116 sys_config
= deposit32(sys_config
, 0, 4, info
->sram_banks
);
117 sys_config
= deposit32(sys_config
, 4, 5, s
->sram_addr_width
);
118 sys_config
= deposit32(sys_config
, 24, 4, 2);
119 if (info
->num_cpus
> 1) {
120 sys_config
= deposit32(sys_config
, 10, 1, 1);
121 sys_config
= deposit32(sys_config
, 20, 4, info
->sram_banks
- 1);
122 sys_config
= deposit32(sys_config
, 28, 4, 2);
126 g_assert_not_reached();
131 /* Clock frequency in HZ of the 32KHz "slow clock" */
132 #define S32KCLK (32 * 1000)
134 /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */
135 static bool irq_is_common
[32] = {
137 /* 6, 7: per-CPU MHU interrupts */
139 /* 13: per-CPU icache interrupt */
145 /* 28, 29: per-CPU CTI interrupts */
146 /* 30, 31: reserved */
150 * Create an alias region in @container of @size bytes starting at @base
151 * which mirrors the memory starting at @orig.
153 static void make_alias(ARMSSE
*s
, MemoryRegion
*mr
, MemoryRegion
*container
,
154 const char *name
, hwaddr base
, hwaddr size
, hwaddr orig
)
156 memory_region_init_alias(mr
, NULL
, name
, container
, orig
, size
);
157 /* The alias is even lower priority than unimplemented_device regions */
158 memory_region_add_subregion_overlap(container
, base
, mr
, -1500);
161 static void irq_status_forwarder(void *opaque
, int n
, int level
)
163 qemu_irq destirq
= opaque
;
165 qemu_set_irq(destirq
, level
);
168 static void nsccfg_handler(void *opaque
, int n
, int level
)
170 ARMSSE
*s
= ARMSSE(opaque
);
175 static void armsse_forward_ppc(ARMSSE
*s
, const char *ppcname
, int ppcnum
)
177 /* Each of the 4 AHB and 4 APB PPCs that might be present in a
178 * system using the ARMSSE has a collection of control lines which
179 * are provided by the security controller and which we want to
180 * expose as control lines on the ARMSSE device itself, so the
181 * code using the ARMSSE can wire them up to the PPCs.
183 SplitIRQ
*splitter
= &s
->ppc_irq_splitter
[ppcnum
];
184 DeviceState
*armssedev
= DEVICE(s
);
185 DeviceState
*dev_secctl
= DEVICE(&s
->secctl
);
186 DeviceState
*dev_splitter
= DEVICE(splitter
);
189 name
= g_strdup_printf("%s_nonsec", ppcname
);
190 qdev_pass_gpios(dev_secctl
, armssedev
, name
);
192 name
= g_strdup_printf("%s_ap", ppcname
);
193 qdev_pass_gpios(dev_secctl
, armssedev
, name
);
195 name
= g_strdup_printf("%s_irq_enable", ppcname
);
196 qdev_pass_gpios(dev_secctl
, armssedev
, name
);
198 name
= g_strdup_printf("%s_irq_clear", ppcname
);
199 qdev_pass_gpios(dev_secctl
, armssedev
, name
);
202 /* irq_status is a little more tricky, because we need to
203 * split it so we can send it both to the security controller
204 * and to our OR gate for the NVIC interrupt line.
205 * Connect up the splitter's outputs, and create a GPIO input
206 * which will pass the line state to the input splitter.
208 name
= g_strdup_printf("%s_irq_status", ppcname
);
209 qdev_connect_gpio_out(dev_splitter
, 0,
210 qdev_get_gpio_in_named(dev_secctl
,
212 qdev_connect_gpio_out(dev_splitter
, 1,
213 qdev_get_gpio_in(DEVICE(&s
->ppc_irq_orgate
), ppcnum
));
214 s
->irq_status_in
[ppcnum
] = qdev_get_gpio_in(dev_splitter
, 0);
215 qdev_init_gpio_in_named_with_opaque(armssedev
, irq_status_forwarder
,
216 s
->irq_status_in
[ppcnum
], name
, 1);
220 static void armsse_forward_sec_resp_cfg(ARMSSE
*s
)
222 /* Forward the 3rd output from the splitter device as a
223 * named GPIO output of the armsse object.
225 DeviceState
*dev
= DEVICE(s
);
226 DeviceState
*dev_splitter
= DEVICE(&s
->sec_resp_splitter
);
228 qdev_init_gpio_out_named(dev
, &s
->sec_resp_cfg
, "sec_resp_cfg", 1);
229 s
->sec_resp_cfg_in
= qemu_allocate_irq(irq_status_forwarder
,
231 qdev_connect_gpio_out(dev_splitter
, 2, s
->sec_resp_cfg_in
);
234 static void armsse_init(Object
*obj
)
236 ARMSSE
*s
= ARMSSE(obj
);
237 ARMSSEClass
*asc
= ARMSSE_GET_CLASS(obj
);
238 const ARMSSEInfo
*info
= asc
->info
;
241 assert(info
->sram_banks
<= MAX_SRAM_BANKS
);
242 assert(info
->num_cpus
<= SSE_MAX_CPUS
);
244 memory_region_init(&s
->container
, obj
, "armsse-container", UINT64_MAX
);
246 for (i
= 0; i
< info
->num_cpus
; i
++) {
248 * We put each CPU in its own cluster as they are logically
249 * distinct and may be configured differently.
253 name
= g_strdup_printf("cluster%d", i
);
254 object_initialize_child(obj
, name
, &s
->cluster
[i
], TYPE_CPU_CLUSTER
);
255 qdev_prop_set_uint32(DEVICE(&s
->cluster
[i
]), "cluster-id", i
);
258 name
= g_strdup_printf("armv7m%d", i
);
259 sysbus_init_child_obj(OBJECT(&s
->cluster
[i
]), name
,
260 &s
->armv7m
[i
], sizeof(s
->armv7m
[i
]),
262 qdev_prop_set_string(DEVICE(&s
->armv7m
[i
]), "cpu-type",
263 ARM_CPU_TYPE_NAME("cortex-m33"));
265 name
= g_strdup_printf("arm-sse-cpu-container%d", i
);
266 memory_region_init(&s
->cpu_container
[i
], obj
, name
, UINT64_MAX
);
269 name
= g_strdup_printf("arm-sse-container-alias%d", i
);
270 memory_region_init_alias(&s
->container_alias
[i
- 1], obj
,
271 name
, &s
->container
, 0, UINT64_MAX
);
276 object_initialize_child(obj
, "secctl", &s
->secctl
, TYPE_IOTKIT_SECCTL
);
277 object_initialize_child(obj
, "apb-ppc0", &s
->apb_ppc0
, TYPE_TZ_PPC
);
278 object_initialize_child(obj
, "apb-ppc1", &s
->apb_ppc1
, TYPE_TZ_PPC
);
279 for (i
= 0; i
< info
->sram_banks
; i
++) {
280 char *name
= g_strdup_printf("mpc%d", i
);
281 object_initialize_child(obj
, name
, &s
->mpc
[i
], TYPE_TZ_MPC
);
284 object_initialize_child(obj
, "mpc-irq-orgate", &s
->mpc_irq_orgate
,
287 for (i
= 0; i
< IOTS_NUM_EXP_MPC
+ info
->sram_banks
; i
++) {
288 char *name
= g_strdup_printf("mpc-irq-splitter-%d", i
);
289 SplitIRQ
*splitter
= &s
->mpc_irq_splitter
[i
];
291 object_initialize_child(obj
, name
, splitter
, TYPE_SPLIT_IRQ
);
294 object_initialize_child(obj
, "timer0", &s
->timer0
, TYPE_CMSDK_APB_TIMER
);
295 object_initialize_child(obj
, "timer1", &s
->timer1
, TYPE_CMSDK_APB_TIMER
);
296 object_initialize_child(obj
, "s32ktimer", &s
->s32ktimer
,
297 TYPE_CMSDK_APB_TIMER
);
298 object_initialize_child(obj
, "dualtimer", &s
->dualtimer
,
299 TYPE_CMSDK_APB_DUALTIMER
);
300 object_initialize_child(obj
, "s32kwatchdog", &s
->s32kwatchdog
,
301 TYPE_CMSDK_APB_WATCHDOG
);
302 object_initialize_child(obj
, "nswatchdog", &s
->nswatchdog
,
303 TYPE_CMSDK_APB_WATCHDOG
);
304 object_initialize_child(obj
, "swatchdog", &s
->swatchdog
,
305 TYPE_CMSDK_APB_WATCHDOG
);
306 object_initialize_child(obj
, "armsse-sysctl", &s
->sysctl
,
308 object_initialize_child(obj
, "armsse-sysinfo", &s
->sysinfo
,
309 TYPE_IOTKIT_SYSINFO
);
310 if (info
->has_mhus
) {
311 sysbus_init_child_obj(obj
, "mhu0", &s
->mhu
[0], sizeof(s
->mhu
[0]),
313 sysbus_init_child_obj(obj
, "mhu1", &s
->mhu
[1], sizeof(s
->mhu
[1]),
316 if (info
->has_ppus
) {
317 for (i
= 0; i
< info
->num_cpus
; i
++) {
318 char *name
= g_strdup_printf("CPU%dCORE_PPU", i
);
319 int ppuidx
= CPU0CORE_PPU
+ i
;
321 sysbus_init_child_obj(obj
, name
, &s
->ppu
[ppuidx
],
322 sizeof(s
->ppu
[ppuidx
]),
323 TYPE_UNIMPLEMENTED_DEVICE
);
326 sysbus_init_child_obj(obj
, "DBG_PPU", &s
->ppu
[DBG_PPU
],
327 sizeof(s
->ppu
[DBG_PPU
]),
328 TYPE_UNIMPLEMENTED_DEVICE
);
329 for (i
= 0; i
< info
->sram_banks
; i
++) {
330 char *name
= g_strdup_printf("RAM%d_PPU", i
);
331 int ppuidx
= RAM0_PPU
+ i
;
333 sysbus_init_child_obj(obj
, name
, &s
->ppu
[ppuidx
],
334 sizeof(s
->ppu
[ppuidx
]),
335 TYPE_UNIMPLEMENTED_DEVICE
);
339 if (info
->has_cachectrl
) {
340 for (i
= 0; i
< info
->num_cpus
; i
++) {
341 char *name
= g_strdup_printf("cachectrl%d", i
);
343 object_initialize_child(obj
, name
, &s
->cachectrl
[i
],
344 TYPE_UNIMPLEMENTED_DEVICE
);
348 if (info
->has_cpusecctrl
) {
349 for (i
= 0; i
< info
->num_cpus
; i
++) {
350 char *name
= g_strdup_printf("cpusecctrl%d", i
);
352 object_initialize_child(obj
, name
, &s
->cpusecctrl
[i
],
353 TYPE_UNIMPLEMENTED_DEVICE
);
357 if (info
->has_cpuid
) {
358 for (i
= 0; i
< info
->num_cpus
; i
++) {
359 char *name
= g_strdup_printf("cpuid%d", i
);
361 object_initialize_child(obj
, name
, &s
->cpuid
[i
],
366 object_initialize_child(obj
, "nmi-orgate", &s
->nmi_orgate
, TYPE_OR_IRQ
);
367 object_initialize_child(obj
, "ppc-irq-orgate", &s
->ppc_irq_orgate
,
369 object_initialize_child(obj
, "sec-resp-splitter", &s
->sec_resp_splitter
,
371 for (i
= 0; i
< ARRAY_SIZE(s
->ppc_irq_splitter
); i
++) {
372 char *name
= g_strdup_printf("ppc-irq-splitter-%d", i
);
373 SplitIRQ
*splitter
= &s
->ppc_irq_splitter
[i
];
375 object_initialize_child(obj
, name
, splitter
, TYPE_SPLIT_IRQ
);
378 if (info
->num_cpus
> 1) {
379 for (i
= 0; i
< ARRAY_SIZE(s
->cpu_irq_splitter
); i
++) {
380 if (irq_is_common
[i
]) {
381 char *name
= g_strdup_printf("cpu-irq-splitter%d", i
);
382 SplitIRQ
*splitter
= &s
->cpu_irq_splitter
[i
];
384 object_initialize_child(obj
, name
, splitter
, TYPE_SPLIT_IRQ
);
391 static void armsse_exp_irq(void *opaque
, int n
, int level
)
393 qemu_irq
*irqarray
= opaque
;
395 qemu_set_irq(irqarray
[n
], level
);
398 static void armsse_mpcexp_status(void *opaque
, int n
, int level
)
400 ARMSSE
*s
= ARMSSE(opaque
);
401 qemu_set_irq(s
->mpcexp_status_in
[n
], level
);
404 static qemu_irq
armsse_get_common_irq_in(ARMSSE
*s
, int irqno
)
407 * Return a qemu_irq which can be used to signal IRQ n to
408 * all CPUs in the SSE.
410 ARMSSEClass
*asc
= ARMSSE_GET_CLASS(s
);
411 const ARMSSEInfo
*info
= asc
->info
;
413 assert(irq_is_common
[irqno
]);
415 if (info
->num_cpus
== 1) {
416 /* Only one CPU -- just connect directly to it */
417 return qdev_get_gpio_in(DEVICE(&s
->armv7m
[0]), irqno
);
419 /* Connect to the splitter which feeds all CPUs */
420 return qdev_get_gpio_in(DEVICE(&s
->cpu_irq_splitter
[irqno
]), 0);
424 static void map_ppu(ARMSSE
*s
, int ppuidx
, const char *name
, hwaddr addr
)
426 /* Map a PPU unimplemented device stub */
427 DeviceState
*dev
= DEVICE(&s
->ppu
[ppuidx
]);
429 qdev_prop_set_string(dev
, "name", name
);
430 qdev_prop_set_uint64(dev
, "size", 0x1000);
431 qdev_init_nofail(dev
);
432 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ppu
[ppuidx
]), 0, addr
);
435 static void armsse_realize(DeviceState
*dev
, Error
**errp
)
437 ARMSSE
*s
= ARMSSE(dev
);
438 ARMSSEClass
*asc
= ARMSSE_GET_CLASS(dev
);
439 const ARMSSEInfo
*info
= asc
->info
;
443 SysBusDevice
*sbd_apb_ppc0
;
444 SysBusDevice
*sbd_secctl
;
445 DeviceState
*dev_apb_ppc0
;
446 DeviceState
*dev_apb_ppc1
;
447 DeviceState
*dev_secctl
;
448 DeviceState
*dev_splitter
;
449 uint32_t addr_width_max
;
451 if (!s
->board_memory
) {
452 error_setg(errp
, "memory property was not set");
456 if (!s
->mainclk_frq
) {
457 error_setg(errp
, "MAINCLK property was not set");
461 /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */
462 assert(is_power_of_2(info
->sram_banks
));
463 addr_width_max
= 24 - ctz32(info
->sram_banks
);
464 if (s
->sram_addr_width
< 1 || s
->sram_addr_width
> addr_width_max
) {
465 error_setg(errp
, "SRAM_ADDR_WIDTH must be between 1 and %d",
470 /* Handling of which devices should be available only to secure
471 * code is usually done differently for M profile than for A profile.
472 * Instead of putting some devices only into the secure address space,
473 * devices exist in both address spaces but with hard-wired security
474 * permissions that will cause the CPU to fault for non-secure accesses.
476 * The ARMSSE has an IDAU (Implementation Defined Access Unit),
477 * which specifies hard-wired security permissions for different
478 * areas of the physical address space. For the ARMSSE IDAU, the
479 * top 4 bits of the physical address are the IDAU region ID, and
480 * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS
481 * region, otherwise it is an S region.
483 * The various devices and RAMs are generally all mapped twice,
484 * once into a region that the IDAU defines as secure and once
485 * into a non-secure region. They sit behind either a Memory
486 * Protection Controller (for RAM) or a Peripheral Protection
487 * Controller (for devices), which allow a more fine grained
488 * configuration of whether non-secure accesses are permitted.
490 * (The other place that guest software can configure security
491 * permissions is in the architected SAU (Security Attribution
492 * Unit), which is entirely inside the CPU. The IDAU can upgrade
493 * the security attributes for a region to more restrictive than
494 * the SAU specifies, but cannot downgrade them.)
496 * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff
497 * 0x20000000..0x2007ffff 32KB FPGA block RAM
498 * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff
499 * 0x40000000..0x4000ffff base peripheral region 1
500 * 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE)
501 * 0x40020000..0x4002ffff system control element peripherals
502 * 0x40080000..0x400fffff base peripheral region 2
503 * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff
506 memory_region_add_subregion_overlap(&s
->container
, 0, s
->board_memory
, -2);
508 for (i
= 0; i
< info
->num_cpus
; i
++) {
509 DeviceState
*cpudev
= DEVICE(&s
->armv7m
[i
]);
510 Object
*cpuobj
= OBJECT(&s
->armv7m
[i
]);
514 qdev_prop_set_uint32(cpudev
, "num-irq", s
->exp_numirq
+ 32);
516 * In real hardware the initial Secure VTOR is set from the INITSVTOR*
517 * registers in the IoT Kit System Control Register block. In QEMU
518 * we set the initial value here, and also the reset value of the
519 * sysctl register, from this object's QOM init-svtor property.
520 * If the guest changes the INITSVTOR* registers at runtime then the
521 * code in iotkit-sysctl.c will update the CPU init-svtor property
522 * (which will then take effect on the next CPU warm-reset).
524 * Note that typically a board using the SSE-200 will have a system
525 * control processor whose boot firmware initializes the INITSVTOR*
526 * registers before powering up the CPUs. QEMU doesn't emulate
527 * the control processor, so instead we behave in the way that the
528 * firmware does: the initial value should be set by the board code
529 * (using the init-svtor property on the ARMSSE object) to match
530 * whatever its firmware does.
532 qdev_prop_set_uint32(cpudev
, "init-svtor", s
->init_svtor
);
534 * CPUs start powered down if the corresponding bit in the CPUWAIT
535 * register is 1. In real hardware the CPUWAIT register reset value is
536 * a configurable property of the SSE-200 (via the CPUWAIT0_RST and
537 * CPUWAIT1_RST parameters), but since all the boards we care about
538 * start CPU0 and leave CPU1 powered off, we hard-code that in
539 * info->cpuwait_rst for now. We can add QOM properties for this
540 * later if necessary.
542 if (extract32(info
->cpuwait_rst
, i
, 1)) {
543 object_property_set_bool(cpuobj
, true, "start-powered-off", &err
);
545 error_propagate(errp
, err
);
549 if (!s
->cpu_fpu
[i
]) {
550 object_property_set_bool(cpuobj
, false, "vfp", &err
);
552 error_propagate(errp
, err
);
556 if (!s
->cpu_dsp
[i
]) {
557 object_property_set_bool(cpuobj
, false, "dsp", &err
);
559 error_propagate(errp
, err
);
565 memory_region_add_subregion_overlap(&s
->cpu_container
[i
], 0,
566 &s
->container_alias
[i
- 1], -1);
568 memory_region_add_subregion_overlap(&s
->cpu_container
[i
], 0,
571 object_property_set_link(cpuobj
, OBJECT(&s
->cpu_container
[i
]),
574 error_propagate(errp
, err
);
577 object_property_set_link(cpuobj
, OBJECT(s
), "idau", &err
);
579 error_propagate(errp
, err
);
582 object_property_set_bool(cpuobj
, true, "realized", &err
);
584 error_propagate(errp
, err
);
588 * The cluster must be realized after the armv7m container, as
589 * the container's CPU object is only created on realize, and the
590 * CPU must exist and have been parented into the cluster before
591 * the cluster is realized.
593 object_property_set_bool(OBJECT(&s
->cluster
[i
]),
594 true, "realized", &err
);
596 error_propagate(errp
, err
);
600 /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */
601 s
->exp_irqs
[i
] = g_new(qemu_irq
, s
->exp_numirq
);
602 for (j
= 0; j
< s
->exp_numirq
; j
++) {
603 s
->exp_irqs
[i
][j
] = qdev_get_gpio_in(cpudev
, j
+ 32);
606 gpioname
= g_strdup("EXP_IRQ");
608 gpioname
= g_strdup_printf("EXP_CPU%d_IRQ", i
);
610 qdev_init_gpio_in_named_with_opaque(dev
, armsse_exp_irq
,
612 gpioname
, s
->exp_numirq
);
616 /* Wire up the splitters that connect common IRQs to all CPUs */
617 if (info
->num_cpus
> 1) {
618 for (i
= 0; i
< ARRAY_SIZE(s
->cpu_irq_splitter
); i
++) {
619 if (irq_is_common
[i
]) {
620 Object
*splitter
= OBJECT(&s
->cpu_irq_splitter
[i
]);
621 DeviceState
*devs
= DEVICE(splitter
);
624 object_property_set_int(splitter
, info
->num_cpus
,
627 error_propagate(errp
, err
);
630 object_property_set_bool(splitter
, true, "realized", &err
);
632 error_propagate(errp
, err
);
635 for (cpunum
= 0; cpunum
< info
->num_cpus
; cpunum
++) {
636 DeviceState
*cpudev
= DEVICE(&s
->armv7m
[cpunum
]);
638 qdev_connect_gpio_out(devs
, cpunum
,
639 qdev_get_gpio_in(cpudev
, i
));
645 /* Set up the big aliases first */
646 make_alias(s
, &s
->alias1
, &s
->container
, "alias 1",
647 0x10000000, 0x10000000, 0x00000000);
648 make_alias(s
, &s
->alias2
, &s
->container
,
649 "alias 2", 0x30000000, 0x10000000, 0x20000000);
650 /* The 0x50000000..0x5fffffff region is not a pure alias: it has
651 * a few extra devices that only appear there (generally the
652 * control interfaces for the protection controllers).
653 * We implement this by mapping those devices over the top of this
654 * alias MR at a higher priority. Some of the devices in this range
655 * are per-CPU, so we must put this alias in the per-cpu containers.
657 for (i
= 0; i
< info
->num_cpus
; i
++) {
658 make_alias(s
, &s
->alias3
[i
], &s
->cpu_container
[i
],
659 "alias 3", 0x50000000, 0x10000000, 0x40000000);
662 /* Security controller */
663 sysbus_realize(SYS_BUS_DEVICE(&s
->secctl
), &err
);
665 error_propagate(errp
, err
);
668 sbd_secctl
= SYS_BUS_DEVICE(&s
->secctl
);
669 dev_secctl
= DEVICE(&s
->secctl
);
670 sysbus_mmio_map(sbd_secctl
, 0, 0x50080000);
671 sysbus_mmio_map(sbd_secctl
, 1, 0x40080000);
673 s
->nsc_cfg_in
= qemu_allocate_irq(nsccfg_handler
, s
, 1);
674 qdev_connect_gpio_out_named(dev_secctl
, "nsc_cfg", 0, s
->nsc_cfg_in
);
676 /* The sec_resp_cfg output from the security controller must be split into
677 * multiple lines, one for each of the PPCs within the ARMSSE and one
678 * that will be an output from the ARMSSE to the system.
680 object_property_set_int(OBJECT(&s
->sec_resp_splitter
), 3,
683 error_propagate(errp
, err
);
686 object_property_set_bool(OBJECT(&s
->sec_resp_splitter
), true,
689 error_propagate(errp
, err
);
692 dev_splitter
= DEVICE(&s
->sec_resp_splitter
);
693 qdev_connect_gpio_out_named(dev_secctl
, "sec_resp_cfg", 0,
694 qdev_get_gpio_in(dev_splitter
, 0));
696 /* Each SRAM bank lives behind its own Memory Protection Controller */
697 for (i
= 0; i
< info
->sram_banks
; i
++) {
698 char *ramname
= g_strdup_printf("armsse.sram%d", i
);
699 SysBusDevice
*sbd_mpc
;
700 uint32_t sram_bank_size
= 1 << s
->sram_addr_width
;
702 memory_region_init_ram(&s
->sram
[i
], NULL
, ramname
,
703 sram_bank_size
, &err
);
706 error_propagate(errp
, err
);
709 object_property_set_link(OBJECT(&s
->mpc
[i
]), OBJECT(&s
->sram
[i
]),
712 error_propagate(errp
, err
);
715 sysbus_realize(SYS_BUS_DEVICE(&s
->mpc
[i
]), &err
);
717 error_propagate(errp
, err
);
720 /* Map the upstream end of the MPC into the right place... */
721 sbd_mpc
= SYS_BUS_DEVICE(&s
->mpc
[i
]);
722 memory_region_add_subregion(&s
->container
,
723 0x20000000 + i
* sram_bank_size
,
724 sysbus_mmio_get_region(sbd_mpc
, 1));
725 /* ...and its register interface */
726 memory_region_add_subregion(&s
->container
, 0x50083000 + i
* 0x1000,
727 sysbus_mmio_get_region(sbd_mpc
, 0));
730 /* We must OR together lines from the MPC splitters to go to the NVIC */
731 object_property_set_int(OBJECT(&s
->mpc_irq_orgate
),
732 IOTS_NUM_EXP_MPC
+ info
->sram_banks
,
735 error_propagate(errp
, err
);
738 object_property_set_bool(OBJECT(&s
->mpc_irq_orgate
), true,
741 error_propagate(errp
, err
);
744 qdev_connect_gpio_out(DEVICE(&s
->mpc_irq_orgate
), 0,
745 armsse_get_common_irq_in(s
, 9));
747 /* Devices behind APB PPC0:
750 * 0x40002000: dual timer
751 * 0x40003000: MHU0 (SSE-200 only)
752 * 0x40004000: MHU1 (SSE-200 only)
753 * We must configure and realize each downstream device and connect
754 * it to the appropriate PPC port; then we can realize the PPC and
755 * map its upstream ends to the right place in the container.
757 qdev_prop_set_uint32(DEVICE(&s
->timer0
), "pclk-frq", s
->mainclk_frq
);
758 sysbus_realize(SYS_BUS_DEVICE(&s
->timer0
), &err
);
760 error_propagate(errp
, err
);
763 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->timer0
), 0,
764 armsse_get_common_irq_in(s
, 3));
765 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->timer0
), 0);
766 object_property_set_link(OBJECT(&s
->apb_ppc0
), OBJECT(mr
), "port[0]", &err
);
768 error_propagate(errp
, err
);
772 qdev_prop_set_uint32(DEVICE(&s
->timer1
), "pclk-frq", s
->mainclk_frq
);
773 sysbus_realize(SYS_BUS_DEVICE(&s
->timer1
), &err
);
775 error_propagate(errp
, err
);
778 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->timer1
), 0,
779 armsse_get_common_irq_in(s
, 4));
780 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->timer1
), 0);
781 object_property_set_link(OBJECT(&s
->apb_ppc0
), OBJECT(mr
), "port[1]", &err
);
783 error_propagate(errp
, err
);
788 qdev_prop_set_uint32(DEVICE(&s
->dualtimer
), "pclk-frq", s
->mainclk_frq
);
789 sysbus_realize(SYS_BUS_DEVICE(&s
->dualtimer
), &err
);
791 error_propagate(errp
, err
);
794 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->dualtimer
), 0,
795 armsse_get_common_irq_in(s
, 5));
796 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->dualtimer
), 0);
797 object_property_set_link(OBJECT(&s
->apb_ppc0
), OBJECT(mr
), "port[2]", &err
);
799 error_propagate(errp
, err
);
803 if (info
->has_mhus
) {
805 * An SSE-200 with only one CPU should have only one MHU created,
806 * with the region where the second MHU usually is being RAZ/WI.
807 * We don't implement that SSE-200 config; if we want to support
808 * it then this code needs to be enhanced to handle creating the
809 * RAZ/WI region instead of the second MHU.
811 assert(info
->num_cpus
== ARRAY_SIZE(s
->mhu
));
813 for (i
= 0; i
< ARRAY_SIZE(s
->mhu
); i
++) {
816 SysBusDevice
*mhu_sbd
= SYS_BUS_DEVICE(&s
->mhu
[i
]);
818 object_property_set_bool(OBJECT(&s
->mhu
[i
]), true,
821 error_propagate(errp
, err
);
824 port
= g_strdup_printf("port[%d]", i
+ 3);
825 mr
= sysbus_mmio_get_region(mhu_sbd
, 0);
826 object_property_set_link(OBJECT(&s
->apb_ppc0
), OBJECT(mr
),
830 error_propagate(errp
, err
);
835 * Each MHU has an irq line for each CPU:
836 * MHU 0 irq line 0 -> CPU 0 IRQ 6
837 * MHU 0 irq line 1 -> CPU 1 IRQ 6
838 * MHU 1 irq line 0 -> CPU 0 IRQ 7
839 * MHU 1 irq line 1 -> CPU 1 IRQ 7
841 for (cpunum
= 0; cpunum
< info
->num_cpus
; cpunum
++) {
842 DeviceState
*cpudev
= DEVICE(&s
->armv7m
[cpunum
]);
844 sysbus_connect_irq(mhu_sbd
, cpunum
,
845 qdev_get_gpio_in(cpudev
, 6 + i
));
850 sysbus_realize(SYS_BUS_DEVICE(&s
->apb_ppc0
), &err
);
852 error_propagate(errp
, err
);
856 sbd_apb_ppc0
= SYS_BUS_DEVICE(&s
->apb_ppc0
);
857 dev_apb_ppc0
= DEVICE(&s
->apb_ppc0
);
859 mr
= sysbus_mmio_get_region(sbd_apb_ppc0
, 0);
860 memory_region_add_subregion(&s
->container
, 0x40000000, mr
);
861 mr
= sysbus_mmio_get_region(sbd_apb_ppc0
, 1);
862 memory_region_add_subregion(&s
->container
, 0x40001000, mr
);
863 mr
= sysbus_mmio_get_region(sbd_apb_ppc0
, 2);
864 memory_region_add_subregion(&s
->container
, 0x40002000, mr
);
865 if (info
->has_mhus
) {
866 mr
= sysbus_mmio_get_region(sbd_apb_ppc0
, 3);
867 memory_region_add_subregion(&s
->container
, 0x40003000, mr
);
868 mr
= sysbus_mmio_get_region(sbd_apb_ppc0
, 4);
869 memory_region_add_subregion(&s
->container
, 0x40004000, mr
);
871 for (i
= 0; i
< IOTS_APB_PPC0_NUM_PORTS
; i
++) {
872 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc0_nonsec", i
,
873 qdev_get_gpio_in_named(dev_apb_ppc0
,
875 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc0_ap", i
,
876 qdev_get_gpio_in_named(dev_apb_ppc0
,
879 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc0_irq_enable", 0,
880 qdev_get_gpio_in_named(dev_apb_ppc0
,
882 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc0_irq_clear", 0,
883 qdev_get_gpio_in_named(dev_apb_ppc0
,
885 qdev_connect_gpio_out(dev_splitter
, 0,
886 qdev_get_gpio_in_named(dev_apb_ppc0
,
889 /* All the PPC irq lines (from the 2 internal PPCs and the 8 external
890 * ones) are sent individually to the security controller, and also
891 * ORed together to give a single combined PPC interrupt to the NVIC.
893 object_property_set_int(OBJECT(&s
->ppc_irq_orgate
),
894 NUM_PPCS
, "num-lines", &err
);
896 error_propagate(errp
, err
);
899 object_property_set_bool(OBJECT(&s
->ppc_irq_orgate
), true,
902 error_propagate(errp
, err
);
905 qdev_connect_gpio_out(DEVICE(&s
->ppc_irq_orgate
), 0,
906 armsse_get_common_irq_in(s
, 10));
909 * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias):
910 * private per-CPU region (all these devices are SSE-200 only):
911 * 0x50010000: L1 icache control registers
912 * 0x50011000: CPUSECCTRL (CPU local security control registers)
913 * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block
915 if (info
->has_cachectrl
) {
916 for (i
= 0; i
< info
->num_cpus
; i
++) {
917 char *name
= g_strdup_printf("cachectrl%d", i
);
920 qdev_prop_set_string(DEVICE(&s
->cachectrl
[i
]), "name", name
);
922 qdev_prop_set_uint64(DEVICE(&s
->cachectrl
[i
]), "size", 0x1000);
923 sysbus_realize(SYS_BUS_DEVICE(&s
->cachectrl
[i
]), &err
);
925 error_propagate(errp
, err
);
929 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->cachectrl
[i
]), 0);
930 memory_region_add_subregion(&s
->cpu_container
[i
], 0x50010000, mr
);
933 if (info
->has_cpusecctrl
) {
934 for (i
= 0; i
< info
->num_cpus
; i
++) {
935 char *name
= g_strdup_printf("CPUSECCTRL%d", i
);
938 qdev_prop_set_string(DEVICE(&s
->cpusecctrl
[i
]), "name", name
);
940 qdev_prop_set_uint64(DEVICE(&s
->cpusecctrl
[i
]), "size", 0x1000);
941 sysbus_realize(SYS_BUS_DEVICE(&s
->cpusecctrl
[i
]), &err
);
943 error_propagate(errp
, err
);
947 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->cpusecctrl
[i
]), 0);
948 memory_region_add_subregion(&s
->cpu_container
[i
], 0x50011000, mr
);
951 if (info
->has_cpuid
) {
952 for (i
= 0; i
< info
->num_cpus
; i
++) {
955 qdev_prop_set_uint32(DEVICE(&s
->cpuid
[i
]), "CPUID", i
);
956 sysbus_realize(SYS_BUS_DEVICE(&s
->cpuid
[i
]), &err
);
958 error_propagate(errp
, err
);
962 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->cpuid
[i
]), 0);
963 memory_region_add_subregion(&s
->cpu_container
[i
], 0x4001F000, mr
);
967 /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */
968 /* Devices behind APB PPC1:
969 * 0x4002f000: S32K timer
971 qdev_prop_set_uint32(DEVICE(&s
->s32ktimer
), "pclk-frq", S32KCLK
);
972 sysbus_realize(SYS_BUS_DEVICE(&s
->s32ktimer
), &err
);
974 error_propagate(errp
, err
);
977 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->s32ktimer
), 0,
978 armsse_get_common_irq_in(s
, 2));
979 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->s32ktimer
), 0);
980 object_property_set_link(OBJECT(&s
->apb_ppc1
), OBJECT(mr
), "port[0]", &err
);
982 error_propagate(errp
, err
);
986 sysbus_realize(SYS_BUS_DEVICE(&s
->apb_ppc1
), &err
);
988 error_propagate(errp
, err
);
991 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->apb_ppc1
), 0);
992 memory_region_add_subregion(&s
->container
, 0x4002f000, mr
);
994 dev_apb_ppc1
= DEVICE(&s
->apb_ppc1
);
995 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc1_nonsec", 0,
996 qdev_get_gpio_in_named(dev_apb_ppc1
,
998 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc1_ap", 0,
999 qdev_get_gpio_in_named(dev_apb_ppc1
,
1001 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc1_irq_enable", 0,
1002 qdev_get_gpio_in_named(dev_apb_ppc1
,
1004 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc1_irq_clear", 0,
1005 qdev_get_gpio_in_named(dev_apb_ppc1
,
1007 qdev_connect_gpio_out(dev_splitter
, 1,
1008 qdev_get_gpio_in_named(dev_apb_ppc1
,
1009 "cfg_sec_resp", 0));
1011 object_property_set_int(OBJECT(&s
->sysinfo
), info
->sys_version
,
1012 "SYS_VERSION", &err
);
1014 error_propagate(errp
, err
);
1017 object_property_set_int(OBJECT(&s
->sysinfo
),
1018 armsse_sys_config_value(s
, info
),
1019 "SYS_CONFIG", &err
);
1021 error_propagate(errp
, err
);
1024 sysbus_realize(SYS_BUS_DEVICE(&s
->sysinfo
), &err
);
1026 error_propagate(errp
, err
);
1029 /* System information registers */
1030 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sysinfo
), 0, 0x40020000);
1031 /* System control registers */
1032 object_property_set_int(OBJECT(&s
->sysctl
), info
->sys_version
,
1033 "SYS_VERSION", &err
);
1034 object_property_set_int(OBJECT(&s
->sysctl
), info
->cpuwait_rst
,
1035 "CPUWAIT_RST", &err
);
1036 object_property_set_int(OBJECT(&s
->sysctl
), s
->init_svtor
,
1037 "INITSVTOR0_RST", &err
);
1038 object_property_set_int(OBJECT(&s
->sysctl
), s
->init_svtor
,
1039 "INITSVTOR1_RST", &err
);
1040 sysbus_realize(SYS_BUS_DEVICE(&s
->sysctl
), &err
);
1042 error_propagate(errp
, err
);
1045 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sysctl
), 0, 0x50021000);
1047 if (info
->has_ppus
) {
1048 /* CPUnCORE_PPU for each CPU */
1049 for (i
= 0; i
< info
->num_cpus
; i
++) {
1050 char *name
= g_strdup_printf("CPU%dCORE_PPU", i
);
1052 map_ppu(s
, CPU0CORE_PPU
+ i
, name
, 0x50023000 + i
* 0x2000);
1054 * We don't support CPU debug so don't create the
1055 * CPU0DEBUG_PPU at 0x50024000 and 0x50026000.
1059 map_ppu(s
, DBG_PPU
, "DBG_PPU", 0x50029000);
1061 for (i
= 0; i
< info
->sram_banks
; i
++) {
1062 char *name
= g_strdup_printf("RAM%d_PPU", i
);
1064 map_ppu(s
, RAM0_PPU
+ i
, name
, 0x5002a000 + i
* 0x1000);
1069 /* This OR gate wires together outputs from the secure watchdogs to NMI */
1070 object_property_set_int(OBJECT(&s
->nmi_orgate
), 2, "num-lines", &err
);
1072 error_propagate(errp
, err
);
1075 object_property_set_bool(OBJECT(&s
->nmi_orgate
), true, "realized", &err
);
1077 error_propagate(errp
, err
);
1080 qdev_connect_gpio_out(DEVICE(&s
->nmi_orgate
), 0,
1081 qdev_get_gpio_in_named(DEVICE(&s
->armv7m
), "NMI", 0));
1083 qdev_prop_set_uint32(DEVICE(&s
->s32kwatchdog
), "wdogclk-frq", S32KCLK
);
1084 sysbus_realize(SYS_BUS_DEVICE(&s
->s32kwatchdog
), &err
);
1086 error_propagate(errp
, err
);
1089 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->s32kwatchdog
), 0,
1090 qdev_get_gpio_in(DEVICE(&s
->nmi_orgate
), 0));
1091 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->s32kwatchdog
), 0, 0x5002e000);
1093 /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */
1095 qdev_prop_set_uint32(DEVICE(&s
->nswatchdog
), "wdogclk-frq", s
->mainclk_frq
);
1096 sysbus_realize(SYS_BUS_DEVICE(&s
->nswatchdog
), &err
);
1098 error_propagate(errp
, err
);
1101 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->nswatchdog
), 0,
1102 armsse_get_common_irq_in(s
, 1));
1103 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->nswatchdog
), 0, 0x40081000);
1105 qdev_prop_set_uint32(DEVICE(&s
->swatchdog
), "wdogclk-frq", s
->mainclk_frq
);
1106 sysbus_realize(SYS_BUS_DEVICE(&s
->swatchdog
), &err
);
1108 error_propagate(errp
, err
);
1111 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->swatchdog
), 0,
1112 qdev_get_gpio_in(DEVICE(&s
->nmi_orgate
), 1));
1113 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->swatchdog
), 0, 0x50081000);
1115 for (i
= 0; i
< ARRAY_SIZE(s
->ppc_irq_splitter
); i
++) {
1116 Object
*splitter
= OBJECT(&s
->ppc_irq_splitter
[i
]);
1118 object_property_set_int(splitter
, 2, "num-lines", &err
);
1120 error_propagate(errp
, err
);
1123 object_property_set_bool(splitter
, true, "realized", &err
);
1125 error_propagate(errp
, err
);
1130 for (i
= 0; i
< IOTS_NUM_AHB_EXP_PPC
; i
++) {
1131 char *ppcname
= g_strdup_printf("ahb_ppcexp%d", i
);
1133 armsse_forward_ppc(s
, ppcname
, i
);
1137 for (i
= 0; i
< IOTS_NUM_APB_EXP_PPC
; i
++) {
1138 char *ppcname
= g_strdup_printf("apb_ppcexp%d", i
);
1140 armsse_forward_ppc(s
, ppcname
, i
+ IOTS_NUM_AHB_EXP_PPC
);
1144 for (i
= NUM_EXTERNAL_PPCS
; i
< NUM_PPCS
; i
++) {
1145 /* Wire up IRQ splitter for internal PPCs */
1146 DeviceState
*devs
= DEVICE(&s
->ppc_irq_splitter
[i
]);
1147 char *gpioname
= g_strdup_printf("apb_ppc%d_irq_status",
1148 i
- NUM_EXTERNAL_PPCS
);
1149 TZPPC
*ppc
= (i
== NUM_EXTERNAL_PPCS
) ? &s
->apb_ppc0
: &s
->apb_ppc1
;
1151 qdev_connect_gpio_out(devs
, 0,
1152 qdev_get_gpio_in_named(dev_secctl
, gpioname
, 0));
1153 qdev_connect_gpio_out(devs
, 1,
1154 qdev_get_gpio_in(DEVICE(&s
->ppc_irq_orgate
), i
));
1155 qdev_connect_gpio_out_named(DEVICE(ppc
), "irq", 0,
1156 qdev_get_gpio_in(devs
, 0));
1160 /* Wire up the splitters for the MPC IRQs */
1161 for (i
= 0; i
< IOTS_NUM_EXP_MPC
+ info
->sram_banks
; i
++) {
1162 SplitIRQ
*splitter
= &s
->mpc_irq_splitter
[i
];
1163 DeviceState
*dev_splitter
= DEVICE(splitter
);
1165 object_property_set_int(OBJECT(splitter
), 2, "num-lines", &err
);
1167 error_propagate(errp
, err
);
1170 object_property_set_bool(OBJECT(splitter
), true, "realized", &err
);
1172 error_propagate(errp
, err
);
1176 if (i
< IOTS_NUM_EXP_MPC
) {
1177 /* Splitter input is from GPIO input line */
1178 s
->mpcexp_status_in
[i
] = qdev_get_gpio_in(dev_splitter
, 0);
1179 qdev_connect_gpio_out(dev_splitter
, 0,
1180 qdev_get_gpio_in_named(dev_secctl
,
1181 "mpcexp_status", i
));
1183 /* Splitter input is from our own MPC */
1184 qdev_connect_gpio_out_named(DEVICE(&s
->mpc
[i
- IOTS_NUM_EXP_MPC
]),
1186 qdev_get_gpio_in(dev_splitter
, 0));
1187 qdev_connect_gpio_out(dev_splitter
, 0,
1188 qdev_get_gpio_in_named(dev_secctl
,
1192 qdev_connect_gpio_out(dev_splitter
, 1,
1193 qdev_get_gpio_in(DEVICE(&s
->mpc_irq_orgate
), i
));
1195 /* Create GPIO inputs which will pass the line state for our
1196 * mpcexp_irq inputs to the correct splitter devices.
1198 qdev_init_gpio_in_named(dev
, armsse_mpcexp_status
, "mpcexp_status",
1201 armsse_forward_sec_resp_cfg(s
);
1203 /* Forward the MSC related signals */
1204 qdev_pass_gpios(dev_secctl
, dev
, "mscexp_status");
1205 qdev_pass_gpios(dev_secctl
, dev
, "mscexp_clear");
1206 qdev_pass_gpios(dev_secctl
, dev
, "mscexp_ns");
1207 qdev_connect_gpio_out_named(dev_secctl
, "msc_irq", 0,
1208 armsse_get_common_irq_in(s
, 11));
1211 * Expose our container region to the board model; this corresponds
1212 * to the AHB Slave Expansion ports which allow bus master devices
1213 * (eg DMA controllers) in the board model to make transactions into
1214 * devices in the ARMSSE.
1216 sysbus_init_mmio(SYS_BUS_DEVICE(s
), &s
->container
);
1218 system_clock_scale
= NANOSECONDS_PER_SECOND
/ s
->mainclk_frq
;
1221 static void armsse_idau_check(IDAUInterface
*ii
, uint32_t address
,
1222 int *iregion
, bool *exempt
, bool *ns
, bool *nsc
)
1225 * For ARMSSE systems the IDAU responses are simple logical functions
1226 * of the address bits. The NSC attribute is guest-adjustable via the
1227 * NSCCFG register in the security controller.
1229 ARMSSE
*s
= ARMSSE(ii
);
1230 int region
= extract32(address
, 28, 4);
1232 *ns
= !(region
& 1);
1233 *nsc
= (region
== 1 && (s
->nsccfg
& 1)) || (region
== 3 && (s
->nsccfg
& 2));
1234 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */
1235 *exempt
= (address
& 0xeff00000) == 0xe0000000;
1239 static const VMStateDescription armsse_vmstate
= {
1242 .minimum_version_id
= 1,
1243 .fields
= (VMStateField
[]) {
1244 VMSTATE_UINT32(nsccfg
, ARMSSE
),
1245 VMSTATE_END_OF_LIST()
1249 static void armsse_reset(DeviceState
*dev
)
1251 ARMSSE
*s
= ARMSSE(dev
);
1256 static void armsse_class_init(ObjectClass
*klass
, void *data
)
1258 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1259 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_CLASS(klass
);
1260 ARMSSEClass
*asc
= ARMSSE_CLASS(klass
);
1261 const ARMSSEInfo
*info
= data
;
1263 dc
->realize
= armsse_realize
;
1264 dc
->vmsd
= &armsse_vmstate
;
1265 device_class_set_props(dc
, info
->props
);
1266 dc
->reset
= armsse_reset
;
1267 iic
->check
= armsse_idau_check
;
1271 static const TypeInfo armsse_info
= {
1272 .name
= TYPE_ARMSSE
,
1273 .parent
= TYPE_SYS_BUS_DEVICE
,
1274 .instance_size
= sizeof(ARMSSE
),
1275 .instance_init
= armsse_init
,
1277 .interfaces
= (InterfaceInfo
[]) {
1278 { TYPE_IDAU_INTERFACE
},
1283 static void armsse_register_types(void)
1287 type_register_static(&armsse_info
);
1289 for (i
= 0; i
< ARRAY_SIZE(armsse_variants
); i
++) {
1291 .name
= armsse_variants
[i
].name
,
1292 .parent
= TYPE_ARMSSE
,
1293 .class_init
= armsse_class_init
,
1294 .class_data
= (void *)&armsse_variants
[i
],
1300 type_init(armsse_register_types
);