hw/arm/armv7m.c

   1 /*
   2  * ARMV7M System emulation.
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "hw/arm/armv7m.h"
  12 #include "qapi/error.h"
  13 #include "qemu-common.h"
  14 #include "cpu.h"
  15 #include "hw/sysbus.h"
  16 #include "hw/arm/arm.h"
  17 #include "hw/loader.h"
  18 #include "elf.h"
  19 #include "sysemu/qtest.h"
  20 #include "qemu/error-report.h"
  21 #include "exec/address-spaces.h"
  22 #include "target/arm/idau.h"
  23
  24 /* Bitbanded IO.  Each word corresponds to a single bit.  */
  25
  26 /* Get the byte address of the real memory for a bitband access.  */
  27 static inline hwaddr bitband_addr(BitBandState *s, hwaddr offset)
  28 {
  29     return s->base | (offset & 0x1ffffff) >> 5;
  30 }
  31
  32 static MemTxResult bitband_read(void *opaque, hwaddr offset,
  33                                 uint64_t *data, unsigned size, MemTxAttrs attrs)
  34 {
  35     BitBandState *s = opaque;
  36     uint8_t buf[4];
  37     MemTxResult res;
  38     int bitpos, bit;
  39     hwaddr addr;
  40
  41     assert(size <= 4);
  42
  43     /* Find address in underlying memory and round down to multiple of size */
  44     addr = bitband_addr(s, offset) & (-size);
  45     res = address_space_read(&s->source_as, addr, attrs, buf, size);
  46     if (res) {
  47         return res;
  48     }
  49     /* Bit position in the N bytes read... */
  50     bitpos = (offset >> 2) & ((size * 8) - 1);
  51     /* ...converted to byte in buffer and bit in byte */
  52     bit = (buf[bitpos >> 3] >> (bitpos & 7)) & 1;
  53     *data = bit;
  54     return MEMTX_OK;
  55 }
  56
  57 static MemTxResult bitband_write(void *opaque, hwaddr offset, uint64_t value,
  58                                  unsigned size, MemTxAttrs attrs)
  59 {
  60     BitBandState *s = opaque;
  61     uint8_t buf[4];
  62     MemTxResult res;
  63     int bitpos, bit;
  64     hwaddr addr;
  65
  66     assert(size <= 4);
  67
  68     /* Find address in underlying memory and round down to multiple of size */
  69     addr = bitband_addr(s, offset) & (-size);
  70     res = address_space_read(&s->source_as, addr, attrs, buf, size);
  71     if (res) {
  72         return res;
  73     }
  74     /* Bit position in the N bytes read... */
  75     bitpos = (offset >> 2) & ((size * 8) - 1);
  76     /* ...converted to byte in buffer and bit in byte */
  77     bit = 1 << (bitpos & 7);
  78     if (value & 1) {
  79         buf[bitpos >> 3] |= bit;
  80     } else {
  81         buf[bitpos >> 3] &= ~bit;
  82     }
  83     return address_space_write(&s->source_as, addr, attrs, buf, size);
  84 }
  85
  86 static const MemoryRegionOps bitband_ops = {
  87     .read_with_attrs = bitband_read,
  88     .write_with_attrs = bitband_write,
  89     .endianness = DEVICE_NATIVE_ENDIAN,
  90     .impl.min_access_size = 1,
  91     .impl.max_access_size = 4,
  92     .valid.min_access_size = 1,
  93     .valid.max_access_size = 4,
  94 };
  95
  96 static void bitband_init(Object *obj)
  97 {
  98     BitBandState *s = BITBAND(obj);
  99     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 100
 101     memory_region_init_io(&s->iomem, obj, &bitband_ops, s,
 102                           "bitband", 0x02000000);
 103     sysbus_init_mmio(dev, &s->iomem);
 104 }
 105
 106 static void bitband_realize(DeviceState *dev, Error **errp)
 107 {
 108     BitBandState *s = BITBAND(dev);
 109
 110     if (!s->source_memory) {
 111         error_setg(errp, "source-memory property not set");
 112         return;
 113     }
 114
 115     address_space_init(&s->source_as, s->source_memory, "bitband-source");
 116 }
 117
 118 /* Board init.  */
 119
 120 static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
 121     0x20000000, 0x40000000
 122 };
 123
 124 static const hwaddr bitband_output_addr[ARMV7M_NUM_BITBANDS] = {
 125     0x22000000, 0x42000000
 126 };
 127
 128 static void armv7m_instance_init(Object *obj)
 129 {
 130     ARMv7MState *s = ARMV7M(obj);
 131     int i;
 132
 133     /* Can't init the cpu here, we don't yet know which model to use */
 134
 135     memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);
 136
 137     sysbus_init_child_obj(obj, "nvnic", &s->nvic, sizeof(s->nvic), TYPE_NVIC);
 138     object_property_add_alias(obj, "num-irq",
 139                               OBJECT(&s->nvic), "num-irq", &error_abort);
 140
 141     for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
 142         sysbus_init_child_obj(obj, "bitband[*]", &s->bitband[i],
 143                               sizeof(s->bitband[i]), TYPE_BITBAND);
 144     }
 145 }
 146
 147 static void armv7m_realize(DeviceState *dev, Error **errp)
 148 {
 149     ARMv7MState *s = ARMV7M(dev);
 150     SysBusDevice *sbd;
 151     Error *err = NULL;
 152     int i;
 153
 154     if (!s->board_memory) {
 155         error_setg(errp, "memory property was not set");
 156         return;
 157     }
 158
 159     memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
 160
 161     s->cpu = ARM_CPU(object_new(s->cpu_type));
 162
 163     object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory",
 164                              &error_abort);
 165     if (object_property_find(OBJECT(s->cpu), "idau", NULL)) {
 166         object_property_set_link(OBJECT(s->cpu), s->idau, "idau", &err);
 167         if (err != NULL) {
 168             error_propagate(errp, err);
 169             return;
 170         }
 171     }
 172     if (object_property_find(OBJECT(s->cpu), "init-svtor", NULL)) {
 173         object_property_set_uint(OBJECT(s->cpu), s->init_svtor,
 174                                  "init-svtor", &err);
 175         if (err != NULL) {
 176             error_propagate(errp, err);
 177             return;
 178         }
 179     }
 180
 181     /* Tell the CPU where the NVIC is; it will fail realize if it doesn't
 182      * have one.
 183      */
 184     s->cpu->env.nvic = &s->nvic;
 185
 186     object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
 187     if (err != NULL) {
 188         error_propagate(errp, err);
 189         return;
 190     }
 191
 192     /* Note that we must realize the NVIC after the CPU */
 193     object_property_set_bool(OBJECT(&s->nvic), true, "realized", &err);
 194     if (err != NULL) {
 195         error_propagate(errp, err);
 196         return;
 197     }
 198
 199     /* Alias the NVIC's input and output GPIOs as our own so the board
 200      * code can wire them up. (We do this in realize because the
 201      * NVIC doesn't create the input GPIO array until realize.)
 202      */
 203     qdev_pass_gpios(DEVICE(&s->nvic), dev, NULL);
 204     qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
 205     qdev_pass_gpios(DEVICE(&s->nvic), dev, "NMI");
 206
 207     /* Wire the NVIC up to the CPU */
 208     sbd = SYS_BUS_DEVICE(&s->nvic);
 209     sysbus_connect_irq(sbd, 0,
 210                        qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
 211
 212     memory_region_add_subregion(&s->container, 0xe000e000,
 213                                 sysbus_mmio_get_region(sbd, 0));
 214
 215     if (s->enable_bitband) {
 216         for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
 217             Object *obj = OBJECT(&s->bitband[i]);
 218             SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
 219
 220             object_property_set_int(obj, bitband_input_addr[i], "base", &err);
 221             if (err != NULL) {
 222                 error_propagate(errp, err);
 223                 return;
 224             }
 225             object_property_set_link(obj, OBJECT(s->board_memory),
 226                                      "source-memory", &error_abort);
 227             object_property_set_bool(obj, true, "realized", &err);
 228             if (err != NULL) {
 229                 error_propagate(errp, err);
 230                 return;
 231             }
 232
 233             memory_region_add_subregion(&s->container, bitband_output_addr[i],
 234                                         sysbus_mmio_get_region(sbd, 0));
 235         }
 236     }
 237 }
 238
 239 static Property armv7m_properties[] = {
 240     DEFINE_PROP_STRING("cpu-type", ARMv7MState, cpu_type),
 241     DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION,
 242                      MemoryRegion *),
 243     DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *),
 244     DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0),
 245     DEFINE_PROP_BOOL("enable-bitband", ARMv7MState, enable_bitband, false),
 246     DEFINE_PROP_END_OF_LIST(),
 247 };
 248
 249 static void armv7m_class_init(ObjectClass *klass, void *data)
 250 {
 251     DeviceClass *dc = DEVICE_CLASS(klass);
 252
 253     dc->realize = armv7m_realize;
 254     dc->props = armv7m_properties;
 255 }
 256
 257 static const TypeInfo armv7m_info = {
 258     .name = TYPE_ARMV7M,
 259     .parent = TYPE_SYS_BUS_DEVICE,
 260     .instance_size = sizeof(ARMv7MState),
 261     .instance_init = armv7m_instance_init,
 262     .class_init = armv7m_class_init,
 263 };
 264
 265 static void armv7m_reset(void *opaque)
 266 {
 267     ARMCPU *cpu = opaque;
 268
 269     cpu_reset(CPU(cpu));
 270 }
 271
 272 void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
 273 {
 274     int image_size;
 275     uint64_t entry;
 276     uint64_t lowaddr;
 277     int big_endian;
 278     AddressSpace *as;
 279     int asidx;
 280     CPUState *cs = CPU(cpu);
 281
 282 #ifdef TARGET_WORDS_BIGENDIAN
 283     big_endian = 1;
 284 #else
 285     big_endian = 0;
 286 #endif
 287
 288     if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
 289         asidx = ARMASIdx_S;
 290     } else {
 291         asidx = ARMASIdx_NS;
 292     }
 293     as = cpu_get_address_space(cs, asidx);
 294
 295     if (kernel_filename) {
 296         image_size = load_elf_as(kernel_filename, NULL, NULL, &entry, &lowaddr,
 297                                  NULL, big_endian, EM_ARM, 1, 0, as);
 298         if (image_size < 0) {
 299             image_size = load_image_targphys_as(kernel_filename, 0,
 300                                                 mem_size, as);
 301             lowaddr = 0;
 302         }
 303         if (image_size < 0) {
 304             error_report("Could not load kernel '%s'", kernel_filename);
 305             exit(1);
 306         }
 307     }
 308
 309     /* CPU objects (unlike devices) are not automatically reset on system
 310      * reset, so we must always register a handler to do so. Unlike
 311      * A-profile CPUs, we don't need to do anything special in the
 312      * handler to arrange that it starts correctly.
 313      * This is arguably the wrong place to do this, but it matches the
 314      * way A-profile does it. Note that this means that every M profile
 315      * board must call this function!
 316      */
 317     qemu_register_reset(armv7m_reset, cpu);
 318 }
 319
 320 static Property bitband_properties[] = {
 321     DEFINE_PROP_UINT32("base", BitBandState, base, 0),
 322     DEFINE_PROP_LINK("source-memory", BitBandState, source_memory,
 323                      TYPE_MEMORY_REGION, MemoryRegion *),
 324     DEFINE_PROP_END_OF_LIST(),
 325 };
 326
 327 static void bitband_class_init(ObjectClass *klass, void *data)
 328 {
 329     DeviceClass *dc = DEVICE_CLASS(klass);
 330
 331     dc->realize = bitband_realize;
 332     dc->props = bitband_properties;
 333 }
 334
 335 static const TypeInfo bitband_info = {
 336     .name          = TYPE_BITBAND,
 337     .parent        = TYPE_SYS_BUS_DEVICE,
 338     .instance_size = sizeof(BitBandState),
 339     .instance_init = bitband_init,
 340     .class_init    = bitband_class_init,
 341 };
 342
 343 static void armv7m_register_types(void)
 344 {
 345     type_register_static(&bitband_info);
 346     type_register_static(&armv7m_info);
 347 }
 348
 349 type_init(armv7m_register_types)