]> git.proxmox.com Git - mirror_qemu.git/blob - hw/arm/aspeed.c
projects / mirror_qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
hw/arm/aspeed: Use arm_write_bootloader() to write the bootloader
[mirror_qemu.git] / hw / arm / aspeed.c
1 /*
2 * OpenPOWER Palmetto BMC
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "hw/arm/boot.h"
15 #include "hw/arm/aspeed.h"
16 #include "hw/arm/aspeed_soc.h"
17 #include "hw/arm/aspeed_eeprom.h"
18 #include "hw/i2c/i2c_mux_pca954x.h"
19 #include "hw/i2c/smbus_eeprom.h"
20 #include "hw/misc/pca9552.h"
21 #include "hw/nvram/eeprom_at24c.h"
22 #include "hw/sensor/tmp105.h"
23 #include "hw/misc/led.h"
24 #include "hw/qdev-properties.h"
25 #include "sysemu/block-backend.h"
26 #include "sysemu/reset.h"
27 #include "hw/loader.h"
28 #include "qemu/error-report.h"
29 #include "qemu/units.h"
30 #include "hw/qdev-clock.h"
31 #include "sysemu/sysemu.h"
32
33 static struct arm_boot_info aspeed_board_binfo = {
34 .board_id = -1, /* device-tree-only board */
35 };
36
37 struct AspeedMachineState {
38 /* Private */
39 MachineState parent_obj;
40 /* Public */
41
42 AspeedSoCState soc;
43 bool mmio_exec;
44 char *fmc_model;
45 char *spi_model;
46 };
47
48 /* Palmetto hardware value: 0x120CE416 */
49 #define PALMETTO_BMC_HW_STRAP1 ( \
50 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
51 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
52 SCU_AST2400_HW_STRAP_ACPI_DIS | \
53 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
54 SCU_HW_STRAP_VGA_CLASS_CODE | \
55 SCU_HW_STRAP_LPC_RESET_PIN | \
56 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
57 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
58 SCU_HW_STRAP_SPI_WIDTH | \
59 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
60 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
61
62 /* TODO: Find the actual hardware value */
63 #define SUPERMICROX11_BMC_HW_STRAP1 ( \
64 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
65 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
66 SCU_AST2400_HW_STRAP_ACPI_DIS | \
67 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
68 SCU_HW_STRAP_VGA_CLASS_CODE | \
69 SCU_HW_STRAP_LPC_RESET_PIN | \
70 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
71 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
72 SCU_HW_STRAP_SPI_WIDTH | \
73 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
74 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
75
76 /* TODO: Find the actual hardware value */
77 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \
78 AST2500_HW_STRAP1_DEFAULTS | \
79 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
80 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
81 SCU_AST2500_HW_STRAP_UART_DEBUG | \
82 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
83 SCU_HW_STRAP_SPI_WIDTH | \
84 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
85
86 /* AST2500 evb hardware value: 0xF100C2E6 */
87 #define AST2500_EVB_HW_STRAP1 (( \
88 AST2500_HW_STRAP1_DEFAULTS | \
89 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
90 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
91 SCU_AST2500_HW_STRAP_UART_DEBUG | \
92 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
93 SCU_HW_STRAP_MAC1_RGMII | \
94 SCU_HW_STRAP_MAC0_RGMII) & \
95 ~SCU_HW_STRAP_2ND_BOOT_WDT)
96
97 /* Romulus hardware value: 0xF10AD206 */
98 #define ROMULUS_BMC_HW_STRAP1 ( \
99 AST2500_HW_STRAP1_DEFAULTS | \
100 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
101 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
102 SCU_AST2500_HW_STRAP_UART_DEBUG | \
103 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
104 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
105 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
106
107 /* Sonorapass hardware value: 0xF100D216 */
108 #define SONORAPASS_BMC_HW_STRAP1 ( \
109 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
110 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
111 SCU_AST2500_HW_STRAP_UART_DEBUG | \
112 SCU_AST2500_HW_STRAP_RESERVED28 | \
113 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
114 SCU_HW_STRAP_VGA_CLASS_CODE | \
115 SCU_HW_STRAP_LPC_RESET_PIN | \
116 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
117 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
118 SCU_HW_STRAP_VGA_BIOS_ROM | \
119 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
120 SCU_AST2500_HW_STRAP_RESERVED1)
121
122 #define G220A_BMC_HW_STRAP1 ( \
123 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
124 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
125 SCU_AST2500_HW_STRAP_UART_DEBUG | \
126 SCU_AST2500_HW_STRAP_RESERVED28 | \
127 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
128 SCU_HW_STRAP_2ND_BOOT_WDT | \
129 SCU_HW_STRAP_VGA_CLASS_CODE | \
130 SCU_HW_STRAP_LPC_RESET_PIN | \
131 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
132 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
133 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \
134 SCU_AST2500_HW_STRAP_RESERVED1)
135
136 /* FP5280G2 hardware value: 0XF100D286 */
137 #define FP5280G2_BMC_HW_STRAP1 ( \
138 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
139 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
140 SCU_AST2500_HW_STRAP_UART_DEBUG | \
141 SCU_AST2500_HW_STRAP_RESERVED28 | \
142 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
143 SCU_HW_STRAP_VGA_CLASS_CODE | \
144 SCU_HW_STRAP_LPC_RESET_PIN | \
145 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
146 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
147 SCU_HW_STRAP_MAC1_RGMII | \
148 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
149 SCU_AST2500_HW_STRAP_RESERVED1)
150
151 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
152 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
153
154 /* Quanta-Q71l hardware value */
155 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \
156 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
157 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
158 SCU_AST2400_HW_STRAP_ACPI_DIS | \
159 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \
160 SCU_HW_STRAP_VGA_CLASS_CODE | \
161 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \
162 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
163 SCU_HW_STRAP_SPI_WIDTH | \
164 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \
165 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
166
167 /* AST2600 evb hardware value */
168 #define AST2600_EVB_HW_STRAP1 0x000000C0
169 #define AST2600_EVB_HW_STRAP2 0x00000003
170
171 /* Tacoma hardware value */
172 #define TACOMA_BMC_HW_STRAP1 0x00000000
173 #define TACOMA_BMC_HW_STRAP2 0x00000040
174
175 /* Rainier hardware value: (QEMU prototype) */
176 #define RAINIER_BMC_HW_STRAP1 0x00422016
177 #define RAINIER_BMC_HW_STRAP2 0x80000848
178
179 /* Fuji hardware value */
180 #define FUJI_BMC_HW_STRAP1 0x00000000
181 #define FUJI_BMC_HW_STRAP2 0x00000000
182
183 /* Bletchley hardware value */
184 /* TODO: Leave same as EVB for now. */
185 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
186 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
187
188 /* Qualcomm DC-SCM hardware value */
189 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000
190 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041
191
192 #define AST_SMP_MAILBOX_BASE 0x1e6e2180
193 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
194 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
195 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
196 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
197 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
198 #define AST_SMP_MBOX_GOSIGN 0xabbaab00
199
200 static void aspeed_write_smpboot(ARMCPU *cpu,
201 const struct arm_boot_info *info)
202 {
203 AddressSpace *as = arm_boot_address_space(cpu, info);
204 static const ARMInsnFixup poll_mailbox_ready[] = {
205 /*
206 * r2 = per-cpu go sign value
207 * r1 = AST_SMP_MBOX_FIELD_ENTRY
208 * r0 = AST_SMP_MBOX_FIELD_GOSIGN
209 */
210 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */
211 { 0xe21000ff }, /* ands r0, r0, #255 */
212 { 0xe59f201c }, /* ldr r2, [pc, #28] */
213 { 0xe1822000 }, /* orr r2, r2, r0 */
214
215 { 0xe59f1018 }, /* ldr r1, [pc, #24] */
216 { 0xe59f0018 }, /* ldr r0, [pc, #24] */
217
218 { 0xe320f002 }, /* wfe */
219 { 0xe5904000 }, /* ldr r4, [r0] */
220 { 0xe1520004 }, /* cmp r2, r4 */
221 { 0x1afffffb }, /* bne <wfe> */
222 { 0xe591f000 }, /* ldr pc, [r1] */
223 { AST_SMP_MBOX_GOSIGN },
224 { AST_SMP_MBOX_FIELD_ENTRY },
225 { AST_SMP_MBOX_FIELD_GOSIGN },
226 { 0, FIXUP_TERMINATOR }
227 };
228 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 };
229
230 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start,
231 poll_mailbox_ready, fixupcontext);
232 }
233
234 static void aspeed_reset_secondary(ARMCPU *cpu,
235 const struct arm_boot_info *info)
236 {
237 AddressSpace *as = arm_boot_address_space(cpu, info);
238 CPUState *cs = CPU(cpu);
239
240 /* info->smp_bootreg_addr */
241 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
242 MEMTXATTRS_UNSPECIFIED, NULL);
243 cpu_set_pc(cs, info->smp_loader_start);
244 }
245
246 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
247 Error **errp)
248 {
249 g_autofree void *storage = NULL;
250 int64_t size;
251
252 /* The block backend size should have already been 'validated' by
253 * the creation of the m25p80 object.
254 */
255 size = blk_getlength(blk);
256 if (size <= 0) {
257 error_setg(errp, "failed to get flash size");
258 return;
259 }
260
261 if (rom_size > size) {
262 rom_size = size;
263 }
264
265 storage = g_malloc0(rom_size);
266 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
267 error_setg(errp, "failed to read the initial flash content");
268 return;
269 }
270
271 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
272 }
273
274 /*
275 * Create a ROM and copy the flash contents at the expected address
276 * (0x0). Boots faster than execute-in-place.
277 */
278 static void aspeed_install_boot_rom(AspeedSoCState *soc, BlockBackend *blk,
279 uint64_t rom_size)
280 {
281 MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
282
283 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", rom_size,
284 &error_abort);
285 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
286 boot_rom, 1);
287 write_boot_rom(blk, ASPEED_SOC_SPI_BOOT_ADDR, rom_size, &error_abort);
288 }
289
290 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
291 unsigned int count, int unit0)
292 {
293 int i;
294
295 if (!flashtype) {
296 return;
297 }
298
299 for (i = 0; i < count; ++i) {
300 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
301 qemu_irq cs_line;
302 DeviceState *dev;
303
304 dev = qdev_new(flashtype);
305 if (dinfo) {
306 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
307 }
308 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
309
310 cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
311 qdev_connect_gpio_out_named(DEVICE(s), "cs", i, cs_line);
312 }
313 }
314
315 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
316 {
317 DeviceState *card;
318
319 if (!dinfo) {
320 return;
321 }
322 card = qdev_new(TYPE_SD_CARD);
323 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
324 &error_fatal);
325 qdev_realize_and_unref(card,
326 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
327 &error_fatal);
328 }
329
330 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
331 {
332 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
333 AspeedSoCState *s = &bmc->soc;
334 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
335
336 aspeed_soc_uart_set_chr(s, amc->uart_default, serial_hd(0));
337 for (int i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
338 if (uart == amc->uart_default) {
339 continue;
340 }
341 aspeed_soc_uart_set_chr(s, uart, serial_hd(i));
342 }
343 }
344
345 static void aspeed_machine_init(MachineState *machine)
346 {
347 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
348 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
349 AspeedSoCClass *sc;
350 int i;
351 NICInfo *nd = &nd_table[0];
352
353 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
354
355 sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
356
357 /*
358 * This will error out if the RAM size is not supported by the
359 * memory controller of the SoC.
360 */
361 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
362 &error_fatal);
363
364 for (i = 0; i < sc->macs_num; i++) {
365 if ((amc->macs_mask & (1 << i)) && nd->used) {
366 qemu_check_nic_model(nd, TYPE_FTGMAC100);
367 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
368 nd++;
369 }
370 }
371
372 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
373 &error_abort);
374 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
375 &error_abort);
376 object_property_set_link(OBJECT(&bmc->soc), "memory",
377 OBJECT(get_system_memory()), &error_abort);
378 object_property_set_link(OBJECT(&bmc->soc), "dram",
379 OBJECT(machine->ram), &error_abort);
380 if (machine->kernel_filename) {
381 /*
382 * When booting with a -kernel command line there is no u-boot
383 * that runs to unlock the SCU. In this case set the default to
384 * be unlocked as the kernel expects
385 */
386 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
387 ASPEED_SCU_PROT_KEY, &error_abort);
388 }
389 connect_serial_hds_to_uarts(bmc);
390 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
391
392 aspeed_board_init_flashes(&bmc->soc.fmc,
393 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
394 amc->num_cs, 0);
395 aspeed_board_init_flashes(&bmc->soc.spi[0],
396 bmc->spi_model ? bmc->spi_model : amc->spi_model,
397 1, amc->num_cs);
398
399 if (machine->kernel_filename && sc->num_cpus > 1) {
400 /* With no u-boot we must set up a boot stub for the secondary CPU */
401 MemoryRegion *smpboot = g_new(MemoryRegion, 1);
402 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
403 0x80, &error_abort);
404 memory_region_add_subregion(get_system_memory(),
405 AST_SMP_MAILBOX_BASE, smpboot);
406
407 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
408 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
409 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
410 }
411
412 aspeed_board_binfo.ram_size = machine->ram_size;
413 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
414
415 if (amc->i2c_init) {
416 amc->i2c_init(bmc);
417 }
418
419 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
420 sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
421 drive_get(IF_SD, 0, i));
422 }
423
424 if (bmc->soc.emmc.num_slots) {
425 sdhci_attach_drive(&bmc->soc.emmc.slots[0],
426 drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
427 }
428
429 if (!bmc->mmio_exec) {
430 DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0);
431
432 if (mtd0) {
433 uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot);
434 aspeed_install_boot_rom(&bmc->soc, blk_by_legacy_dinfo(mtd0),
435 rom_size);
436 }
437 }
438
439 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
440 }
441
442 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
443 {
444 AspeedSoCState *soc = &bmc->soc;
445 DeviceState *dev;
446 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
447
448 /* The palmetto platform expects a ds3231 RTC but a ds1338 is
449 * enough to provide basic RTC features. Alarms will be missing */
450 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
451
452 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
453 eeprom_buf);
454
455 /* add a TMP423 temperature sensor */
456 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
457 "tmp423", 0x4c));
458 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
459 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
460 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
461 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
462 }
463
464 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
465 {
466 AspeedSoCState *soc = &bmc->soc;
467
468 /*
469 * The quanta-q71l platform expects tmp75s which are compatible with
470 * tmp105s.
471 */
472 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
473 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
474 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
475
476 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
477 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
478 /* TODO: Add Memory Riser i2c mux and eeproms. */
479
480 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
481 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
482
483 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
484
485 /* i2c-7 */
486 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
487 /* - i2c@0: pmbus@59 */
488 /* - i2c@1: pmbus@58 */
489 /* - i2c@2: pmbus@58 */
490 /* - i2c@3: pmbus@59 */
491
492 /* TODO: i2c-7: Add PDB FRU eeprom@52 */
493 /* TODO: i2c-8: Add BMC FRU eeprom@50 */
494 }
495
496 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
497 {
498 AspeedSoCState *soc = &bmc->soc;
499 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
500
501 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
502 eeprom_buf);
503
504 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
505 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
506 TYPE_TMP105, 0x4d);
507 }
508
509 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
510 {
511 AspeedSoCState *soc = &bmc->soc;
512 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
513
514 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
515 eeprom_buf);
516
517 /* LM75 is compatible with TMP105 driver */
518 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
519 TYPE_TMP105, 0x4d);
520 }
521
522 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
523 {
524 AspeedSoCState *soc = &bmc->soc;
525
526 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
527 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
528 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len);
529 /* TMP421 */
530 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f);
531 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e);
532 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f);
533
534 }
535
536 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
537 {
538 AspeedSoCState *soc = &bmc->soc;
539
540 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
541 * good enough */
542 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
543 }
544
545 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
546 {
547 AspeedSoCState *soc = &bmc->soc;
548
549 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
550 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
551 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len);
552 /* TMP421 */
553 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f);
554 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f);
555 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e);
556 }
557
558 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
559 {
560 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
561 TYPE_PCA9552, addr);
562 }
563
564 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
565 {
566 AspeedSoCState *soc = &bmc->soc;
567
568 /* bus 2 : */
569 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
570 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
571 /* bus 2 : pca9546 @ 0x73 */
572
573 /* bus 3 : pca9548 @ 0x70 */
574
575 /* bus 4 : */
576 uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
577 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
578 eeprom4_54);
579 /* PCA9539 @ 0x76, but PCA9552 is compatible */
580 create_pca9552(soc, 4, 0x76);
581 /* PCA9539 @ 0x77, but PCA9552 is compatible */
582 create_pca9552(soc, 4, 0x77);
583
584 /* bus 6 : */
585 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
586 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
587 /* bus 6 : pca9546 @ 0x73 */
588
589 /* bus 8 : */
590 uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
591 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
592 eeprom8_56);
593 create_pca9552(soc, 8, 0x60);
594 create_pca9552(soc, 8, 0x61);
595 /* bus 8 : adc128d818 @ 0x1d */
596 /* bus 8 : adc128d818 @ 0x1f */
597
598 /*
599 * bus 13 : pca9548 @ 0x71
600 * - channel 3:
601 * - tmm421 @ 0x4c
602 * - tmp421 @ 0x4e
603 * - tmp421 @ 0x4f
604 */
605
606 }
607
608 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
609 {
610 static const struct {
611 unsigned gpio_id;
612 LEDColor color;
613 const char *description;
614 bool gpio_polarity;
615 } pca1_leds[] = {
616 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW},
617 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
618 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
619 };
620 AspeedSoCState *soc = &bmc->soc;
621 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
622 DeviceState *dev;
623 LEDState *led;
624
625 /* Bus 3: TODO bmp280@77 */
626 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
627 qdev_prop_set_string(dev, "description", "pca1");
628 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
629 aspeed_i2c_get_bus(&soc->i2c, 3),
630 &error_fatal);
631
632 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
633 led = led_create_simple(OBJECT(bmc),
634 pca1_leds[i].gpio_polarity,
635 pca1_leds[i].color,
636 pca1_leds[i].description);
637 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
638 qdev_get_gpio_in(DEVICE(led), 0));
639 }
640 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
641 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52);
642 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
643 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
644
645 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
646 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
647 0x4a);
648
649 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
650 * good enough */
651 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
652
653 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
654 eeprom_buf);
655 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
656 qdev_prop_set_string(dev, "description", "pca0");
657 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
658 aspeed_i2c_get_bus(&soc->i2c, 11),
659 &error_fatal);
660 /* Bus 11: TODO ucd90160@64 */
661 }
662
663 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
664 {
665 AspeedSoCState *soc = &bmc->soc;
666 DeviceState *dev;
667
668 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
669 "emc1413", 0x4c));
670 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
671 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
672 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
673
674 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
675 "emc1413", 0x4c));
676 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
677 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
678 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
679
680 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
681 "emc1413", 0x4c));
682 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
683 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
684 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
685
686 static uint8_t eeprom_buf[2 * 1024] = {
687 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
688 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
689 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
690 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
691 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
692 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
693 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
694 };
695 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
696 eeprom_buf);
697 }
698
699 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
700 {
701 AspeedSoCState *soc = &bmc->soc;
702 I2CSlave *i2c_mux;
703
704 /* The at24c256 */
705 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
706
707 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
708 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
709 0x48);
710 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
711 0x49);
712
713 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
714 "pca9546", 0x70);
715 /* It expects a TMP112 but a TMP105 is compatible */
716 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
717 0x4a);
718
719 /* It expects a ds3232 but a ds1338 is good enough */
720 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
721
722 /* It expects a pca9555 but a pca9552 is compatible */
723 create_pca9552(soc, 8, 0x30);
724 }
725
726 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
727 {
728 AspeedSoCState *soc = &bmc->soc;
729 I2CSlave *i2c_mux;
730
731 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
732
733 create_pca9552(soc, 3, 0x61);
734
735 /* The rainier expects a TMP275 but a TMP105 is compatible */
736 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
737 0x48);
738 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
739 0x49);
740 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
741 0x4a);
742 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
743 "pca9546", 0x70);
744 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
745 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
746 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
747 create_pca9552(soc, 4, 0x60);
748
749 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
750 0x48);
751 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
752 0x49);
753 create_pca9552(soc, 5, 0x60);
754 create_pca9552(soc, 5, 0x61);
755 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
756 "pca9546", 0x70);
757 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
758 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
759
760 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
761 0x48);
762 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
763 0x4a);
764 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
765 0x4b);
766 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
767 "pca9546", 0x70);
768 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
769 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
770 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
771 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
772
773 create_pca9552(soc, 7, 0x30);
774 create_pca9552(soc, 7, 0x31);
775 create_pca9552(soc, 7, 0x32);
776 create_pca9552(soc, 7, 0x33);
777 create_pca9552(soc, 7, 0x60);
778 create_pca9552(soc, 7, 0x61);
779 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
780 /* Bus 7: TODO si7021-a20@20 */
781 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
782 0x48);
783 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
784 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
785 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
786
787 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
788 0x48);
789 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
790 0x4a);
791 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
792 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
793 create_pca9552(soc, 8, 0x60);
794 create_pca9552(soc, 8, 0x61);
795 /* Bus 8: ucd90320@11 */
796 /* Bus 8: ucd90320@b */
797 /* Bus 8: ucd90320@c */
798
799 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
800 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
801 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
802
803 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
804 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
805 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
806
807 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
808 0x48);
809 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
810 0x49);
811 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
812 "pca9546", 0x70);
813 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
814 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
815 create_pca9552(soc, 11, 0x60);
816
817
818 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
819 create_pca9552(soc, 13, 0x60);
820
821 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
822 create_pca9552(soc, 14, 0x60);
823
824 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
825 create_pca9552(soc, 15, 0x60);
826 }
827
828 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
829 I2CBus **channels)
830 {
831 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
832 for (int i = 0; i < 8; i++) {
833 channels[i] = pca954x_i2c_get_bus(mux, i);
834 }
835 }
836
837 #define TYPE_LM75 TYPE_TMP105
838 #define TYPE_TMP75 TYPE_TMP105
839 #define TYPE_TMP422 "tmp422"
840
841 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
842 {
843 AspeedSoCState *soc = &bmc->soc;
844 I2CBus *i2c[144] = {};
845
846 for (int i = 0; i < 16; i++) {
847 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
848 }
849 I2CBus *i2c180 = i2c[2];
850 I2CBus *i2c480 = i2c[8];
851 I2CBus *i2c600 = i2c[11];
852
853 get_pca9548_channels(i2c180, 0x70, &i2c[16]);
854 get_pca9548_channels(i2c480, 0x70, &i2c[24]);
855 /* NOTE: The device tree skips [32, 40) in the alias numbering */
856 get_pca9548_channels(i2c600, 0x77, &i2c[40]);
857 get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
858 get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
859 get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
860 get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
861 for (int i = 0; i < 8; i++) {
862 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
863 }
864
865 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
866 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
867
868 /*
869 * EEPROM 24c64 size is 64Kbits or 8 Kbytes
870 * 24c02 size is 2Kbits or 256 bytes
871 */
872 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB);
873 at24c_eeprom_init(i2c[20], 0x50, 256);
874 at24c_eeprom_init(i2c[22], 0x52, 256);
875
876 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
877 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
878 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
879 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
880
881 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB);
882 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
883
884 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
885 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB);
886 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
887 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
888
889 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
890 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
891
892 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB);
893 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
894 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
895 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB);
896 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB);
897 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB);
898 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB);
899
900 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB);
901 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
902 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
903 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB);
904 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB);
905 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB);
906 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB);
907 at24c_eeprom_init(i2c[28], 0x50, 256);
908
909 for (int i = 0; i < 8; i++) {
910 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
911 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
912 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
913 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
914 }
915 }
916
917 #define TYPE_TMP421 "tmp421"
918
919 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
920 {
921 AspeedSoCState *soc = &bmc->soc;
922 I2CBus *i2c[13] = {};
923 for (int i = 0; i < 13; i++) {
924 if ((i == 8) || (i == 11)) {
925 continue;
926 }
927 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
928 }
929
930 /* Bus 0 - 5 all have the same config. */
931 for (int i = 0; i < 6; i++) {
932 /* Missing model: ti,ina230 @ 0x45 */
933 /* Missing model: mps,mp5023 @ 0x40 */
934 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f);
935 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */
936 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76);
937 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67);
938 /* Missing model: fsc,fusb302 @ 0x22 */
939 }
940
941 /* Bus 6 */
942 at24c_eeprom_init(i2c[6], 0x56, 65536);
943 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */
944 i2c_slave_create_simple(i2c[6], "ds1338", 0x51);
945
946
947 /* Bus 7 */
948 at24c_eeprom_init(i2c[7], 0x54, 65536);
949
950 /* Bus 9 */
951 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f);
952
953 /* Bus 10 */
954 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f);
955 /* Missing model: ti,hdc1080 @ 0x40 */
956 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67);
957
958 /* Bus 12 */
959 /* Missing model: adi,adm1278 @ 0x11 */
960 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c);
961 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d);
962 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
963 }
964
965 static void fby35_i2c_init(AspeedMachineState *bmc)
966 {
967 AspeedSoCState *soc = &bmc->soc;
968 I2CBus *i2c[16];
969
970 for (int i = 0; i < 16; i++) {
971 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
972 }
973
974 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f);
975 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f);
976 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */
977 i2c_slave_create_simple(i2c[11], "adm1272", 0x44);
978 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
979 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
980
981 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
982 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
983 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid,
984 fby35_nic_fruid_len);
985 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid,
986 fby35_bb_fruid_len);
987 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid,
988 fby35_bmc_fruid_len);
989
990 /*
991 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
992 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on
993 * each.
994 */
995 }
996
997 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
998 {
999 AspeedSoCState *soc = &bmc->soc;
1000
1001 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
1002 }
1003
1004 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
1005 {
1006 AspeedSoCState *soc = &bmc->soc;
1007 I2CSlave *therm_mux, *cpuvr_mux;
1008
1009 /* Create the generic DC-SCM hardware */
1010 qcom_dc_scm_bmc_i2c_init(bmc);
1011
1012 /* Now create the Firework specific hardware */
1013
1014 /* I2C7 CPUVR MUX */
1015 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
1016 "pca9546", 0x70);
1017 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72);
1018 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72);
1019 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72);
1020 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72);
1021
1022 /* I2C8 Thermal Diodes*/
1023 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
1024 "pca9548", 0x70);
1025 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C);
1026 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C);
1027 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48);
1028 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48);
1029 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48);
1030
1031 /* I2C9 Fan Controller (MAX31785) */
1032 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52);
1033 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54);
1034 }
1035
1036 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
1037 {
1038 return ASPEED_MACHINE(obj)->mmio_exec;
1039 }
1040
1041 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
1042 {
1043 ASPEED_MACHINE(obj)->mmio_exec = value;
1044 }
1045
1046 static void aspeed_machine_instance_init(Object *obj)
1047 {
1048 ASPEED_MACHINE(obj)->mmio_exec = false;
1049 }
1050
1051 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
1052 {
1053 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1054 return g_strdup(bmc->fmc_model);
1055 }
1056
1057 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
1058 {
1059 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1060
1061 g_free(bmc->fmc_model);
1062 bmc->fmc_model = g_strdup(value);
1063 }
1064
1065 static char *aspeed_get_spi_model(Object *obj, Error **errp)
1066 {
1067 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1068 return g_strdup(bmc->spi_model);
1069 }
1070
1071 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
1072 {
1073 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1074
1075 g_free(bmc->spi_model);
1076 bmc->spi_model = g_strdup(value);
1077 }
1078
1079 static void aspeed_machine_class_props_init(ObjectClass *oc)
1080 {
1081 object_class_property_add_bool(oc, "execute-in-place",
1082 aspeed_get_mmio_exec,
1083 aspeed_set_mmio_exec);
1084 object_class_property_set_description(oc, "execute-in-place",
1085 "boot directly from CE0 flash device");
1086
1087 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
1088 aspeed_set_fmc_model);
1089 object_class_property_set_description(oc, "fmc-model",
1090 "Change the FMC Flash model");
1091 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
1092 aspeed_set_spi_model);
1093 object_class_property_set_description(oc, "spi-model",
1094 "Change the SPI Flash model");
1095 }
1096
1097 static int aspeed_soc_num_cpus(const char *soc_name)
1098 {
1099 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
1100 return sc->num_cpus;
1101 }
1102
1103 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
1104 {
1105 MachineClass *mc = MACHINE_CLASS(oc);
1106 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1107
1108 mc->init = aspeed_machine_init;
1109 mc->no_floppy = 1;
1110 mc->no_cdrom = 1;
1111 mc->no_parallel = 1;
1112 mc->default_ram_id = "ram";
1113 amc->macs_mask = ASPEED_MAC0_ON;
1114 amc->uart_default = ASPEED_DEV_UART5;
1115
1116 aspeed_machine_class_props_init(oc);
1117 }
1118
1119 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
1120 {
1121 MachineClass *mc = MACHINE_CLASS(oc);
1122 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1123
1124 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
1125 amc->soc_name = "ast2400-a1";
1126 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
1127 amc->fmc_model = "n25q256a";
1128 amc->spi_model = "mx25l25635f";
1129 amc->num_cs = 1;
1130 amc->i2c_init = palmetto_bmc_i2c_init;
1131 mc->default_ram_size = 256 * MiB;
1132 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1133 aspeed_soc_num_cpus(amc->soc_name);
1134 };
1135
1136 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
1137 {
1138 MachineClass *mc = MACHINE_CLASS(oc);
1139 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1140
1141 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)";
1142 amc->soc_name = "ast2400-a1";
1143 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
1144 amc->fmc_model = "n25q256a";
1145 amc->spi_model = "mx25l25635e";
1146 amc->num_cs = 1;
1147 amc->i2c_init = quanta_q71l_bmc_i2c_init;
1148 mc->default_ram_size = 128 * MiB;
1149 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1150 aspeed_soc_num_cpus(amc->soc_name);
1151 }
1152
1153 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
1154 void *data)
1155 {
1156 MachineClass *mc = MACHINE_CLASS(oc);
1157 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1158
1159 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
1160 amc->soc_name = "ast2400-a1";
1161 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
1162 amc->fmc_model = "mx25l25635e";
1163 amc->spi_model = "mx25l25635e";
1164 amc->num_cs = 1;
1165 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1166 amc->i2c_init = palmetto_bmc_i2c_init;
1167 mc->default_ram_size = 256 * MiB;
1168 }
1169
1170 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
1171 void *data)
1172 {
1173 MachineClass *mc = MACHINE_CLASS(oc);
1174 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1175
1176 mc->desc = "Supermicro X11 SPI BMC (ARM1176)";
1177 amc->soc_name = "ast2500-a1";
1178 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1;
1179 amc->fmc_model = "mx25l25635e";
1180 amc->spi_model = "mx25l25635e";
1181 amc->num_cs = 1;
1182 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1183 amc->i2c_init = palmetto_bmc_i2c_init;
1184 mc->default_ram_size = 512 * MiB;
1185 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1186 aspeed_soc_num_cpus(amc->soc_name);
1187 }
1188
1189 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
1190 {
1191 MachineClass *mc = MACHINE_CLASS(oc);
1192 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1193
1194 mc->desc = "Aspeed AST2500 EVB (ARM1176)";
1195 amc->soc_name = "ast2500-a1";
1196 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1197 amc->fmc_model = "mx25l25635e";
1198 amc->spi_model = "mx25l25635f";
1199 amc->num_cs = 1;
1200 amc->i2c_init = ast2500_evb_i2c_init;
1201 mc->default_ram_size = 512 * MiB;
1202 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1203 aspeed_soc_num_cpus(amc->soc_name);
1204 };
1205
1206 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
1207 {
1208 MachineClass *mc = MACHINE_CLASS(oc);
1209 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1210
1211 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)";
1212 amc->soc_name = "ast2500-a1";
1213 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1214 amc->hw_strap2 = 0;
1215 amc->fmc_model = "n25q256a";
1216 amc->spi_model = "mx25l25635e";
1217 amc->num_cs = 2;
1218 amc->i2c_init = yosemitev2_bmc_i2c_init;
1219 mc->default_ram_size = 512 * MiB;
1220 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1221 aspeed_soc_num_cpus(amc->soc_name);
1222 };
1223
1224 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
1225 {
1226 MachineClass *mc = MACHINE_CLASS(oc);
1227 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1228
1229 mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
1230 amc->soc_name = "ast2500-a1";
1231 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
1232 amc->fmc_model = "n25q256a";
1233 amc->spi_model = "mx66l1g45g";
1234 amc->num_cs = 2;
1235 amc->i2c_init = romulus_bmc_i2c_init;
1236 mc->default_ram_size = 512 * MiB;
1237 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1238 aspeed_soc_num_cpus(amc->soc_name);
1239 };
1240
1241 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
1242 {
1243 MachineClass *mc = MACHINE_CLASS(oc);
1244 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1245
1246 mc->desc = "Facebook Tiogapass BMC (ARM1176)";
1247 amc->soc_name = "ast2500-a1";
1248 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1249 amc->hw_strap2 = 0;
1250 amc->fmc_model = "n25q256a";
1251 amc->spi_model = "mx25l25635e";
1252 amc->num_cs = 2;
1253 amc->i2c_init = tiogapass_bmc_i2c_init;
1254 mc->default_ram_size = 1 * GiB;
1255 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1256 aspeed_soc_num_cpus(amc->soc_name);
1257 aspeed_soc_num_cpus(amc->soc_name);
1258 };
1259
1260 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
1261 {
1262 MachineClass *mc = MACHINE_CLASS(oc);
1263 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1264
1265 mc->desc = "OCP SonoraPass BMC (ARM1176)";
1266 amc->soc_name = "ast2500-a1";
1267 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
1268 amc->fmc_model = "mx66l1g45g";
1269 amc->spi_model = "mx66l1g45g";
1270 amc->num_cs = 2;
1271 amc->i2c_init = sonorapass_bmc_i2c_init;
1272 mc->default_ram_size = 512 * MiB;
1273 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1274 aspeed_soc_num_cpus(amc->soc_name);
1275 };
1276
1277 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
1278 {
1279 MachineClass *mc = MACHINE_CLASS(oc);
1280 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1281
1282 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
1283 amc->soc_name = "ast2500-a1";
1284 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
1285 amc->fmc_model = "mx25l25635f";
1286 amc->spi_model = "mx66l1g45g";
1287 amc->num_cs = 2;
1288 amc->i2c_init = witherspoon_bmc_i2c_init;
1289 mc->default_ram_size = 512 * MiB;
1290 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1291 aspeed_soc_num_cpus(amc->soc_name);
1292 };
1293
1294 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
1295 {
1296 MachineClass *mc = MACHINE_CLASS(oc);
1297 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1298
1299 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)";
1300 amc->soc_name = "ast2600-a3";
1301 amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1302 amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
1303 amc->fmc_model = "mx66u51235f";
1304 amc->spi_model = "mx66u51235f";
1305 amc->num_cs = 1;
1306 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1307 ASPEED_MAC3_ON;
1308 amc->i2c_init = ast2600_evb_i2c_init;
1309 mc->default_ram_size = 1 * GiB;
1310 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1311 aspeed_soc_num_cpus(amc->soc_name);
1312 };
1313
1314 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
1315 {
1316 MachineClass *mc = MACHINE_CLASS(oc);
1317 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1318
1319 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)";
1320 amc->soc_name = "ast2600-a3";
1321 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
1322 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
1323 amc->fmc_model = "mx66l1g45g";
1324 amc->spi_model = "mx66l1g45g";
1325 amc->num_cs = 2;
1326 amc->macs_mask = ASPEED_MAC2_ON;
1327 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
1328 mc->default_ram_size = 1 * GiB;
1329 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1330 aspeed_soc_num_cpus(amc->soc_name);
1331 };
1332
1333 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
1334 {
1335 MachineClass *mc = MACHINE_CLASS(oc);
1336 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1337
1338 mc->desc = "Bytedance G220A BMC (ARM1176)";
1339 amc->soc_name = "ast2500-a1";
1340 amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1341 amc->fmc_model = "n25q512a";
1342 amc->spi_model = "mx25l25635e";
1343 amc->num_cs = 2;
1344 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1345 amc->i2c_init = g220a_bmc_i2c_init;
1346 mc->default_ram_size = 1024 * MiB;
1347 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1348 aspeed_soc_num_cpus(amc->soc_name);
1349 };
1350
1351 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
1352 {
1353 MachineClass *mc = MACHINE_CLASS(oc);
1354 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1355
1356 mc->desc = "Inspur FP5280G2 BMC (ARM1176)";
1357 amc->soc_name = "ast2500-a1";
1358 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
1359 amc->fmc_model = "n25q512a";
1360 amc->spi_model = "mx25l25635e";
1361 amc->num_cs = 2;
1362 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1363 amc->i2c_init = fp5280g2_bmc_i2c_init;
1364 mc->default_ram_size = 512 * MiB;
1365 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1366 aspeed_soc_num_cpus(amc->soc_name);
1367 };
1368
1369 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
1370 {
1371 MachineClass *mc = MACHINE_CLASS(oc);
1372 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1373
1374 mc->desc = "IBM Rainier BMC (Cortex-A7)";
1375 amc->soc_name = "ast2600-a3";
1376 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1377 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1378 amc->fmc_model = "mx66l1g45g";
1379 amc->spi_model = "mx66l1g45g";
1380 amc->num_cs = 2;
1381 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1382 amc->i2c_init = rainier_bmc_i2c_init;
1383 mc->default_ram_size = 1 * GiB;
1384 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1385 aspeed_soc_num_cpus(amc->soc_name);
1386 };
1387
1388 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1389 #if HOST_LONG_BITS == 32
1390 #define FUJI_BMC_RAM_SIZE (1 * GiB)
1391 #else
1392 #define FUJI_BMC_RAM_SIZE (2 * GiB)
1393 #endif
1394
1395 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
1396 {
1397 MachineClass *mc = MACHINE_CLASS(oc);
1398 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1399
1400 mc->desc = "Facebook Fuji BMC (Cortex-A7)";
1401 amc->soc_name = "ast2600-a3";
1402 amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
1403 amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
1404 amc->fmc_model = "mx66l1g45g";
1405 amc->spi_model = "mx66l1g45g";
1406 amc->num_cs = 2;
1407 amc->macs_mask = ASPEED_MAC3_ON;
1408 amc->i2c_init = fuji_bmc_i2c_init;
1409 amc->uart_default = ASPEED_DEV_UART1;
1410 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1411 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1412 aspeed_soc_num_cpus(amc->soc_name);
1413 };
1414
1415 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1416 #if HOST_LONG_BITS == 32
1417 #define BLETCHLEY_BMC_RAM_SIZE (1 * GiB)
1418 #else
1419 #define BLETCHLEY_BMC_RAM_SIZE (2 * GiB)
1420 #endif
1421
1422 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
1423 {
1424 MachineClass *mc = MACHINE_CLASS(oc);
1425 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1426
1427 mc->desc = "Facebook Bletchley BMC (Cortex-A7)";
1428 amc->soc_name = "ast2600-a3";
1429 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1;
1430 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2;
1431 amc->fmc_model = "w25q01jvq";
1432 amc->spi_model = NULL;
1433 amc->num_cs = 2;
1434 amc->macs_mask = ASPEED_MAC2_ON;
1435 amc->i2c_init = bletchley_bmc_i2c_init;
1436 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
1437 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1438 aspeed_soc_num_cpus(amc->soc_name);
1439 }
1440
1441 static void fby35_reset(MachineState *state, ShutdownCause reason)
1442 {
1443 AspeedMachineState *bmc = ASPEED_MACHINE(state);
1444 AspeedGPIOState *gpio = &bmc->soc.gpio;
1445
1446 qemu_devices_reset(reason);
1447
1448 /* Board ID: 7 (Class-1, 4 slots) */
1449 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);
1450 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);
1451 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);
1452 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);
1453
1454 /* Slot presence pins, inverse polarity. (False means present) */
1455 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal);
1456 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal);
1457 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal);
1458 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal);
1459
1460 /* Slot 12v power pins, normal polarity. (True means powered-on) */
1461 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal);
1462 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal);
1463 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal);
1464 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal);
1465 }
1466
1467 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
1468 {
1469 MachineClass *mc = MACHINE_CLASS(oc);
1470 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1471
1472 mc->desc = "Facebook fby35 BMC (Cortex-A7)";
1473 mc->reset = fby35_reset;
1474 amc->fmc_model = "mx66l1g45g";
1475 amc->num_cs = 2;
1476 amc->macs_mask = ASPEED_MAC3_ON;
1477 amc->i2c_init = fby35_i2c_init;
1478 /* FIXME: Replace this macro with something more general */
1479 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1480 }
1481
1482 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
1483 /* Main SYSCLK frequency in Hz (200MHz) */
1484 #define SYSCLK_FRQ 200000000ULL
1485
1486 static void aspeed_minibmc_machine_init(MachineState *machine)
1487 {
1488 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
1489 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
1490 Clock *sysclk;
1491
1492 sysclk = clock_new(OBJECT(machine), "SYSCLK");
1493 clock_set_hz(sysclk, SYSCLK_FRQ);
1494
1495 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
1496 qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
1497
1498 object_property_set_link(OBJECT(&bmc->soc), "memory",
1499 OBJECT(get_system_memory()), &error_abort);
1500 connect_serial_hds_to_uarts(bmc);
1501 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
1502
1503 aspeed_board_init_flashes(&bmc->soc.fmc,
1504 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
1505 amc->num_cs,
1506 0);
1507
1508 aspeed_board_init_flashes(&bmc->soc.spi[0],
1509 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1510 amc->num_cs, amc->num_cs);
1511
1512 aspeed_board_init_flashes(&bmc->soc.spi[1],
1513 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1514 amc->num_cs, (amc->num_cs * 2));
1515
1516 if (amc->i2c_init) {
1517 amc->i2c_init(bmc);
1518 }
1519
1520 armv7m_load_kernel(ARM_CPU(first_cpu),
1521 machine->kernel_filename,
1522 0,
1523 AST1030_INTERNAL_FLASH_SIZE);
1524 }
1525
1526 static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
1527 {
1528 AspeedSoCState *soc = &bmc->soc;
1529
1530 /* U10 24C08 connects to SDA/SCL Groupt 1 by default */
1531 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
1532 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
1533
1534 /* U11 LM75 connects to SDA/SCL Group 2 by default */
1535 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
1536 }
1537
1538 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
1539 void *data)
1540 {
1541 MachineClass *mc = MACHINE_CLASS(oc);
1542 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1543
1544 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
1545 amc->soc_name = "ast1030-a1";
1546 amc->hw_strap1 = 0;
1547 amc->hw_strap2 = 0;
1548 mc->init = aspeed_minibmc_machine_init;
1549 amc->i2c_init = ast1030_evb_i2c_init;
1550 mc->default_ram_size = 0;
1551 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
1552 amc->fmc_model = "sst25vf032b";
1553 amc->spi_model = "sst25vf032b";
1554 amc->num_cs = 2;
1555 amc->macs_mask = 0;
1556 }
1557
1558 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
1559 void *data)
1560 {
1561 MachineClass *mc = MACHINE_CLASS(oc);
1562 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1563
1564 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)";
1565 amc->soc_name = "ast2600-a3";
1566 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1567 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1568 amc->fmc_model = "n25q512a";
1569 amc->spi_model = "n25q512a";
1570 amc->num_cs = 2;
1571 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1572 amc->i2c_init = qcom_dc_scm_bmc_i2c_init;
1573 mc->default_ram_size = 1 * GiB;
1574 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1575 aspeed_soc_num_cpus(amc->soc_name);
1576 };
1577
1578 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
1579 void *data)
1580 {
1581 MachineClass *mc = MACHINE_CLASS(oc);
1582 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1583
1584 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)";
1585 amc->soc_name = "ast2600-a3";
1586 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1587 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1588 amc->fmc_model = "n25q512a";
1589 amc->spi_model = "n25q512a";
1590 amc->num_cs = 2;
1591 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1592 amc->i2c_init = qcom_dc_scm_firework_i2c_init;
1593 mc->default_ram_size = 1 * GiB;
1594 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1595 aspeed_soc_num_cpus(amc->soc_name);
1596 };
1597
1598 static const TypeInfo aspeed_machine_types[] = {
1599 {
1600 .name = MACHINE_TYPE_NAME("palmetto-bmc"),
1601 .parent = TYPE_ASPEED_MACHINE,
1602 .class_init = aspeed_machine_palmetto_class_init,
1603 }, {
1604 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
1605 .parent = TYPE_ASPEED_MACHINE,
1606 .class_init = aspeed_machine_supermicrox11_bmc_class_init,
1607 }, {
1608 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
1609 .parent = TYPE_ASPEED_MACHINE,
1610 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init,
1611 }, {
1612 .name = MACHINE_TYPE_NAME("ast2500-evb"),
1613 .parent = TYPE_ASPEED_MACHINE,
1614 .class_init = aspeed_machine_ast2500_evb_class_init,
1615 }, {
1616 .name = MACHINE_TYPE_NAME("romulus-bmc"),
1617 .parent = TYPE_ASPEED_MACHINE,
1618 .class_init = aspeed_machine_romulus_class_init,
1619 }, {
1620 .name = MACHINE_TYPE_NAME("sonorapass-bmc"),
1621 .parent = TYPE_ASPEED_MACHINE,
1622 .class_init = aspeed_machine_sonorapass_class_init,
1623 }, {
1624 .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
1625 .parent = TYPE_ASPEED_MACHINE,
1626 .class_init = aspeed_machine_witherspoon_class_init,
1627 }, {
1628 .name = MACHINE_TYPE_NAME("ast2600-evb"),
1629 .parent = TYPE_ASPEED_MACHINE,
1630 .class_init = aspeed_machine_ast2600_evb_class_init,
1631 }, {
1632 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"),
1633 .parent = TYPE_ASPEED_MACHINE,
1634 .class_init = aspeed_machine_yosemitev2_class_init,
1635 }, {
1636 .name = MACHINE_TYPE_NAME("tacoma-bmc"),
1637 .parent = TYPE_ASPEED_MACHINE,
1638 .class_init = aspeed_machine_tacoma_class_init,
1639 }, {
1640 .name = MACHINE_TYPE_NAME("tiogapass-bmc"),
1641 .parent = TYPE_ASPEED_MACHINE,
1642 .class_init = aspeed_machine_tiogapass_class_init,
1643 }, {
1644 .name = MACHINE_TYPE_NAME("g220a-bmc"),
1645 .parent = TYPE_ASPEED_MACHINE,
1646 .class_init = aspeed_machine_g220a_class_init,
1647 }, {
1648 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
1649 .parent = TYPE_ASPEED_MACHINE,
1650 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init,
1651 }, {
1652 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"),
1653 .parent = TYPE_ASPEED_MACHINE,
1654 .class_init = aspeed_machine_qcom_firework_class_init,
1655 }, {
1656 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"),
1657 .parent = TYPE_ASPEED_MACHINE,
1658 .class_init = aspeed_machine_fp5280g2_class_init,
1659 }, {
1660 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
1661 .parent = TYPE_ASPEED_MACHINE,
1662 .class_init = aspeed_machine_quanta_q71l_class_init,
1663 }, {
1664 .name = MACHINE_TYPE_NAME("rainier-bmc"),
1665 .parent = TYPE_ASPEED_MACHINE,
1666 .class_init = aspeed_machine_rainier_class_init,
1667 }, {
1668 .name = MACHINE_TYPE_NAME("fuji-bmc"),
1669 .parent = TYPE_ASPEED_MACHINE,
1670 .class_init = aspeed_machine_fuji_class_init,
1671 }, {
1672 .name = MACHINE_TYPE_NAME("bletchley-bmc"),
1673 .parent = TYPE_ASPEED_MACHINE,
1674 .class_init = aspeed_machine_bletchley_class_init,
1675 }, {
1676 .name = MACHINE_TYPE_NAME("fby35-bmc"),
1677 .parent = MACHINE_TYPE_NAME("ast2600-evb"),
1678 .class_init = aspeed_machine_fby35_class_init,
1679 }, {
1680 .name = MACHINE_TYPE_NAME("ast1030-evb"),
1681 .parent = TYPE_ASPEED_MACHINE,
1682 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
1683 }, {
1684 .name = TYPE_ASPEED_MACHINE,
1685 .parent = TYPE_MACHINE,
1686 .instance_size = sizeof(AspeedMachineState),
1687 .instance_init = aspeed_machine_instance_init,
1688 .class_size = sizeof(AspeedMachineClass),
1689 .class_init = aspeed_machine_class_init,
1690 .abstract = true,
1691 }
1692 };
1693
1694 DEFINE_TYPES(aspeed_machine_types)
QEMU mirror