hw/arm/aspeed.c

   1 /*
   2  * OpenPOWER Palmetto BMC
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  *
   6  * Copyright 2016 IBM Corp.
   7  *
   8  * This code is licensed under the GPL version 2 or later.  See
   9  * the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "qapi/error.h"
  14 #include "qemu-common.h"
  15 #include "cpu.h"
  16 #include "exec/address-spaces.h"
  17 #include "hw/arm/boot.h"
  18 #include "hw/arm/aspeed.h"
  19 #include "hw/arm/aspeed_soc.h"
  20 #include "hw/boards.h"
  21 #include "hw/i2c/smbus_eeprom.h"
  22 #include "hw/misc/pca9552.h"
  23 #include "hw/misc/tmp105.h"
  24 #include "qemu/log.h"
  25 #include "sysemu/block-backend.h"
  26 #include "hw/loader.h"
  27 #include "qemu/error-report.h"
  28 #include "qemu/units.h"
  29
  30 static struct arm_boot_info aspeed_board_binfo = {
  31     .board_id = -1, /* device-tree-only board */
  32     .nb_cpus = 1,
  33 };
  34
  35 struct AspeedBoardState {
  36     AspeedSoCState soc;
  37     MemoryRegion ram;
  38     MemoryRegion max_ram;
  39 };
  40
  41 /* Palmetto hardware value: 0x120CE416 */
  42 #define PALMETTO_BMC_HW_STRAP1 (                                        \
  43         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) |               \
  44         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
  45         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
  46         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) |       \
  47         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
  48         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
  49         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) |                \
  50         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
  51         SCU_HW_STRAP_SPI_WIDTH |                                        \
  52         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
  53         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
  54
  55 /* AST2500 evb hardware value: 0xF100C2E6 */
  56 #define AST2500_EVB_HW_STRAP1 ((                                        \
  57         AST2500_HW_STRAP1_DEFAULTS |                                    \
  58         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
  59         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
  60         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
  61         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
  62         SCU_HW_STRAP_MAC1_RGMII |                                       \
  63         SCU_HW_STRAP_MAC0_RGMII) &                                      \
  64         ~SCU_HW_STRAP_2ND_BOOT_WDT)
  65
  66 /* Romulus hardware value: 0xF10AD206 */
  67 #define ROMULUS_BMC_HW_STRAP1 (                                         \
  68         AST2500_HW_STRAP1_DEFAULTS |                                    \
  69         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
  70         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
  71         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
  72         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
  73         SCU_AST2500_HW_STRAP_ACPI_ENABLE |                              \
  74         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
  75
  76 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
  77 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
  78
  79 /*
  80  * The max ram region is for firmwares that scan the address space
  81  * with load/store to guess how much RAM the SoC has.
  82  */
  83 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size)
  84 {
  85     return 0;
  86 }
  87
  88 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value,
  89                            unsigned size)
  90 {
  91     /* Discard writes */
  92 }
  93
  94 static const MemoryRegionOps max_ram_ops = {
  95     .read = max_ram_read,
  96     .write = max_ram_write,
  97     .endianness = DEVICE_NATIVE_ENDIAN,
  98 };
  99
 100 #define FIRMWARE_ADDR 0x0
 101
 102 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
 103                            Error **errp)
 104 {
 105     BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
 106     uint8_t *storage;
 107     int64_t size;
 108
 109     /* The block backend size should have already been 'validated' by
 110      * the creation of the m25p80 object.
 111      */
 112     size = blk_getlength(blk);
 113     if (size <= 0) {
 114         error_setg(errp, "failed to get flash size");
 115         return;
 116     }
 117
 118     if (rom_size > size) {
 119         rom_size = size;
 120     }
 121
 122     storage = g_new0(uint8_t, rom_size);
 123     if (blk_pread(blk, 0, storage, rom_size) < 0) {
 124         error_setg(errp, "failed to read the initial flash content");
 125         return;
 126     }
 127
 128     rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
 129     g_free(storage);
 130 }
 131
 132 static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
 133                                       Error **errp)
 134 {
 135     int i ;
 136
 137     for (i = 0; i < s->num_cs; ++i) {
 138         AspeedSMCFlash *fl = &s->flashes[i];
 139         DriveInfo *dinfo = drive_get_next(IF_MTD);
 140         qemu_irq cs_line;
 141
 142         fl->flash = ssi_create_slave_no_init(s->spi, flashtype);
 143         if (dinfo) {
 144             qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo),
 145                                 errp);
 146         }
 147         qdev_init_nofail(fl->flash);
 148
 149         cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0);
 150         sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
 151     }
 152 }
 153
 154 static void aspeed_board_init(MachineState *machine,
 155                               const AspeedBoardConfig *cfg)
 156 {
 157     AspeedBoardState *bmc;
 158     AspeedSoCClass *sc;
 159     DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
 160     ram_addr_t max_ram_size;
 161
 162     bmc = g_new0(AspeedBoardState, 1);
 163     object_initialize_child(OBJECT(machine), "soc", &bmc->soc,
 164                             (sizeof(bmc->soc)), cfg->soc_name, &error_abort,
 165                             NULL);
 166
 167     sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
 168
 169     object_property_set_uint(OBJECT(&bmc->soc), ram_size, "ram-size",
 170                              &error_abort);
 171     object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1",
 172                             &error_abort);
 173     object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs",
 174                             &error_abort);
 175     if (machine->kernel_filename) {
 176         /*
 177          * When booting with a -kernel command line there is no u-boot
 178          * that runs to unlock the SCU. In this case set the default to
 179          * be unlocked as the kernel expects
 180          */
 181         object_property_set_int(OBJECT(&bmc->soc), ASPEED_SCU_PROT_KEY,
 182                                 "hw-prot-key", &error_abort);
 183     }
 184     object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
 185                              &error_abort);
 186
 187     /*
 188      * Allocate RAM after the memory controller has checked the size
 189      * was valid. If not, a default value is used.
 190      */
 191     ram_size = object_property_get_uint(OBJECT(&bmc->soc), "ram-size",
 192                                         &error_abort);
 193
 194     memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
 195     memory_region_add_subregion(get_system_memory(), sc->info->sdram_base,
 196                                 &bmc->ram);
 197     object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
 198                                    &error_abort);
 199
 200     max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
 201                                             &error_abort);
 202     memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
 203                           "max_ram", max_ram_size  - ram_size);
 204     memory_region_add_subregion(get_system_memory(),
 205                                 sc->info->sdram_base + ram_size,
 206                                 &bmc->max_ram);
 207
 208     aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort);
 209     aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort);
 210
 211     /* Install first FMC flash content as a boot rom. */
 212     if (drive0) {
 213         AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
 214         MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
 215
 216         /*
 217          * create a ROM region using the default mapping window size of
 218          * the flash module. The window size is 64MB for the AST2400
 219          * SoC and 128MB for the AST2500 SoC, which is twice as big as
 220          * needed by the flash modules of the Aspeed machines.
 221          */
 222         memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom",
 223                                fl->size, &error_abort);
 224         memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
 225                                     boot_rom);
 226         write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort);
 227     }
 228
 229     aspeed_board_binfo.kernel_filename = machine->kernel_filename;
 230     aspeed_board_binfo.initrd_filename = machine->initrd_filename;
 231     aspeed_board_binfo.kernel_cmdline = machine->kernel_cmdline;
 232     aspeed_board_binfo.ram_size = ram_size;
 233     aspeed_board_binfo.loader_start = sc->info->sdram_base;
 234
 235     if (cfg->i2c_init) {
 236         cfg->i2c_init(bmc);
 237     }
 238
 239     arm_load_kernel(ARM_CPU(first_cpu), &aspeed_board_binfo);
 240 }
 241
 242 static void palmetto_bmc_i2c_init(AspeedBoardState *bmc)
 243 {
 244     AspeedSoCState *soc = &bmc->soc;
 245     DeviceState *dev;
 246     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
 247
 248     /* The palmetto platform expects a ds3231 RTC but a ds1338 is
 249      * enough to provide basic RTC features. Alarms will be missing */
 250     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68);
 251
 252     smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), 0x50,
 253                           eeprom_buf);
 254
 255     /* add a TMP423 temperature sensor */
 256     dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2),
 257                            "tmp423", 0x4c);
 258     object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort);
 259     object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort);
 260     object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort);
 261     object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort);
 262 }
 263
 264 static void ast2500_evb_i2c_init(AspeedBoardState *bmc)
 265 {
 266     AspeedSoCState *soc = &bmc->soc;
 267     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 268
 269     smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), 0x50,
 270                           eeprom_buf);
 271
 272     /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
 273     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7),
 274                      TYPE_TMP105, 0x4d);
 275
 276     /* The AST2500 EVB does not have an RTC. Let's pretend that one is
 277      * plugged on the I2C bus header */
 278     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
 279 }
 280
 281 static void romulus_bmc_i2c_init(AspeedBoardState *bmc)
 282 {
 283     AspeedSoCState *soc = &bmc->soc;
 284
 285     /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
 286      * good enough */
 287     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
 288 }
 289
 290 static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
 291 {
 292     AspeedSoCState *soc = &bmc->soc;
 293     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 294
 295     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), TYPE_PCA9552,
 296                      0x60);
 297
 298     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "tmp423", 0x4c);
 299     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 5), "tmp423", 0x4c);
 300
 301     /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
 302     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), TYPE_TMP105,
 303                      0x4a);
 304
 305     /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
 306      * good enough */
 307     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
 308
 309     smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), 0x51,
 310                           eeprom_buf);
 311     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), TYPE_PCA9552,
 312                      0x60);
 313 }
 314
 315 static void aspeed_machine_init(MachineState *machine)
 316 {
 317     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
 318
 319     aspeed_board_init(machine, amc->board);
 320 }
 321
 322 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
 323 {
 324     MachineClass *mc = MACHINE_CLASS(oc);
 325     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
 326     const AspeedBoardConfig *board = data;
 327
 328     mc->desc = board->desc;
 329     mc->init = aspeed_machine_init;
 330     mc->max_cpus = 1;
 331     mc->no_sdcard = 1;
 332     mc->no_floppy = 1;
 333     mc->no_cdrom = 1;
 334     mc->no_parallel = 1;
 335     if (board->ram) {
 336         mc->default_ram_size = board->ram;
 337     }
 338     amc->board = board;
 339 }
 340
 341 static const TypeInfo aspeed_machine_type = {
 342     .name = TYPE_ASPEED_MACHINE,
 343     .parent = TYPE_MACHINE,
 344     .instance_size = sizeof(AspeedMachine),
 345     .class_size = sizeof(AspeedMachineClass),
 346     .abstract = true,
 347 };
 348
 349 static const AspeedBoardConfig aspeed_boards[] = {
 350     {
 351         .name      = MACHINE_TYPE_NAME("palmetto-bmc"),
 352         .desc      = "OpenPOWER Palmetto BMC (ARM926EJ-S)",
 353         .soc_name  = "ast2400-a1",
 354         .hw_strap1 = PALMETTO_BMC_HW_STRAP1,
 355         .fmc_model = "n25q256a",
 356         .spi_model = "mx25l25635e",
 357         .num_cs    = 1,
 358         .i2c_init  = palmetto_bmc_i2c_init,
 359         .ram       = 256 * MiB,
 360     }, {
 361         .name      = MACHINE_TYPE_NAME("ast2500-evb"),
 362         .desc      = "Aspeed AST2500 EVB (ARM1176)",
 363         .soc_name  = "ast2500-a1",
 364         .hw_strap1 = AST2500_EVB_HW_STRAP1,
 365         .fmc_model = "w25q256",
 366         .spi_model = "mx25l25635e",
 367         .num_cs    = 1,
 368         .i2c_init  = ast2500_evb_i2c_init,
 369         .ram       = 512 * MiB,
 370     }, {
 371         .name      = MACHINE_TYPE_NAME("romulus-bmc"),
 372         .desc      = "OpenPOWER Romulus BMC (ARM1176)",
 373         .soc_name  = "ast2500-a1",
 374         .hw_strap1 = ROMULUS_BMC_HW_STRAP1,
 375         .fmc_model = "n25q256a",
 376         .spi_model = "mx66l1g45g",
 377         .num_cs    = 2,
 378         .i2c_init  = romulus_bmc_i2c_init,
 379         .ram       = 512 * MiB,
 380     }, {
 381         .name      = MACHINE_TYPE_NAME("witherspoon-bmc"),
 382         .desc      = "OpenPOWER Witherspoon BMC (ARM1176)",
 383         .soc_name  = "ast2500-a1",
 384         .hw_strap1 = WITHERSPOON_BMC_HW_STRAP1,
 385         .fmc_model = "mx25l25635e",
 386         .spi_model = "mx66l1g45g",
 387         .num_cs    = 2,
 388         .i2c_init  = witherspoon_bmc_i2c_init,
 389         .ram       = 512 * MiB,
 390     },
 391 };
 392
 393 static void aspeed_machine_types(void)
 394 {
 395     int i;
 396
 397     type_register_static(&aspeed_machine_type);
 398     for (i = 0; i < ARRAY_SIZE(aspeed_boards); ++i) {
 399         TypeInfo ti = {
 400             .name       = aspeed_boards[i].name,
 401             .parent     = TYPE_ASPEED_MACHINE,
 402             .class_init = aspeed_machine_class_init,
 403             .class_data = (void *)&aspeed_boards[i],
 404         };
 405         type_register(&ti);
 406     }
 407 }
 408
 409 type_init(aspeed_machine_types)