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hw/arm/aspeed: Allow machine to set UART default
[mirror_qemu.git] / hw / arm / aspeed.c
1 /*
2 * OpenPOWER Palmetto BMC
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "hw/arm/boot.h"
15 #include "hw/arm/aspeed.h"
16 #include "hw/arm/aspeed_soc.h"
17 #include "hw/i2c/i2c_mux_pca954x.h"
18 #include "hw/i2c/smbus_eeprom.h"
19 #include "hw/misc/pca9552.h"
20 #include "hw/sensor/tmp105.h"
21 #include "hw/misc/led.h"
22 #include "hw/qdev-properties.h"
23 #include "sysemu/block-backend.h"
24 #include "hw/loader.h"
25 #include "qemu/error-report.h"
26 #include "qemu/units.h"
27
28 static struct arm_boot_info aspeed_board_binfo = {
29 .board_id = -1, /* device-tree-only board */
30 };
31
32 struct AspeedMachineState {
33 /* Private */
34 MachineState parent_obj;
35 /* Public */
36
37 AspeedSoCState soc;
38 MemoryRegion ram_container;
39 MemoryRegion max_ram;
40 bool mmio_exec;
41 char *fmc_model;
42 char *spi_model;
43 };
44
45 /* Palmetto hardware value: 0x120CE416 */
46 #define PALMETTO_BMC_HW_STRAP1 ( \
47 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
48 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
49 SCU_AST2400_HW_STRAP_ACPI_DIS | \
50 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
51 SCU_HW_STRAP_VGA_CLASS_CODE | \
52 SCU_HW_STRAP_LPC_RESET_PIN | \
53 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
54 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
55 SCU_HW_STRAP_SPI_WIDTH | \
56 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
57 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
58
59 /* TODO: Find the actual hardware value */
60 #define SUPERMICROX11_BMC_HW_STRAP1 ( \
61 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
62 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
63 SCU_AST2400_HW_STRAP_ACPI_DIS | \
64 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
65 SCU_HW_STRAP_VGA_CLASS_CODE | \
66 SCU_HW_STRAP_LPC_RESET_PIN | \
67 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
68 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
69 SCU_HW_STRAP_SPI_WIDTH | \
70 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
71 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
72
73 /* AST2500 evb hardware value: 0xF100C2E6 */
74 #define AST2500_EVB_HW_STRAP1 (( \
75 AST2500_HW_STRAP1_DEFAULTS | \
76 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
77 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
78 SCU_AST2500_HW_STRAP_UART_DEBUG | \
79 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
80 SCU_HW_STRAP_MAC1_RGMII | \
81 SCU_HW_STRAP_MAC0_RGMII) & \
82 ~SCU_HW_STRAP_2ND_BOOT_WDT)
83
84 /* Romulus hardware value: 0xF10AD206 */
85 #define ROMULUS_BMC_HW_STRAP1 ( \
86 AST2500_HW_STRAP1_DEFAULTS | \
87 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
88 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
89 SCU_AST2500_HW_STRAP_UART_DEBUG | \
90 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
91 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
92 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
93
94 /* Sonorapass hardware value: 0xF100D216 */
95 #define SONORAPASS_BMC_HW_STRAP1 ( \
96 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
97 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
98 SCU_AST2500_HW_STRAP_UART_DEBUG | \
99 SCU_AST2500_HW_STRAP_RESERVED28 | \
100 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
101 SCU_HW_STRAP_VGA_CLASS_CODE | \
102 SCU_HW_STRAP_LPC_RESET_PIN | \
103 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
104 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
105 SCU_HW_STRAP_VGA_BIOS_ROM | \
106 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
107 SCU_AST2500_HW_STRAP_RESERVED1)
108
109 /* Swift hardware value: 0xF11AD206 */
110 #define SWIFT_BMC_HW_STRAP1 ( \
111 AST2500_HW_STRAP1_DEFAULTS | \
112 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
113 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
114 SCU_AST2500_HW_STRAP_UART_DEBUG | \
115 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
116 SCU_H_PLL_BYPASS_EN | \
117 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
118 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
119
120 #define G220A_BMC_HW_STRAP1 ( \
121 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
122 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
123 SCU_AST2500_HW_STRAP_UART_DEBUG | \
124 SCU_AST2500_HW_STRAP_RESERVED28 | \
125 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
126 SCU_HW_STRAP_2ND_BOOT_WDT | \
127 SCU_HW_STRAP_VGA_CLASS_CODE | \
128 SCU_HW_STRAP_LPC_RESET_PIN | \
129 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
130 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
131 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \
132 SCU_AST2500_HW_STRAP_RESERVED1)
133
134 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
135 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
136
137 /* Quanta-Q71l hardware value */
138 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \
139 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
140 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
141 SCU_AST2400_HW_STRAP_ACPI_DIS | \
142 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \
143 SCU_HW_STRAP_VGA_CLASS_CODE | \
144 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \
145 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
146 SCU_HW_STRAP_SPI_WIDTH | \
147 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \
148 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
149
150 /* AST2600 evb hardware value */
151 #define AST2600_EVB_HW_STRAP1 0x000000C0
152 #define AST2600_EVB_HW_STRAP2 0x00000003
153
154 /* Tacoma hardware value */
155 #define TACOMA_BMC_HW_STRAP1 0x00000000
156 #define TACOMA_BMC_HW_STRAP2 0x00000040
157
158 /* Rainier hardware value: (QEMU prototype) */
159 #define RAINIER_BMC_HW_STRAP1 0x00000000
160 #define RAINIER_BMC_HW_STRAP2 0x00000000
161
162 /*
163 * The max ram region is for firmwares that scan the address space
164 * with load/store to guess how much RAM the SoC has.
165 */
166 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size)
167 {
168 return 0;
169 }
170
171 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value,
172 unsigned size)
173 {
174 /* Discard writes */
175 }
176
177 static const MemoryRegionOps max_ram_ops = {
178 .read = max_ram_read,
179 .write = max_ram_write,
180 .endianness = DEVICE_NATIVE_ENDIAN,
181 };
182
183 #define AST_SMP_MAILBOX_BASE 0x1e6e2180
184 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
185 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
186 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
187 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
188 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
189 #define AST_SMP_MBOX_GOSIGN 0xabbaab00
190
191 static void aspeed_write_smpboot(ARMCPU *cpu,
192 const struct arm_boot_info *info)
193 {
194 static const uint32_t poll_mailbox_ready[] = {
195 /*
196 * r2 = per-cpu go sign value
197 * r1 = AST_SMP_MBOX_FIELD_ENTRY
198 * r0 = AST_SMP_MBOX_FIELD_GOSIGN
199 */
200 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
201 0xe21000ff, /* ands r0, r0, #255 */
202 0xe59f201c, /* ldr r2, [pc, #28] */
203 0xe1822000, /* orr r2, r2, r0 */
204
205 0xe59f1018, /* ldr r1, [pc, #24] */
206 0xe59f0018, /* ldr r0, [pc, #24] */
207
208 0xe320f002, /* wfe */
209 0xe5904000, /* ldr r4, [r0] */
210 0xe1520004, /* cmp r2, r4 */
211 0x1afffffb, /* bne <wfe> */
212 0xe591f000, /* ldr pc, [r1] */
213 AST_SMP_MBOX_GOSIGN,
214 AST_SMP_MBOX_FIELD_ENTRY,
215 AST_SMP_MBOX_FIELD_GOSIGN,
216 };
217
218 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
219 sizeof(poll_mailbox_ready),
220 info->smp_loader_start);
221 }
222
223 static void aspeed_reset_secondary(ARMCPU *cpu,
224 const struct arm_boot_info *info)
225 {
226 AddressSpace *as = arm_boot_address_space(cpu, info);
227 CPUState *cs = CPU(cpu);
228
229 /* info->smp_bootreg_addr */
230 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
231 MEMTXATTRS_UNSPECIFIED, NULL);
232 cpu_set_pc(cs, info->smp_loader_start);
233 }
234
235 #define FIRMWARE_ADDR 0x0
236
237 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
238 Error **errp)
239 {
240 BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
241 uint8_t *storage;
242 int64_t size;
243
244 /* The block backend size should have already been 'validated' by
245 * the creation of the m25p80 object.
246 */
247 size = blk_getlength(blk);
248 if (size <= 0) {
249 error_setg(errp, "failed to get flash size");
250 return;
251 }
252
253 if (rom_size > size) {
254 rom_size = size;
255 }
256
257 storage = g_new0(uint8_t, rom_size);
258 if (blk_pread(blk, 0, storage, rom_size) < 0) {
259 error_setg(errp, "failed to read the initial flash content");
260 return;
261 }
262
263 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
264 g_free(storage);
265 }
266
267 static void aspeed_board_init_flashes(AspeedSMCState *s,
268 const char *flashtype)
269 {
270 int i ;
271
272 for (i = 0; i < s->num_cs; ++i) {
273 AspeedSMCFlash *fl = &s->flashes[i];
274 DriveInfo *dinfo = drive_get_next(IF_MTD);
275 qemu_irq cs_line;
276
277 fl->flash = qdev_new(flashtype);
278 if (dinfo) {
279 qdev_prop_set_drive(fl->flash, "drive",
280 blk_by_legacy_dinfo(dinfo));
281 }
282 qdev_realize_and_unref(fl->flash, BUS(s->spi), &error_fatal);
283
284 cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0);
285 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
286 }
287 }
288
289 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
290 {
291 DeviceState *card;
292
293 if (!dinfo) {
294 return;
295 }
296 card = qdev_new(TYPE_SD_CARD);
297 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
298 &error_fatal);
299 qdev_realize_and_unref(card,
300 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
301 &error_fatal);
302 }
303
304 static void aspeed_machine_init(MachineState *machine)
305 {
306 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
307 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
308 AspeedSoCClass *sc;
309 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
310 ram_addr_t max_ram_size;
311 int i;
312 NICInfo *nd = &nd_table[0];
313
314 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container",
315 4 * GiB);
316 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram);
317
318 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
319
320 sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
321
322 /*
323 * This will error out if isize is not supported by memory controller.
324 */
325 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
326 &error_fatal);
327
328 for (i = 0; i < sc->macs_num; i++) {
329 if ((amc->macs_mask & (1 << i)) && nd->used) {
330 qemu_check_nic_model(nd, TYPE_FTGMAC100);
331 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
332 nd++;
333 }
334 }
335
336 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
337 &error_abort);
338 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
339 &error_abort);
340 object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs,
341 &error_abort);
342 object_property_set_link(OBJECT(&bmc->soc), "dram",
343 OBJECT(machine->ram), &error_abort);
344 if (machine->kernel_filename) {
345 /*
346 * When booting with a -kernel command line there is no u-boot
347 * that runs to unlock the SCU. In this case set the default to
348 * be unlocked as the kernel expects
349 */
350 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
351 ASPEED_SCU_PROT_KEY, &error_abort);
352 }
353 qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default",
354 amc->uart_default);
355 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
356
357 memory_region_add_subregion(get_system_memory(),
358 sc->memmap[ASPEED_DEV_SDRAM],
359 &bmc->ram_container);
360
361 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
362 &error_abort);
363 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
364 "max_ram", max_ram_size - machine->ram_size);
365 memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram);
366
367 aspeed_board_init_flashes(&bmc->soc.fmc, bmc->fmc_model ?
368 bmc->fmc_model : amc->fmc_model);
369 aspeed_board_init_flashes(&bmc->soc.spi[0], bmc->spi_model ?
370 bmc->spi_model : amc->spi_model);
371
372 /* Install first FMC flash content as a boot rom. */
373 if (drive0) {
374 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
375 MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
376
377 /*
378 * create a ROM region using the default mapping window size of
379 * the flash module. The window size is 64MB for the AST2400
380 * SoC and 128MB for the AST2500 SoC, which is twice as big as
381 * needed by the flash modules of the Aspeed machines.
382 */
383 if (ASPEED_MACHINE(machine)->mmio_exec) {
384 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom",
385 &fl->mmio, 0, fl->size);
386 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
387 boot_rom);
388 } else {
389 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom",
390 fl->size, &error_abort);
391 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
392 boot_rom);
393 write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort);
394 }
395 }
396
397 if (machine->kernel_filename && sc->num_cpus > 1) {
398 /* With no u-boot we must set up a boot stub for the secondary CPU */
399 MemoryRegion *smpboot = g_new(MemoryRegion, 1);
400 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
401 0x80, &error_abort);
402 memory_region_add_subregion(get_system_memory(),
403 AST_SMP_MAILBOX_BASE, smpboot);
404
405 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
406 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
407 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
408 }
409
410 aspeed_board_binfo.ram_size = machine->ram_size;
411 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
412 aspeed_board_binfo.nb_cpus = sc->num_cpus;
413
414 if (amc->i2c_init) {
415 amc->i2c_init(bmc);
416 }
417
418 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
419 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD));
420 }
421
422 if (bmc->soc.emmc.num_slots) {
423 sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD));
424 }
425
426 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
427 }
428
429 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
430 {
431 AspeedSoCState *soc = &bmc->soc;
432 DeviceState *dev;
433 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
434
435 /* The palmetto platform expects a ds3231 RTC but a ds1338 is
436 * enough to provide basic RTC features. Alarms will be missing */
437 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
438
439 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
440 eeprom_buf);
441
442 /* add a TMP423 temperature sensor */
443 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
444 "tmp423", 0x4c));
445 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
446 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
447 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
448 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
449 }
450
451 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
452 {
453 AspeedSoCState *soc = &bmc->soc;
454
455 /*
456 * The quanta-q71l platform expects tmp75s which are compatible with
457 * tmp105s.
458 */
459 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
460 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
461 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
462
463 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
464 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
465 /* TODO: Add Memory Riser i2c mux and eeproms. */
466
467 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
468 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
469
470 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
471
472 /* i2c-7 */
473 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
474 /* - i2c@0: pmbus@59 */
475 /* - i2c@1: pmbus@58 */
476 /* - i2c@2: pmbus@58 */
477 /* - i2c@3: pmbus@59 */
478
479 /* TODO: i2c-7: Add PDB FRU eeprom@52 */
480 /* TODO: i2c-8: Add BMC FRU eeprom@50 */
481 }
482
483 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
484 {
485 AspeedSoCState *soc = &bmc->soc;
486 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
487
488 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
489 eeprom_buf);
490
491 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
492 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
493 TYPE_TMP105, 0x4d);
494
495 /* The AST2500 EVB does not have an RTC. Let's pretend that one is
496 * plugged on the I2C bus header */
497 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
498 }
499
500 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
501 {
502 /* Start with some devices on our I2C busses */
503 ast2500_evb_i2c_init(bmc);
504 }
505
506 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
507 {
508 AspeedSoCState *soc = &bmc->soc;
509
510 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
511 * good enough */
512 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
513 }
514
515 static void swift_bmc_i2c_init(AspeedMachineState *bmc)
516 {
517 AspeedSoCState *soc = &bmc->soc;
518
519 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x60);
520
521 /* The swift board expects a TMP275 but a TMP105 is compatible */
522 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "tmp105", 0x48);
523 /* The swift board expects a pca9551 but a pca9552 is compatible */
524 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60);
525
526 /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */
527 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "ds1338", 0x32);
528 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
529
530 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
531 /* The swift board expects a pca9539 but a pca9552 is compatible */
532 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "pca9552", 0x74);
533
534 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
535 /* The swift board expects a pca9539 but a pca9552 is compatible */
536 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "pca9552",
537 0x74);
538
539 /* The swift board expects a TMP275 but a TMP105 is compatible */
540 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x48);
541 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x4a);
542 }
543
544 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
545 {
546 AspeedSoCState *soc = &bmc->soc;
547
548 /* bus 2 : */
549 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
550 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
551 /* bus 2 : pca9546 @ 0x73 */
552
553 /* bus 3 : pca9548 @ 0x70 */
554
555 /* bus 4 : */
556 uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
557 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
558 eeprom4_54);
559 /* PCA9539 @ 0x76, but PCA9552 is compatible */
560 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x76);
561 /* PCA9539 @ 0x77, but PCA9552 is compatible */
562 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x77);
563
564 /* bus 6 : */
565 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
566 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
567 /* bus 6 : pca9546 @ 0x73 */
568
569 /* bus 8 : */
570 uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
571 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
572 eeprom8_56);
573 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
574 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
575 /* bus 8 : adc128d818 @ 0x1d */
576 /* bus 8 : adc128d818 @ 0x1f */
577
578 /*
579 * bus 13 : pca9548 @ 0x71
580 * - channel 3:
581 * - tmm421 @ 0x4c
582 * - tmp421 @ 0x4e
583 * - tmp421 @ 0x4f
584 */
585
586 }
587
588 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
589 {
590 static const struct {
591 unsigned gpio_id;
592 LEDColor color;
593 const char *description;
594 bool gpio_polarity;
595 } pca1_leds[] = {
596 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW},
597 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
598 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
599 };
600 AspeedSoCState *soc = &bmc->soc;
601 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
602 DeviceState *dev;
603 LEDState *led;
604
605 /* Bus 3: TODO bmp280@77 */
606 /* Bus 3: TODO max31785@52 */
607 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
608 qdev_prop_set_string(dev, "description", "pca1");
609 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
610 aspeed_i2c_get_bus(&soc->i2c, 3),
611 &error_fatal);
612
613 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
614 led = led_create_simple(OBJECT(bmc),
615 pca1_leds[i].gpio_polarity,
616 pca1_leds[i].color,
617 pca1_leds[i].description);
618 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
619 qdev_get_gpio_in(DEVICE(led), 0));
620 }
621 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
622 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
623 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
624
625 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
626 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
627 0x4a);
628
629 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
630 * good enough */
631 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
632
633 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
634 eeprom_buf);
635 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
636 qdev_prop_set_string(dev, "description", "pca0");
637 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
638 aspeed_i2c_get_bus(&soc->i2c, 11),
639 &error_fatal);
640 /* Bus 11: TODO ucd90160@64 */
641 }
642
643 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
644 {
645 AspeedSoCState *soc = &bmc->soc;
646 DeviceState *dev;
647
648 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
649 "emc1413", 0x4c));
650 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
651 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
652 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
653
654 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
655 "emc1413", 0x4c));
656 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
657 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
658 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
659
660 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
661 "emc1413", 0x4c));
662 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
663 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
664 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
665
666 static uint8_t eeprom_buf[2 * 1024] = {
667 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
668 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
669 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
670 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
671 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
672 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
673 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
674 };
675 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
676 eeprom_buf);
677 }
678
679 static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
680 {
681 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
682 DeviceState *dev = DEVICE(i2c_dev);
683
684 qdev_prop_set_uint32(dev, "rom-size", rsize);
685 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
686 }
687
688 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
689 {
690 AspeedSoCState *soc = &bmc->soc;
691 I2CSlave *i2c_mux;
692
693 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
694
695 /* The rainier expects a TMP275 but a TMP105 is compatible */
696 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
697 0x48);
698 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
699 0x49);
700 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
701 0x4a);
702 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
703 "pca9546", 0x70);
704 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
705 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
706 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
707
708 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
709 0x48);
710 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
711 0x49);
712 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
713 "pca9546", 0x70);
714 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
715 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
716
717 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
718 0x48);
719 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
720 0x4a);
721 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
722 0x4b);
723 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
724 "pca9546", 0x70);
725 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
726 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
727 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
728 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
729
730 /* Bus 7: TODO max31785@52 */
731 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x61);
732 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
733 /* Bus 7: TODO si7021-a20@20 */
734 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
735 0x48);
736 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
737 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
738
739 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
740 0x48);
741 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
742 0x4a);
743 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
744 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
745 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
746 /* Bus 8: ucd90320@11 */
747 /* Bus 8: ucd90320@b */
748 /* Bus 8: ucd90320@c */
749
750 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
751 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
752 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
753
754 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
755 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
756 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
757
758 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
759 0x48);
760 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
761 0x49);
762 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
763 "pca9546", 0x70);
764 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
765 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
766
767
768 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
769
770 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
771
772 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
773 }
774
775 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
776 {
777 return ASPEED_MACHINE(obj)->mmio_exec;
778 }
779
780 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
781 {
782 ASPEED_MACHINE(obj)->mmio_exec = value;
783 }
784
785 static void aspeed_machine_instance_init(Object *obj)
786 {
787 ASPEED_MACHINE(obj)->mmio_exec = false;
788 }
789
790 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
791 {
792 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
793 return g_strdup(bmc->fmc_model);
794 }
795
796 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
797 {
798 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
799
800 g_free(bmc->fmc_model);
801 bmc->fmc_model = g_strdup(value);
802 }
803
804 static char *aspeed_get_spi_model(Object *obj, Error **errp)
805 {
806 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
807 return g_strdup(bmc->spi_model);
808 }
809
810 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
811 {
812 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
813
814 g_free(bmc->spi_model);
815 bmc->spi_model = g_strdup(value);
816 }
817
818 static void aspeed_machine_class_props_init(ObjectClass *oc)
819 {
820 object_class_property_add_bool(oc, "execute-in-place",
821 aspeed_get_mmio_exec,
822 aspeed_set_mmio_exec);
823 object_class_property_set_description(oc, "execute-in-place",
824 "boot directly from CE0 flash device");
825
826 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
827 aspeed_set_fmc_model);
828 object_class_property_set_description(oc, "fmc-model",
829 "Change the FMC Flash model");
830 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
831 aspeed_set_spi_model);
832 object_class_property_set_description(oc, "spi-model",
833 "Change the SPI Flash model");
834 }
835
836 static int aspeed_soc_num_cpus(const char *soc_name)
837 {
838 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
839 return sc->num_cpus;
840 }
841
842 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
843 {
844 MachineClass *mc = MACHINE_CLASS(oc);
845 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
846
847 mc->init = aspeed_machine_init;
848 mc->no_floppy = 1;
849 mc->no_cdrom = 1;
850 mc->no_parallel = 1;
851 mc->default_ram_id = "ram";
852 amc->macs_mask = ASPEED_MAC0_ON;
853 amc->uart_default = ASPEED_DEV_UART5;
854
855 aspeed_machine_class_props_init(oc);
856 }
857
858 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
859 {
860 MachineClass *mc = MACHINE_CLASS(oc);
861 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
862
863 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
864 amc->soc_name = "ast2400-a1";
865 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
866 amc->fmc_model = "n25q256a";
867 amc->spi_model = "mx25l25635e";
868 amc->num_cs = 1;
869 amc->i2c_init = palmetto_bmc_i2c_init;
870 mc->default_ram_size = 256 * MiB;
871 mc->default_cpus = mc->min_cpus = mc->max_cpus =
872 aspeed_soc_num_cpus(amc->soc_name);
873 };
874
875 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
876 {
877 MachineClass *mc = MACHINE_CLASS(oc);
878 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
879
880 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)";
881 amc->soc_name = "ast2400-a1";
882 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
883 amc->fmc_model = "n25q256a";
884 amc->spi_model = "mx25l25635e";
885 amc->num_cs = 1;
886 amc->i2c_init = quanta_q71l_bmc_i2c_init;
887 mc->default_ram_size = 128 * MiB;
888 mc->default_cpus = mc->min_cpus = mc->max_cpus =
889 aspeed_soc_num_cpus(amc->soc_name);
890 }
891
892 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
893 void *data)
894 {
895 MachineClass *mc = MACHINE_CLASS(oc);
896 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
897
898 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
899 amc->soc_name = "ast2400-a1";
900 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
901 amc->fmc_model = "mx25l25635e";
902 amc->spi_model = "mx25l25635e";
903 amc->num_cs = 1;
904 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
905 amc->i2c_init = palmetto_bmc_i2c_init;
906 mc->default_ram_size = 256 * MiB;
907 }
908
909 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
910 {
911 MachineClass *mc = MACHINE_CLASS(oc);
912 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
913
914 mc->desc = "Aspeed AST2500 EVB (ARM1176)";
915 amc->soc_name = "ast2500-a1";
916 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
917 amc->fmc_model = "w25q256";
918 amc->spi_model = "mx25l25635e";
919 amc->num_cs = 1;
920 amc->i2c_init = ast2500_evb_i2c_init;
921 mc->default_ram_size = 512 * MiB;
922 mc->default_cpus = mc->min_cpus = mc->max_cpus =
923 aspeed_soc_num_cpus(amc->soc_name);
924 };
925
926 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
927 {
928 MachineClass *mc = MACHINE_CLASS(oc);
929 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
930
931 mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
932 amc->soc_name = "ast2500-a1";
933 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
934 amc->fmc_model = "n25q256a";
935 amc->spi_model = "mx66l1g45g";
936 amc->num_cs = 2;
937 amc->i2c_init = romulus_bmc_i2c_init;
938 mc->default_ram_size = 512 * MiB;
939 mc->default_cpus = mc->min_cpus = mc->max_cpus =
940 aspeed_soc_num_cpus(amc->soc_name);
941 };
942
943 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
944 {
945 MachineClass *mc = MACHINE_CLASS(oc);
946 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
947
948 mc->desc = "OCP SonoraPass BMC (ARM1176)";
949 amc->soc_name = "ast2500-a1";
950 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
951 amc->fmc_model = "mx66l1g45g";
952 amc->spi_model = "mx66l1g45g";
953 amc->num_cs = 2;
954 amc->i2c_init = sonorapass_bmc_i2c_init;
955 mc->default_ram_size = 512 * MiB;
956 mc->default_cpus = mc->min_cpus = mc->max_cpus =
957 aspeed_soc_num_cpus(amc->soc_name);
958 };
959
960 static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data)
961 {
962 MachineClass *mc = MACHINE_CLASS(oc);
963 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
964
965 mc->desc = "OpenPOWER Swift BMC (ARM1176)";
966 amc->soc_name = "ast2500-a1";
967 amc->hw_strap1 = SWIFT_BMC_HW_STRAP1;
968 amc->fmc_model = "mx66l1g45g";
969 amc->spi_model = "mx66l1g45g";
970 amc->num_cs = 2;
971 amc->i2c_init = swift_bmc_i2c_init;
972 mc->default_ram_size = 512 * MiB;
973 mc->default_cpus = mc->min_cpus = mc->max_cpus =
974 aspeed_soc_num_cpus(amc->soc_name);
975
976 mc->deprecation_reason = "redundant system. Please use a similar "
977 "OpenPOWER BMC, Witherspoon or Romulus.";
978 };
979
980 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
981 {
982 MachineClass *mc = MACHINE_CLASS(oc);
983 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
984
985 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
986 amc->soc_name = "ast2500-a1";
987 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
988 amc->fmc_model = "mx25l25635e";
989 amc->spi_model = "mx66l1g45g";
990 amc->num_cs = 2;
991 amc->i2c_init = witherspoon_bmc_i2c_init;
992 mc->default_ram_size = 512 * MiB;
993 mc->default_cpus = mc->min_cpus = mc->max_cpus =
994 aspeed_soc_num_cpus(amc->soc_name);
995 };
996
997 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
998 {
999 MachineClass *mc = MACHINE_CLASS(oc);
1000 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1001
1002 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)";
1003 amc->soc_name = "ast2600-a3";
1004 amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1005 amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
1006 amc->fmc_model = "w25q512jv";
1007 amc->spi_model = "mx66u51235f";
1008 amc->num_cs = 1;
1009 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1010 ASPEED_MAC3_ON;
1011 amc->i2c_init = ast2600_evb_i2c_init;
1012 mc->default_ram_size = 1 * GiB;
1013 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1014 aspeed_soc_num_cpus(amc->soc_name);
1015 };
1016
1017 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
1018 {
1019 MachineClass *mc = MACHINE_CLASS(oc);
1020 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1021
1022 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)";
1023 amc->soc_name = "ast2600-a3";
1024 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
1025 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
1026 amc->fmc_model = "mx66l1g45g";
1027 amc->spi_model = "mx66l1g45g";
1028 amc->num_cs = 2;
1029 amc->macs_mask = ASPEED_MAC2_ON;
1030 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
1031 mc->default_ram_size = 1 * GiB;
1032 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1033 aspeed_soc_num_cpus(amc->soc_name);
1034 };
1035
1036 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
1037 {
1038 MachineClass *mc = MACHINE_CLASS(oc);
1039 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1040
1041 mc->desc = "Bytedance G220A BMC (ARM1176)";
1042 amc->soc_name = "ast2500-a1";
1043 amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1044 amc->fmc_model = "n25q512a";
1045 amc->spi_model = "mx25l25635e";
1046 amc->num_cs = 2;
1047 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1048 amc->i2c_init = g220a_bmc_i2c_init;
1049 mc->default_ram_size = 1024 * MiB;
1050 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1051 aspeed_soc_num_cpus(amc->soc_name);
1052 };
1053
1054 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
1055 {
1056 MachineClass *mc = MACHINE_CLASS(oc);
1057 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1058
1059 mc->desc = "IBM Rainier BMC (Cortex-A7)";
1060 amc->soc_name = "ast2600-a3";
1061 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1062 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1063 amc->fmc_model = "mx66l1g45g";
1064 amc->spi_model = "mx66l1g45g";
1065 amc->num_cs = 2;
1066 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1067 amc->i2c_init = rainier_bmc_i2c_init;
1068 mc->default_ram_size = 1 * GiB;
1069 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1070 aspeed_soc_num_cpus(amc->soc_name);
1071 };
1072
1073 static const TypeInfo aspeed_machine_types[] = {
1074 {
1075 .name = MACHINE_TYPE_NAME("palmetto-bmc"),
1076 .parent = TYPE_ASPEED_MACHINE,
1077 .class_init = aspeed_machine_palmetto_class_init,
1078 }, {
1079 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
1080 .parent = TYPE_ASPEED_MACHINE,
1081 .class_init = aspeed_machine_supermicrox11_bmc_class_init,
1082 }, {
1083 .name = MACHINE_TYPE_NAME("ast2500-evb"),
1084 .parent = TYPE_ASPEED_MACHINE,
1085 .class_init = aspeed_machine_ast2500_evb_class_init,
1086 }, {
1087 .name = MACHINE_TYPE_NAME("romulus-bmc"),
1088 .parent = TYPE_ASPEED_MACHINE,
1089 .class_init = aspeed_machine_romulus_class_init,
1090 }, {
1091 .name = MACHINE_TYPE_NAME("swift-bmc"),
1092 .parent = TYPE_ASPEED_MACHINE,
1093 .class_init = aspeed_machine_swift_class_init,
1094 }, {
1095 .name = MACHINE_TYPE_NAME("sonorapass-bmc"),
1096 .parent = TYPE_ASPEED_MACHINE,
1097 .class_init = aspeed_machine_sonorapass_class_init,
1098 }, {
1099 .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
1100 .parent = TYPE_ASPEED_MACHINE,
1101 .class_init = aspeed_machine_witherspoon_class_init,
1102 }, {
1103 .name = MACHINE_TYPE_NAME("ast2600-evb"),
1104 .parent = TYPE_ASPEED_MACHINE,
1105 .class_init = aspeed_machine_ast2600_evb_class_init,
1106 }, {
1107 .name = MACHINE_TYPE_NAME("tacoma-bmc"),
1108 .parent = TYPE_ASPEED_MACHINE,
1109 .class_init = aspeed_machine_tacoma_class_init,
1110 }, {
1111 .name = MACHINE_TYPE_NAME("g220a-bmc"),
1112 .parent = TYPE_ASPEED_MACHINE,
1113 .class_init = aspeed_machine_g220a_class_init,
1114 }, {
1115 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
1116 .parent = TYPE_ASPEED_MACHINE,
1117 .class_init = aspeed_machine_quanta_q71l_class_init,
1118 }, {
1119 .name = MACHINE_TYPE_NAME("rainier-bmc"),
1120 .parent = TYPE_ASPEED_MACHINE,
1121 .class_init = aspeed_machine_rainier_class_init,
1122 }, {
1123 .name = TYPE_ASPEED_MACHINE,
1124 .parent = TYPE_MACHINE,
1125 .instance_size = sizeof(AspeedMachineState),
1126 .instance_init = aspeed_machine_instance_init,
1127 .class_size = sizeof(AspeedMachineClass),
1128 .class_init = aspeed_machine_class_init,
1129 .abstract = true,
1130 }
1131 };
1132
1133 DEFINE_TYPES(aspeed_machine_types)
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