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aspeed: Add support for the quanta-q7l1-bmc board
[mirror_qemu.git] / hw / arm / aspeed.c
1 /*
2 * OpenPOWER Palmetto BMC
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "cpu.h"
15 #include "exec/address-spaces.h"
16 #include "hw/arm/boot.h"
17 #include "hw/arm/aspeed.h"
18 #include "hw/arm/aspeed_soc.h"
19 #include "hw/boards.h"
20 #include "hw/i2c/smbus_eeprom.h"
21 #include "hw/misc/pca9552.h"
22 #include "hw/misc/tmp105.h"
23 #include "hw/misc/led.h"
24 #include "hw/qdev-properties.h"
25 #include "qemu/log.h"
26 #include "sysemu/block-backend.h"
27 #include "sysemu/sysemu.h"
28 #include "hw/loader.h"
29 #include "qemu/error-report.h"
30 #include "qemu/units.h"
31
32 static struct arm_boot_info aspeed_board_binfo = {
33 .board_id = -1, /* device-tree-only board */
34 };
35
36 struct AspeedMachineState {
37 /* Private */
38 MachineState parent_obj;
39 /* Public */
40
41 AspeedSoCState soc;
42 MemoryRegion ram_container;
43 MemoryRegion max_ram;
44 bool mmio_exec;
45 char *fmc_model;
46 char *spi_model;
47 };
48
49 /* Palmetto hardware value: 0x120CE416 */
50 #define PALMETTO_BMC_HW_STRAP1 ( \
51 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
52 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
53 SCU_AST2400_HW_STRAP_ACPI_DIS | \
54 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
55 SCU_HW_STRAP_VGA_CLASS_CODE | \
56 SCU_HW_STRAP_LPC_RESET_PIN | \
57 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
58 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
59 SCU_HW_STRAP_SPI_WIDTH | \
60 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
61 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
62
63 /* TODO: Find the actual hardware value */
64 #define SUPERMICROX11_BMC_HW_STRAP1 ( \
65 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
66 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
67 SCU_AST2400_HW_STRAP_ACPI_DIS | \
68 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
69 SCU_HW_STRAP_VGA_CLASS_CODE | \
70 SCU_HW_STRAP_LPC_RESET_PIN | \
71 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
72 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
73 SCU_HW_STRAP_SPI_WIDTH | \
74 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
75 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
76
77 /* AST2500 evb hardware value: 0xF100C2E6 */
78 #define AST2500_EVB_HW_STRAP1 (( \
79 AST2500_HW_STRAP1_DEFAULTS | \
80 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
81 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
82 SCU_AST2500_HW_STRAP_UART_DEBUG | \
83 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
84 SCU_HW_STRAP_MAC1_RGMII | \
85 SCU_HW_STRAP_MAC0_RGMII) & \
86 ~SCU_HW_STRAP_2ND_BOOT_WDT)
87
88 /* Romulus hardware value: 0xF10AD206 */
89 #define ROMULUS_BMC_HW_STRAP1 ( \
90 AST2500_HW_STRAP1_DEFAULTS | \
91 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
92 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
93 SCU_AST2500_HW_STRAP_UART_DEBUG | \
94 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
95 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
96 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
97
98 /* Sonorapass hardware value: 0xF100D216 */
99 #define SONORAPASS_BMC_HW_STRAP1 ( \
100 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
101 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
102 SCU_AST2500_HW_STRAP_UART_DEBUG | \
103 SCU_AST2500_HW_STRAP_RESERVED28 | \
104 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
105 SCU_HW_STRAP_VGA_CLASS_CODE | \
106 SCU_HW_STRAP_LPC_RESET_PIN | \
107 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
108 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
109 SCU_HW_STRAP_VGA_BIOS_ROM | \
110 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
111 SCU_AST2500_HW_STRAP_RESERVED1)
112
113 /* Swift hardware value: 0xF11AD206 */
114 #define SWIFT_BMC_HW_STRAP1 ( \
115 AST2500_HW_STRAP1_DEFAULTS | \
116 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
117 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
118 SCU_AST2500_HW_STRAP_UART_DEBUG | \
119 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
120 SCU_H_PLL_BYPASS_EN | \
121 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
122 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
123
124 #define G220A_BMC_HW_STRAP1 ( \
125 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
126 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
127 SCU_AST2500_HW_STRAP_UART_DEBUG | \
128 SCU_AST2500_HW_STRAP_RESERVED28 | \
129 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
130 SCU_HW_STRAP_2ND_BOOT_WDT | \
131 SCU_HW_STRAP_VGA_CLASS_CODE | \
132 SCU_HW_STRAP_LPC_RESET_PIN | \
133 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
134 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
135 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \
136 SCU_AST2500_HW_STRAP_RESERVED1)
137
138 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
139 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
140
141 /* Quanta-Q71l hardware value */
142 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \
143 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
144 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
145 SCU_AST2400_HW_STRAP_ACPI_DIS | \
146 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \
147 SCU_HW_STRAP_VGA_CLASS_CODE | \
148 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \
149 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
150 SCU_HW_STRAP_SPI_WIDTH | \
151 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \
152 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
153
154 /* AST2600 evb hardware value */
155 #define AST2600_EVB_HW_STRAP1 0x000000C0
156 #define AST2600_EVB_HW_STRAP2 0x00000003
157
158 /* Tacoma hardware value */
159 #define TACOMA_BMC_HW_STRAP1 0x00000000
160 #define TACOMA_BMC_HW_STRAP2 0x00000040
161
162 /* Rainier hardware value: (QEMU prototype) */
163 #define RAINIER_BMC_HW_STRAP1 0x00000000
164 #define RAINIER_BMC_HW_STRAP2 0x00000000
165
166 /*
167 * The max ram region is for firmwares that scan the address space
168 * with load/store to guess how much RAM the SoC has.
169 */
170 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size)
171 {
172 return 0;
173 }
174
175 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value,
176 unsigned size)
177 {
178 /* Discard writes */
179 }
180
181 static const MemoryRegionOps max_ram_ops = {
182 .read = max_ram_read,
183 .write = max_ram_write,
184 .endianness = DEVICE_NATIVE_ENDIAN,
185 };
186
187 #define AST_SMP_MAILBOX_BASE 0x1e6e2180
188 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
189 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
190 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
191 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
192 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
193 #define AST_SMP_MBOX_GOSIGN 0xabbaab00
194
195 static void aspeed_write_smpboot(ARMCPU *cpu,
196 const struct arm_boot_info *info)
197 {
198 static const uint32_t poll_mailbox_ready[] = {
199 /*
200 * r2 = per-cpu go sign value
201 * r1 = AST_SMP_MBOX_FIELD_ENTRY
202 * r0 = AST_SMP_MBOX_FIELD_GOSIGN
203 */
204 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
205 0xe21000ff, /* ands r0, r0, #255 */
206 0xe59f201c, /* ldr r2, [pc, #28] */
207 0xe1822000, /* orr r2, r2, r0 */
208
209 0xe59f1018, /* ldr r1, [pc, #24] */
210 0xe59f0018, /* ldr r0, [pc, #24] */
211
212 0xe320f002, /* wfe */
213 0xe5904000, /* ldr r4, [r0] */
214 0xe1520004, /* cmp r2, r4 */
215 0x1afffffb, /* bne <wfe> */
216 0xe591f000, /* ldr pc, [r1] */
217 AST_SMP_MBOX_GOSIGN,
218 AST_SMP_MBOX_FIELD_ENTRY,
219 AST_SMP_MBOX_FIELD_GOSIGN,
220 };
221
222 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
223 sizeof(poll_mailbox_ready),
224 info->smp_loader_start);
225 }
226
227 static void aspeed_reset_secondary(ARMCPU *cpu,
228 const struct arm_boot_info *info)
229 {
230 AddressSpace *as = arm_boot_address_space(cpu, info);
231 CPUState *cs = CPU(cpu);
232
233 /* info->smp_bootreg_addr */
234 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
235 MEMTXATTRS_UNSPECIFIED, NULL);
236 cpu_set_pc(cs, info->smp_loader_start);
237 }
238
239 #define FIRMWARE_ADDR 0x0
240
241 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
242 Error **errp)
243 {
244 BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
245 uint8_t *storage;
246 int64_t size;
247
248 /* The block backend size should have already been 'validated' by
249 * the creation of the m25p80 object.
250 */
251 size = blk_getlength(blk);
252 if (size <= 0) {
253 error_setg(errp, "failed to get flash size");
254 return;
255 }
256
257 if (rom_size > size) {
258 rom_size = size;
259 }
260
261 storage = g_new0(uint8_t, rom_size);
262 if (blk_pread(blk, 0, storage, rom_size) < 0) {
263 error_setg(errp, "failed to read the initial flash content");
264 return;
265 }
266
267 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
268 g_free(storage);
269 }
270
271 static void aspeed_board_init_flashes(AspeedSMCState *s,
272 const char *flashtype)
273 {
274 int i ;
275
276 for (i = 0; i < s->num_cs; ++i) {
277 AspeedSMCFlash *fl = &s->flashes[i];
278 DriveInfo *dinfo = drive_get_next(IF_MTD);
279 qemu_irq cs_line;
280
281 fl->flash = qdev_new(flashtype);
282 if (dinfo) {
283 qdev_prop_set_drive(fl->flash, "drive",
284 blk_by_legacy_dinfo(dinfo));
285 }
286 qdev_realize_and_unref(fl->flash, BUS(s->spi), &error_fatal);
287
288 cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0);
289 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
290 }
291 }
292
293 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
294 {
295 DeviceState *card;
296
297 if (!dinfo) {
298 return;
299 }
300 card = qdev_new(TYPE_SD_CARD);
301 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
302 &error_fatal);
303 qdev_realize_and_unref(card,
304 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
305 &error_fatal);
306 }
307
308 static void aspeed_machine_init(MachineState *machine)
309 {
310 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
311 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
312 AspeedSoCClass *sc;
313 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
314 ram_addr_t max_ram_size;
315 int i;
316 NICInfo *nd = &nd_table[0];
317
318 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container",
319 4 * GiB);
320 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram);
321
322 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
323
324 sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
325
326 /*
327 * This will error out if isize is not supported by memory controller.
328 */
329 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
330 &error_fatal);
331
332 for (i = 0; i < sc->macs_num; i++) {
333 if ((amc->macs_mask & (1 << i)) && nd->used) {
334 qemu_check_nic_model(nd, TYPE_FTGMAC100);
335 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
336 nd++;
337 }
338 }
339
340 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
341 &error_abort);
342 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
343 &error_abort);
344 object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs,
345 &error_abort);
346 object_property_set_link(OBJECT(&bmc->soc), "dram",
347 OBJECT(machine->ram), &error_abort);
348 if (machine->kernel_filename) {
349 /*
350 * When booting with a -kernel command line there is no u-boot
351 * that runs to unlock the SCU. In this case set the default to
352 * be unlocked as the kernel expects
353 */
354 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
355 ASPEED_SCU_PROT_KEY, &error_abort);
356 }
357 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
358
359 memory_region_add_subregion(get_system_memory(),
360 sc->memmap[ASPEED_DEV_SDRAM],
361 &bmc->ram_container);
362
363 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
364 &error_abort);
365 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
366 "max_ram", max_ram_size - machine->ram_size);
367 memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram);
368
369 aspeed_board_init_flashes(&bmc->soc.fmc, bmc->fmc_model ?
370 bmc->fmc_model : amc->fmc_model);
371 aspeed_board_init_flashes(&bmc->soc.spi[0], bmc->spi_model ?
372 bmc->spi_model : amc->spi_model);
373
374 /* Install first FMC flash content as a boot rom. */
375 if (drive0) {
376 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
377 MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
378
379 /*
380 * create a ROM region using the default mapping window size of
381 * the flash module. The window size is 64MB for the AST2400
382 * SoC and 128MB for the AST2500 SoC, which is twice as big as
383 * needed by the flash modules of the Aspeed machines.
384 */
385 if (ASPEED_MACHINE(machine)->mmio_exec) {
386 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom",
387 &fl->mmio, 0, fl->size);
388 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
389 boot_rom);
390 } else {
391 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom",
392 fl->size, &error_abort);
393 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
394 boot_rom);
395 write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort);
396 }
397 }
398
399 if (machine->kernel_filename && sc->num_cpus > 1) {
400 /* With no u-boot we must set up a boot stub for the secondary CPU */
401 MemoryRegion *smpboot = g_new(MemoryRegion, 1);
402 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
403 0x80, &error_abort);
404 memory_region_add_subregion(get_system_memory(),
405 AST_SMP_MAILBOX_BASE, smpboot);
406
407 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
408 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
409 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
410 }
411
412 aspeed_board_binfo.ram_size = machine->ram_size;
413 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
414 aspeed_board_binfo.nb_cpus = sc->num_cpus;
415
416 if (amc->i2c_init) {
417 amc->i2c_init(bmc);
418 }
419
420 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
421 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD));
422 }
423
424 if (bmc->soc.emmc.num_slots) {
425 sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD));
426 }
427
428 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
429 }
430
431 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
432 {
433 AspeedSoCState *soc = &bmc->soc;
434 DeviceState *dev;
435 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
436
437 /* The palmetto platform expects a ds3231 RTC but a ds1338 is
438 * enough to provide basic RTC features. Alarms will be missing */
439 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
440
441 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
442 eeprom_buf);
443
444 /* add a TMP423 temperature sensor */
445 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
446 "tmp423", 0x4c));
447 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
448 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
449 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
450 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
451 }
452
453 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
454 {
455 AspeedSoCState *soc = &bmc->soc;
456
457 /*
458 * The quanta-q71l platform expects tmp75s which are compatible with
459 * tmp105s.
460 */
461 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
462 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
463 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
464
465 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
466 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
467 /* TODO: Add Memory Riser i2c mux and eeproms. */
468
469 /* TODO: i2c-2: pca9546@74 */
470 /* TODO: i2c-2: pca9548@77 */
471 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
472 /* TODO: i2c-7: Add pca9546@70 */
473 /* - i2c@0: pmbus@59 */
474 /* - i2c@1: pmbus@58 */
475 /* - i2c@2: pmbus@58 */
476 /* - i2c@3: pmbus@59 */
477 /* TODO: i2c-7: Add PDB FRU eeprom@52 */
478 /* TODO: i2c-8: Add BMC FRU eeprom@50 */
479 }
480
481 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
482 {
483 AspeedSoCState *soc = &bmc->soc;
484 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
485
486 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
487 eeprom_buf);
488
489 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
490 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
491 TYPE_TMP105, 0x4d);
492
493 /* The AST2500 EVB does not have an RTC. Let's pretend that one is
494 * plugged on the I2C bus header */
495 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
496 }
497
498 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
499 {
500 /* Start with some devices on our I2C busses */
501 ast2500_evb_i2c_init(bmc);
502 }
503
504 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
505 {
506 AspeedSoCState *soc = &bmc->soc;
507
508 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
509 * good enough */
510 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
511 }
512
513 static void swift_bmc_i2c_init(AspeedMachineState *bmc)
514 {
515 AspeedSoCState *soc = &bmc->soc;
516
517 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x60);
518
519 /* The swift board expects a TMP275 but a TMP105 is compatible */
520 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "tmp105", 0x48);
521 /* The swift board expects a pca9551 but a pca9552 is compatible */
522 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60);
523
524 /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */
525 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "ds1338", 0x32);
526 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
527
528 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
529 /* The swift board expects a pca9539 but a pca9552 is compatible */
530 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "pca9552", 0x74);
531
532 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
533 /* The swift board expects a pca9539 but a pca9552 is compatible */
534 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "pca9552",
535 0x74);
536
537 /* The swift board expects a TMP275 but a TMP105 is compatible */
538 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x48);
539 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x4a);
540 }
541
542 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
543 {
544 AspeedSoCState *soc = &bmc->soc;
545
546 /* bus 2 : */
547 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
548 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
549 /* bus 2 : pca9546 @ 0x73 */
550
551 /* bus 3 : pca9548 @ 0x70 */
552
553 /* bus 4 : */
554 uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
555 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
556 eeprom4_54);
557 /* PCA9539 @ 0x76, but PCA9552 is compatible */
558 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x76);
559 /* PCA9539 @ 0x77, but PCA9552 is compatible */
560 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x77);
561
562 /* bus 6 : */
563 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
564 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
565 /* bus 6 : pca9546 @ 0x73 */
566
567 /* bus 8 : */
568 uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
569 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
570 eeprom8_56);
571 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
572 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
573 /* bus 8 : adc128d818 @ 0x1d */
574 /* bus 8 : adc128d818 @ 0x1f */
575
576 /*
577 * bus 13 : pca9548 @ 0x71
578 * - channel 3:
579 * - tmm421 @ 0x4c
580 * - tmp421 @ 0x4e
581 * - tmp421 @ 0x4f
582 */
583
584 }
585
586 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
587 {
588 static const struct {
589 unsigned gpio_id;
590 LEDColor color;
591 const char *description;
592 bool gpio_polarity;
593 } pca1_leds[] = {
594 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW},
595 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
596 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
597 };
598 AspeedSoCState *soc = &bmc->soc;
599 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
600 DeviceState *dev;
601 LEDState *led;
602
603 /* Bus 3: TODO bmp280@77 */
604 /* Bus 3: TODO max31785@52 */
605 /* Bus 3: TODO dps310@76 */
606 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
607 qdev_prop_set_string(dev, "description", "pca1");
608 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
609 aspeed_i2c_get_bus(&soc->i2c, 3),
610 &error_fatal);
611
612 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
613 led = led_create_simple(OBJECT(bmc),
614 pca1_leds[i].gpio_polarity,
615 pca1_leds[i].color,
616 pca1_leds[i].description);
617 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
618 qdev_get_gpio_in(DEVICE(led), 0));
619 }
620 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
621 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
622
623 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
624 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
625 0x4a);
626
627 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
628 * good enough */
629 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
630
631 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
632 eeprom_buf);
633 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
634 qdev_prop_set_string(dev, "description", "pca0");
635 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
636 aspeed_i2c_get_bus(&soc->i2c, 11),
637 &error_fatal);
638 /* Bus 11: TODO ucd90160@64 */
639 }
640
641 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
642 {
643 AspeedSoCState *soc = &bmc->soc;
644 DeviceState *dev;
645
646 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
647 "emc1413", 0x4c));
648 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
649 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
650 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
651
652 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
653 "emc1413", 0x4c));
654 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
655 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
656 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
657
658 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
659 "emc1413", 0x4c));
660 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
661 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
662 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
663
664 static uint8_t eeprom_buf[2 * 1024] = {
665 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
666 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
667 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
668 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
669 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
670 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
671 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
672 };
673 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
674 eeprom_buf);
675 }
676
677 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
678 {
679 AspeedSoCState *soc = &bmc->soc;
680
681 /* The rainier expects a TMP275 but a TMP105 is compatible */
682 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
683 0x48);
684 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
685 0x49);
686 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
687 0x4a);
688
689 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
690 0x48);
691 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
692 0x49);
693
694 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
695 0x48);
696 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
697 0x4a);
698 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
699 0x4b);
700
701 /* Bus 7: TODO dps310@76 */
702 /* Bus 7: TODO max31785@52 */
703 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x61);
704 /* Bus 7: TODO si7021-a20@20 */
705 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
706 0x48);
707
708 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
709 0x48);
710 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
711 0x4a);
712 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
713 /* Bus 8: ucd90320@11 */
714 /* Bus 8: ucd90320@b */
715 /* Bus 8: ucd90320@c */
716
717 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
718 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
719
720 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
721 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
722
723 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
724 0x48);
725 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
726 0x49);
727 }
728
729 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
730 {
731 return ASPEED_MACHINE(obj)->mmio_exec;
732 }
733
734 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
735 {
736 ASPEED_MACHINE(obj)->mmio_exec = value;
737 }
738
739 static void aspeed_machine_instance_init(Object *obj)
740 {
741 ASPEED_MACHINE(obj)->mmio_exec = false;
742 }
743
744 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
745 {
746 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
747 return g_strdup(bmc->fmc_model);
748 }
749
750 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
751 {
752 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
753
754 g_free(bmc->fmc_model);
755 bmc->fmc_model = g_strdup(value);
756 }
757
758 static char *aspeed_get_spi_model(Object *obj, Error **errp)
759 {
760 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
761 return g_strdup(bmc->spi_model);
762 }
763
764 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
765 {
766 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
767
768 g_free(bmc->spi_model);
769 bmc->spi_model = g_strdup(value);
770 }
771
772 static void aspeed_machine_class_props_init(ObjectClass *oc)
773 {
774 object_class_property_add_bool(oc, "execute-in-place",
775 aspeed_get_mmio_exec,
776 aspeed_set_mmio_exec);
777 object_class_property_set_description(oc, "execute-in-place",
778 "boot directly from CE0 flash device");
779
780 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
781 aspeed_set_fmc_model);
782 object_class_property_set_description(oc, "fmc-model",
783 "Change the FMC Flash model");
784 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
785 aspeed_set_spi_model);
786 object_class_property_set_description(oc, "spi-model",
787 "Change the SPI Flash model");
788 }
789
790 static int aspeed_soc_num_cpus(const char *soc_name)
791 {
792 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
793 return sc->num_cpus;
794 }
795
796 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
797 {
798 MachineClass *mc = MACHINE_CLASS(oc);
799 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
800
801 mc->init = aspeed_machine_init;
802 mc->no_floppy = 1;
803 mc->no_cdrom = 1;
804 mc->no_parallel = 1;
805 mc->default_ram_id = "ram";
806 amc->macs_mask = ASPEED_MAC0_ON;
807
808 aspeed_machine_class_props_init(oc);
809 }
810
811 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
812 {
813 MachineClass *mc = MACHINE_CLASS(oc);
814 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
815
816 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
817 amc->soc_name = "ast2400-a1";
818 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
819 amc->fmc_model = "n25q256a";
820 amc->spi_model = "mx25l25635e";
821 amc->num_cs = 1;
822 amc->i2c_init = palmetto_bmc_i2c_init;
823 mc->default_ram_size = 256 * MiB;
824 mc->default_cpus = mc->min_cpus = mc->max_cpus =
825 aspeed_soc_num_cpus(amc->soc_name);
826 };
827
828 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
829 {
830 MachineClass *mc = MACHINE_CLASS(oc);
831 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
832
833 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)";
834 amc->soc_name = "ast2400-a1";
835 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
836 amc->fmc_model = "n25q256a";
837 amc->spi_model = "mx25l25635e";
838 amc->num_cs = 1;
839 amc->i2c_init = quanta_q71l_bmc_i2c_init;
840 mc->default_ram_size = 128 * MiB;
841 mc->default_cpus = mc->min_cpus = mc->max_cpus =
842 aspeed_soc_num_cpus(amc->soc_name);
843 }
844
845 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
846 void *data)
847 {
848 MachineClass *mc = MACHINE_CLASS(oc);
849 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
850
851 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
852 amc->soc_name = "ast2400-a1";
853 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
854 amc->fmc_model = "mx25l25635e";
855 amc->spi_model = "mx25l25635e";
856 amc->num_cs = 1;
857 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
858 amc->i2c_init = palmetto_bmc_i2c_init;
859 mc->default_ram_size = 256 * MiB;
860 }
861
862 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
863 {
864 MachineClass *mc = MACHINE_CLASS(oc);
865 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
866
867 mc->desc = "Aspeed AST2500 EVB (ARM1176)";
868 amc->soc_name = "ast2500-a1";
869 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
870 amc->fmc_model = "w25q256";
871 amc->spi_model = "mx25l25635e";
872 amc->num_cs = 1;
873 amc->i2c_init = ast2500_evb_i2c_init;
874 mc->default_ram_size = 512 * MiB;
875 mc->default_cpus = mc->min_cpus = mc->max_cpus =
876 aspeed_soc_num_cpus(amc->soc_name);
877 };
878
879 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
880 {
881 MachineClass *mc = MACHINE_CLASS(oc);
882 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
883
884 mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
885 amc->soc_name = "ast2500-a1";
886 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
887 amc->fmc_model = "n25q256a";
888 amc->spi_model = "mx66l1g45g";
889 amc->num_cs = 2;
890 amc->i2c_init = romulus_bmc_i2c_init;
891 mc->default_ram_size = 512 * MiB;
892 mc->default_cpus = mc->min_cpus = mc->max_cpus =
893 aspeed_soc_num_cpus(amc->soc_name);
894 };
895
896 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
897 {
898 MachineClass *mc = MACHINE_CLASS(oc);
899 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
900
901 mc->desc = "OCP SonoraPass BMC (ARM1176)";
902 amc->soc_name = "ast2500-a1";
903 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
904 amc->fmc_model = "mx66l1g45g";
905 amc->spi_model = "mx66l1g45g";
906 amc->num_cs = 2;
907 amc->i2c_init = sonorapass_bmc_i2c_init;
908 mc->default_ram_size = 512 * MiB;
909 mc->default_cpus = mc->min_cpus = mc->max_cpus =
910 aspeed_soc_num_cpus(amc->soc_name);
911 };
912
913 static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data)
914 {
915 MachineClass *mc = MACHINE_CLASS(oc);
916 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
917
918 mc->desc = "OpenPOWER Swift BMC (ARM1176)";
919 amc->soc_name = "ast2500-a1";
920 amc->hw_strap1 = SWIFT_BMC_HW_STRAP1;
921 amc->fmc_model = "mx66l1g45g";
922 amc->spi_model = "mx66l1g45g";
923 amc->num_cs = 2;
924 amc->i2c_init = swift_bmc_i2c_init;
925 mc->default_ram_size = 512 * MiB;
926 mc->default_cpus = mc->min_cpus = mc->max_cpus =
927 aspeed_soc_num_cpus(amc->soc_name);
928
929 mc->deprecation_reason = "redundant system. Please use a similar "
930 "OpenPOWER BMC, Witherspoon or Romulus.";
931 };
932
933 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
934 {
935 MachineClass *mc = MACHINE_CLASS(oc);
936 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
937
938 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
939 amc->soc_name = "ast2500-a1";
940 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
941 amc->fmc_model = "mx25l25635e";
942 amc->spi_model = "mx66l1g45g";
943 amc->num_cs = 2;
944 amc->i2c_init = witherspoon_bmc_i2c_init;
945 mc->default_ram_size = 512 * MiB;
946 mc->default_cpus = mc->min_cpus = mc->max_cpus =
947 aspeed_soc_num_cpus(amc->soc_name);
948 };
949
950 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
951 {
952 MachineClass *mc = MACHINE_CLASS(oc);
953 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
954
955 mc->desc = "Aspeed AST2600 EVB (Cortex A7)";
956 amc->soc_name = "ast2600-a1";
957 amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
958 amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
959 amc->fmc_model = "w25q512jv";
960 amc->spi_model = "mx66u51235f";
961 amc->num_cs = 1;
962 amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON | ASPEED_MAC3_ON;
963 amc->i2c_init = ast2600_evb_i2c_init;
964 mc->default_ram_size = 1 * GiB;
965 mc->default_cpus = mc->min_cpus = mc->max_cpus =
966 aspeed_soc_num_cpus(amc->soc_name);
967 };
968
969 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
970 {
971 MachineClass *mc = MACHINE_CLASS(oc);
972 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
973
974 mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)";
975 amc->soc_name = "ast2600-a1";
976 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
977 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
978 amc->fmc_model = "mx66l1g45g";
979 amc->spi_model = "mx66l1g45g";
980 amc->num_cs = 2;
981 amc->macs_mask = ASPEED_MAC2_ON;
982 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
983 mc->default_ram_size = 1 * GiB;
984 mc->default_cpus = mc->min_cpus = mc->max_cpus =
985 aspeed_soc_num_cpus(amc->soc_name);
986 };
987
988 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
989 {
990 MachineClass *mc = MACHINE_CLASS(oc);
991 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
992
993 mc->desc = "Bytedance G220A BMC (ARM1176)";
994 amc->soc_name = "ast2500-a1";
995 amc->hw_strap1 = G220A_BMC_HW_STRAP1;
996 amc->fmc_model = "n25q512a";
997 amc->spi_model = "mx25l25635e";
998 amc->num_cs = 2;
999 amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON;
1000 amc->i2c_init = g220a_bmc_i2c_init;
1001 mc->default_ram_size = 1024 * MiB;
1002 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1003 aspeed_soc_num_cpus(amc->soc_name);
1004 };
1005
1006 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
1007 {
1008 MachineClass *mc = MACHINE_CLASS(oc);
1009 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1010
1011 mc->desc = "IBM Rainier BMC (Cortex A7)";
1012 amc->soc_name = "ast2600-a1";
1013 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1014 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1015 amc->fmc_model = "mx66l1g45g";
1016 amc->spi_model = "mx66l1g45g";
1017 amc->num_cs = 2;
1018 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1019 amc->i2c_init = rainier_bmc_i2c_init;
1020 mc->default_ram_size = 1 * GiB;
1021 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1022 aspeed_soc_num_cpus(amc->soc_name);
1023 };
1024
1025 static const TypeInfo aspeed_machine_types[] = {
1026 {
1027 .name = MACHINE_TYPE_NAME("palmetto-bmc"),
1028 .parent = TYPE_ASPEED_MACHINE,
1029 .class_init = aspeed_machine_palmetto_class_init,
1030 }, {
1031 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
1032 .parent = TYPE_ASPEED_MACHINE,
1033 .class_init = aspeed_machine_supermicrox11_bmc_class_init,
1034 }, {
1035 .name = MACHINE_TYPE_NAME("ast2500-evb"),
1036 .parent = TYPE_ASPEED_MACHINE,
1037 .class_init = aspeed_machine_ast2500_evb_class_init,
1038 }, {
1039 .name = MACHINE_TYPE_NAME("romulus-bmc"),
1040 .parent = TYPE_ASPEED_MACHINE,
1041 .class_init = aspeed_machine_romulus_class_init,
1042 }, {
1043 .name = MACHINE_TYPE_NAME("swift-bmc"),
1044 .parent = TYPE_ASPEED_MACHINE,
1045 .class_init = aspeed_machine_swift_class_init,
1046 }, {
1047 .name = MACHINE_TYPE_NAME("sonorapass-bmc"),
1048 .parent = TYPE_ASPEED_MACHINE,
1049 .class_init = aspeed_machine_sonorapass_class_init,
1050 }, {
1051 .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
1052 .parent = TYPE_ASPEED_MACHINE,
1053 .class_init = aspeed_machine_witherspoon_class_init,
1054 }, {
1055 .name = MACHINE_TYPE_NAME("ast2600-evb"),
1056 .parent = TYPE_ASPEED_MACHINE,
1057 .class_init = aspeed_machine_ast2600_evb_class_init,
1058 }, {
1059 .name = MACHINE_TYPE_NAME("tacoma-bmc"),
1060 .parent = TYPE_ASPEED_MACHINE,
1061 .class_init = aspeed_machine_tacoma_class_init,
1062 }, {
1063 .name = MACHINE_TYPE_NAME("g220a-bmc"),
1064 .parent = TYPE_ASPEED_MACHINE,
1065 .class_init = aspeed_machine_g220a_class_init,
1066 }, {
1067 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
1068 .parent = TYPE_ASPEED_MACHINE,
1069 .class_init = aspeed_machine_quanta_q71l_class_init,
1070 }, {
1071 .name = MACHINE_TYPE_NAME("rainier-bmc"),
1072 .parent = TYPE_ASPEED_MACHINE,
1073 .class_init = aspeed_machine_rainier_class_init,
1074 }, {
1075 .name = TYPE_ASPEED_MACHINE,
1076 .parent = TYPE_MACHINE,
1077 .instance_size = sizeof(AspeedMachineState),
1078 .instance_init = aspeed_machine_instance_init,
1079 .class_size = sizeof(AspeedMachineClass),
1080 .class_init = aspeed_machine_class_init,
1081 .abstract = true,
1082 }
1083 };
1084
1085 DEFINE_TYPES(aspeed_machine_types)
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