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[mirror_qemu.git] / hw / arm / aspeed.c
1 /*
2 * OpenPOWER Palmetto BMC
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "hw/arm/boot.h"
15 #include "hw/arm/aspeed.h"
16 #include "hw/arm/aspeed_soc.h"
17 #include "hw/arm/aspeed_eeprom.h"
18 #include "hw/i2c/i2c_mux_pca954x.h"
19 #include "hw/i2c/smbus_eeprom.h"
20 #include "hw/misc/pca9552.h"
21 #include "hw/nvram/eeprom_at24c.h"
22 #include "hw/sensor/tmp105.h"
23 #include "hw/misc/led.h"
24 #include "hw/qdev-properties.h"
25 #include "sysemu/block-backend.h"
26 #include "sysemu/reset.h"
27 #include "hw/loader.h"
28 #include "qemu/error-report.h"
29 #include "qemu/units.h"
30 #include "hw/qdev-clock.h"
31 #include "sysemu/sysemu.h"
32
33 static struct arm_boot_info aspeed_board_binfo = {
34 .board_id = -1, /* device-tree-only board */
35 };
36
37 struct AspeedMachineState {
38 /* Private */
39 MachineState parent_obj;
40 /* Public */
41
42 AspeedSoCState soc;
43 bool mmio_exec;
44 char *fmc_model;
45 char *spi_model;
46 };
47
48 /* Palmetto hardware value: 0x120CE416 */
49 #define PALMETTO_BMC_HW_STRAP1 ( \
50 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
51 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
52 SCU_AST2400_HW_STRAP_ACPI_DIS | \
53 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
54 SCU_HW_STRAP_VGA_CLASS_CODE | \
55 SCU_HW_STRAP_LPC_RESET_PIN | \
56 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
57 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
58 SCU_HW_STRAP_SPI_WIDTH | \
59 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
60 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
61
62 /* TODO: Find the actual hardware value */
63 #define SUPERMICROX11_BMC_HW_STRAP1 ( \
64 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
65 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
66 SCU_AST2400_HW_STRAP_ACPI_DIS | \
67 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
68 SCU_HW_STRAP_VGA_CLASS_CODE | \
69 SCU_HW_STRAP_LPC_RESET_PIN | \
70 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
71 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
72 SCU_HW_STRAP_SPI_WIDTH | \
73 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
74 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
75
76 /* TODO: Find the actual hardware value */
77 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \
78 AST2500_HW_STRAP1_DEFAULTS | \
79 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
80 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
81 SCU_AST2500_HW_STRAP_UART_DEBUG | \
82 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
83 SCU_HW_STRAP_SPI_WIDTH | \
84 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
85
86 /* AST2500 evb hardware value: 0xF100C2E6 */
87 #define AST2500_EVB_HW_STRAP1 (( \
88 AST2500_HW_STRAP1_DEFAULTS | \
89 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
90 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
91 SCU_AST2500_HW_STRAP_UART_DEBUG | \
92 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
93 SCU_HW_STRAP_MAC1_RGMII | \
94 SCU_HW_STRAP_MAC0_RGMII) & \
95 ~SCU_HW_STRAP_2ND_BOOT_WDT)
96
97 /* Romulus hardware value: 0xF10AD206 */
98 #define ROMULUS_BMC_HW_STRAP1 ( \
99 AST2500_HW_STRAP1_DEFAULTS | \
100 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
101 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
102 SCU_AST2500_HW_STRAP_UART_DEBUG | \
103 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
104 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
105 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
106
107 /* Sonorapass hardware value: 0xF100D216 */
108 #define SONORAPASS_BMC_HW_STRAP1 ( \
109 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
110 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
111 SCU_AST2500_HW_STRAP_UART_DEBUG | \
112 SCU_AST2500_HW_STRAP_RESERVED28 | \
113 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
114 SCU_HW_STRAP_VGA_CLASS_CODE | \
115 SCU_HW_STRAP_LPC_RESET_PIN | \
116 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
117 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
118 SCU_HW_STRAP_VGA_BIOS_ROM | \
119 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
120 SCU_AST2500_HW_STRAP_RESERVED1)
121
122 #define G220A_BMC_HW_STRAP1 ( \
123 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
124 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
125 SCU_AST2500_HW_STRAP_UART_DEBUG | \
126 SCU_AST2500_HW_STRAP_RESERVED28 | \
127 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
128 SCU_HW_STRAP_2ND_BOOT_WDT | \
129 SCU_HW_STRAP_VGA_CLASS_CODE | \
130 SCU_HW_STRAP_LPC_RESET_PIN | \
131 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
132 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
133 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \
134 SCU_AST2500_HW_STRAP_RESERVED1)
135
136 /* FP5280G2 hardware value: 0XF100D286 */
137 #define FP5280G2_BMC_HW_STRAP1 ( \
138 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
139 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
140 SCU_AST2500_HW_STRAP_UART_DEBUG | \
141 SCU_AST2500_HW_STRAP_RESERVED28 | \
142 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
143 SCU_HW_STRAP_VGA_CLASS_CODE | \
144 SCU_HW_STRAP_LPC_RESET_PIN | \
145 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
146 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
147 SCU_HW_STRAP_MAC1_RGMII | \
148 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
149 SCU_AST2500_HW_STRAP_RESERVED1)
150
151 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
152 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
153
154 /* Quanta-Q71l hardware value */
155 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \
156 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
157 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
158 SCU_AST2400_HW_STRAP_ACPI_DIS | \
159 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \
160 SCU_HW_STRAP_VGA_CLASS_CODE | \
161 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \
162 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
163 SCU_HW_STRAP_SPI_WIDTH | \
164 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \
165 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
166
167 /* AST2600 evb hardware value */
168 #define AST2600_EVB_HW_STRAP1 0x000000C0
169 #define AST2600_EVB_HW_STRAP2 0x00000003
170
171 /* Tacoma hardware value */
172 #define TACOMA_BMC_HW_STRAP1 0x00000000
173 #define TACOMA_BMC_HW_STRAP2 0x00000040
174
175 /* Rainier hardware value: (QEMU prototype) */
176 #define RAINIER_BMC_HW_STRAP1 0x00422016
177 #define RAINIER_BMC_HW_STRAP2 0x80000848
178
179 /* Fuji hardware value */
180 #define FUJI_BMC_HW_STRAP1 0x00000000
181 #define FUJI_BMC_HW_STRAP2 0x00000000
182
183 /* Bletchley hardware value */
184 /* TODO: Leave same as EVB for now. */
185 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
186 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
187
188 /* Qualcomm DC-SCM hardware value */
189 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000
190 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041
191
192 #define AST_SMP_MAILBOX_BASE 0x1e6e2180
193 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
194 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
195 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
196 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
197 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
198 #define AST_SMP_MBOX_GOSIGN 0xabbaab00
199
200 static void aspeed_write_smpboot(ARMCPU *cpu,
201 const struct arm_boot_info *info)
202 {
203 static const uint32_t poll_mailbox_ready[] = {
204 /*
205 * r2 = per-cpu go sign value
206 * r1 = AST_SMP_MBOX_FIELD_ENTRY
207 * r0 = AST_SMP_MBOX_FIELD_GOSIGN
208 */
209 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
210 0xe21000ff, /* ands r0, r0, #255 */
211 0xe59f201c, /* ldr r2, [pc, #28] */
212 0xe1822000, /* orr r2, r2, r0 */
213
214 0xe59f1018, /* ldr r1, [pc, #24] */
215 0xe59f0018, /* ldr r0, [pc, #24] */
216
217 0xe320f002, /* wfe */
218 0xe5904000, /* ldr r4, [r0] */
219 0xe1520004, /* cmp r2, r4 */
220 0x1afffffb, /* bne <wfe> */
221 0xe591f000, /* ldr pc, [r1] */
222 AST_SMP_MBOX_GOSIGN,
223 AST_SMP_MBOX_FIELD_ENTRY,
224 AST_SMP_MBOX_FIELD_GOSIGN,
225 };
226
227 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
228 sizeof(poll_mailbox_ready),
229 info->smp_loader_start);
230 }
231
232 static void aspeed_reset_secondary(ARMCPU *cpu,
233 const struct arm_boot_info *info)
234 {
235 AddressSpace *as = arm_boot_address_space(cpu, info);
236 CPUState *cs = CPU(cpu);
237
238 /* info->smp_bootreg_addr */
239 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
240 MEMTXATTRS_UNSPECIFIED, NULL);
241 cpu_set_pc(cs, info->smp_loader_start);
242 }
243
244 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
245 Error **errp)
246 {
247 g_autofree void *storage = NULL;
248 int64_t size;
249
250 /* The block backend size should have already been 'validated' by
251 * the creation of the m25p80 object.
252 */
253 size = blk_getlength(blk);
254 if (size <= 0) {
255 error_setg(errp, "failed to get flash size");
256 return;
257 }
258
259 if (rom_size > size) {
260 rom_size = size;
261 }
262
263 storage = g_malloc0(rom_size);
264 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
265 error_setg(errp, "failed to read the initial flash content");
266 return;
267 }
268
269 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
270 }
271
272 /*
273 * Create a ROM and copy the flash contents at the expected address
274 * (0x0). Boots faster than execute-in-place.
275 */
276 static void aspeed_install_boot_rom(AspeedSoCState *soc, BlockBackend *blk,
277 uint64_t rom_size)
278 {
279 MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
280
281 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", rom_size,
282 &error_abort);
283 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
284 boot_rom, 1);
285 write_boot_rom(blk, ASPEED_SOC_SPI_BOOT_ADDR, rom_size, &error_abort);
286 }
287
288 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
289 unsigned int count, int unit0)
290 {
291 int i;
292
293 if (!flashtype) {
294 return;
295 }
296
297 for (i = 0; i < count; ++i) {
298 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
299 qemu_irq cs_line;
300 DeviceState *dev;
301
302 dev = qdev_new(flashtype);
303 if (dinfo) {
304 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
305 }
306 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
307
308 cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
309 qdev_connect_gpio_out_named(DEVICE(s), "cs", i, cs_line);
310 }
311 }
312
313 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
314 {
315 DeviceState *card;
316
317 if (!dinfo) {
318 return;
319 }
320 card = qdev_new(TYPE_SD_CARD);
321 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
322 &error_fatal);
323 qdev_realize_and_unref(card,
324 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
325 &error_fatal);
326 }
327
328 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
329 {
330 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
331 AspeedSoCState *s = &bmc->soc;
332 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
333
334 aspeed_soc_uart_set_chr(s, amc->uart_default, serial_hd(0));
335 for (int i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
336 if (uart == amc->uart_default) {
337 continue;
338 }
339 aspeed_soc_uart_set_chr(s, uart, serial_hd(i));
340 }
341 }
342
343 static void aspeed_machine_init(MachineState *machine)
344 {
345 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
346 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
347 AspeedSoCClass *sc;
348 int i;
349 NICInfo *nd = &nd_table[0];
350
351 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
352
353 sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
354
355 /*
356 * This will error out if the RAM size is not supported by the
357 * memory controller of the SoC.
358 */
359 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
360 &error_fatal);
361
362 for (i = 0; i < sc->macs_num; i++) {
363 if ((amc->macs_mask & (1 << i)) && nd->used) {
364 qemu_check_nic_model(nd, TYPE_FTGMAC100);
365 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
366 nd++;
367 }
368 }
369
370 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
371 &error_abort);
372 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
373 &error_abort);
374 object_property_set_link(OBJECT(&bmc->soc), "memory",
375 OBJECT(get_system_memory()), &error_abort);
376 object_property_set_link(OBJECT(&bmc->soc), "dram",
377 OBJECT(machine->ram), &error_abort);
378 if (machine->kernel_filename) {
379 /*
380 * When booting with a -kernel command line there is no u-boot
381 * that runs to unlock the SCU. In this case set the default to
382 * be unlocked as the kernel expects
383 */
384 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
385 ASPEED_SCU_PROT_KEY, &error_abort);
386 }
387 connect_serial_hds_to_uarts(bmc);
388 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
389
390 aspeed_board_init_flashes(&bmc->soc.fmc,
391 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
392 amc->num_cs, 0);
393 aspeed_board_init_flashes(&bmc->soc.spi[0],
394 bmc->spi_model ? bmc->spi_model : amc->spi_model,
395 1, amc->num_cs);
396
397 if (machine->kernel_filename && sc->num_cpus > 1) {
398 /* With no u-boot we must set up a boot stub for the secondary CPU */
399 MemoryRegion *smpboot = g_new(MemoryRegion, 1);
400 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
401 0x80, &error_abort);
402 memory_region_add_subregion(get_system_memory(),
403 AST_SMP_MAILBOX_BASE, smpboot);
404
405 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
406 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
407 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
408 }
409
410 aspeed_board_binfo.ram_size = machine->ram_size;
411 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
412
413 if (amc->i2c_init) {
414 amc->i2c_init(bmc);
415 }
416
417 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
418 sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
419 drive_get(IF_SD, 0, i));
420 }
421
422 if (bmc->soc.emmc.num_slots) {
423 sdhci_attach_drive(&bmc->soc.emmc.slots[0],
424 drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
425 }
426
427 if (!bmc->mmio_exec) {
428 DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0);
429
430 if (mtd0) {
431 uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot);
432 aspeed_install_boot_rom(&bmc->soc, blk_by_legacy_dinfo(mtd0),
433 rom_size);
434 }
435 }
436
437 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
438 }
439
440 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
441 {
442 AspeedSoCState *soc = &bmc->soc;
443 DeviceState *dev;
444 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
445
446 /* The palmetto platform expects a ds3231 RTC but a ds1338 is
447 * enough to provide basic RTC features. Alarms will be missing */
448 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
449
450 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
451 eeprom_buf);
452
453 /* add a TMP423 temperature sensor */
454 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
455 "tmp423", 0x4c));
456 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
457 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
458 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
459 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
460 }
461
462 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
463 {
464 AspeedSoCState *soc = &bmc->soc;
465
466 /*
467 * The quanta-q71l platform expects tmp75s which are compatible with
468 * tmp105s.
469 */
470 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
471 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
472 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
473
474 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
475 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
476 /* TODO: Add Memory Riser i2c mux and eeproms. */
477
478 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
479 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
480
481 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
482
483 /* i2c-7 */
484 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
485 /* - i2c@0: pmbus@59 */
486 /* - i2c@1: pmbus@58 */
487 /* - i2c@2: pmbus@58 */
488 /* - i2c@3: pmbus@59 */
489
490 /* TODO: i2c-7: Add PDB FRU eeprom@52 */
491 /* TODO: i2c-8: Add BMC FRU eeprom@50 */
492 }
493
494 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
495 {
496 AspeedSoCState *soc = &bmc->soc;
497 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
498
499 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
500 eeprom_buf);
501
502 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
503 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
504 TYPE_TMP105, 0x4d);
505 }
506
507 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
508 {
509 AspeedSoCState *soc = &bmc->soc;
510 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
511
512 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
513 eeprom_buf);
514
515 /* LM75 is compatible with TMP105 driver */
516 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
517 TYPE_TMP105, 0x4d);
518 }
519
520 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
521 {
522 AspeedSoCState *soc = &bmc->soc;
523
524 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
525 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
526 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len);
527 /* TMP421 */
528 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f);
529 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e);
530 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f);
531
532 }
533
534 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
535 {
536 AspeedSoCState *soc = &bmc->soc;
537
538 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
539 * good enough */
540 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
541 }
542
543 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
544 {
545 AspeedSoCState *soc = &bmc->soc;
546
547 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
548 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
549 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len);
550 /* TMP421 */
551 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f);
552 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f);
553 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e);
554 }
555
556 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
557 {
558 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
559 TYPE_PCA9552, addr);
560 }
561
562 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
563 {
564 AspeedSoCState *soc = &bmc->soc;
565
566 /* bus 2 : */
567 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
568 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
569 /* bus 2 : pca9546 @ 0x73 */
570
571 /* bus 3 : pca9548 @ 0x70 */
572
573 /* bus 4 : */
574 uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
575 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
576 eeprom4_54);
577 /* PCA9539 @ 0x76, but PCA9552 is compatible */
578 create_pca9552(soc, 4, 0x76);
579 /* PCA9539 @ 0x77, but PCA9552 is compatible */
580 create_pca9552(soc, 4, 0x77);
581
582 /* bus 6 : */
583 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
584 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
585 /* bus 6 : pca9546 @ 0x73 */
586
587 /* bus 8 : */
588 uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
589 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
590 eeprom8_56);
591 create_pca9552(soc, 8, 0x60);
592 create_pca9552(soc, 8, 0x61);
593 /* bus 8 : adc128d818 @ 0x1d */
594 /* bus 8 : adc128d818 @ 0x1f */
595
596 /*
597 * bus 13 : pca9548 @ 0x71
598 * - channel 3:
599 * - tmm421 @ 0x4c
600 * - tmp421 @ 0x4e
601 * - tmp421 @ 0x4f
602 */
603
604 }
605
606 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
607 {
608 static const struct {
609 unsigned gpio_id;
610 LEDColor color;
611 const char *description;
612 bool gpio_polarity;
613 } pca1_leds[] = {
614 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW},
615 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
616 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
617 };
618 AspeedSoCState *soc = &bmc->soc;
619 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
620 DeviceState *dev;
621 LEDState *led;
622
623 /* Bus 3: TODO bmp280@77 */
624 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
625 qdev_prop_set_string(dev, "description", "pca1");
626 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
627 aspeed_i2c_get_bus(&soc->i2c, 3),
628 &error_fatal);
629
630 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
631 led = led_create_simple(OBJECT(bmc),
632 pca1_leds[i].gpio_polarity,
633 pca1_leds[i].color,
634 pca1_leds[i].description);
635 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
636 qdev_get_gpio_in(DEVICE(led), 0));
637 }
638 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
639 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52);
640 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
641 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
642
643 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
644 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
645 0x4a);
646
647 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
648 * good enough */
649 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
650
651 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
652 eeprom_buf);
653 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
654 qdev_prop_set_string(dev, "description", "pca0");
655 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
656 aspeed_i2c_get_bus(&soc->i2c, 11),
657 &error_fatal);
658 /* Bus 11: TODO ucd90160@64 */
659 }
660
661 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
662 {
663 AspeedSoCState *soc = &bmc->soc;
664 DeviceState *dev;
665
666 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
667 "emc1413", 0x4c));
668 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
669 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
670 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
671
672 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
673 "emc1413", 0x4c));
674 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
675 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
676 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
677
678 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
679 "emc1413", 0x4c));
680 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
681 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
682 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
683
684 static uint8_t eeprom_buf[2 * 1024] = {
685 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
686 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
687 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
688 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
689 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
690 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
691 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
692 };
693 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
694 eeprom_buf);
695 }
696
697 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
698 {
699 AspeedSoCState *soc = &bmc->soc;
700 I2CSlave *i2c_mux;
701
702 /* The at24c256 */
703 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
704
705 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
706 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
707 0x48);
708 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
709 0x49);
710
711 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
712 "pca9546", 0x70);
713 /* It expects a TMP112 but a TMP105 is compatible */
714 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
715 0x4a);
716
717 /* It expects a ds3232 but a ds1338 is good enough */
718 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
719
720 /* It expects a pca9555 but a pca9552 is compatible */
721 create_pca9552(soc, 8, 0x30);
722 }
723
724 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
725 {
726 AspeedSoCState *soc = &bmc->soc;
727 I2CSlave *i2c_mux;
728
729 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
730
731 create_pca9552(soc, 3, 0x61);
732
733 /* The rainier expects a TMP275 but a TMP105 is compatible */
734 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
735 0x48);
736 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
737 0x49);
738 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
739 0x4a);
740 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
741 "pca9546", 0x70);
742 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
743 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
744 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
745 create_pca9552(soc, 4, 0x60);
746
747 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
748 0x48);
749 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
750 0x49);
751 create_pca9552(soc, 5, 0x60);
752 create_pca9552(soc, 5, 0x61);
753 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
754 "pca9546", 0x70);
755 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
756 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
757
758 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
759 0x48);
760 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
761 0x4a);
762 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
763 0x4b);
764 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
765 "pca9546", 0x70);
766 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
767 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
768 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
769 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
770
771 create_pca9552(soc, 7, 0x30);
772 create_pca9552(soc, 7, 0x31);
773 create_pca9552(soc, 7, 0x32);
774 create_pca9552(soc, 7, 0x33);
775 create_pca9552(soc, 7, 0x60);
776 create_pca9552(soc, 7, 0x61);
777 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
778 /* Bus 7: TODO si7021-a20@20 */
779 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
780 0x48);
781 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
782 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
783 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
784
785 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
786 0x48);
787 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
788 0x4a);
789 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
790 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
791 create_pca9552(soc, 8, 0x60);
792 create_pca9552(soc, 8, 0x61);
793 /* Bus 8: ucd90320@11 */
794 /* Bus 8: ucd90320@b */
795 /* Bus 8: ucd90320@c */
796
797 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
798 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
799 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
800
801 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
802 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
803 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
804
805 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
806 0x48);
807 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
808 0x49);
809 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
810 "pca9546", 0x70);
811 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
812 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
813 create_pca9552(soc, 11, 0x60);
814
815
816 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
817 create_pca9552(soc, 13, 0x60);
818
819 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
820 create_pca9552(soc, 14, 0x60);
821
822 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
823 create_pca9552(soc, 15, 0x60);
824 }
825
826 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
827 I2CBus **channels)
828 {
829 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
830 for (int i = 0; i < 8; i++) {
831 channels[i] = pca954x_i2c_get_bus(mux, i);
832 }
833 }
834
835 #define TYPE_LM75 TYPE_TMP105
836 #define TYPE_TMP75 TYPE_TMP105
837 #define TYPE_TMP422 "tmp422"
838
839 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
840 {
841 AspeedSoCState *soc = &bmc->soc;
842 I2CBus *i2c[144] = {};
843
844 for (int i = 0; i < 16; i++) {
845 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
846 }
847 I2CBus *i2c180 = i2c[2];
848 I2CBus *i2c480 = i2c[8];
849 I2CBus *i2c600 = i2c[11];
850
851 get_pca9548_channels(i2c180, 0x70, &i2c[16]);
852 get_pca9548_channels(i2c480, 0x70, &i2c[24]);
853 /* NOTE: The device tree skips [32, 40) in the alias numbering */
854 get_pca9548_channels(i2c600, 0x77, &i2c[40]);
855 get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
856 get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
857 get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
858 get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
859 for (int i = 0; i < 8; i++) {
860 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
861 }
862
863 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
864 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
865
866 /*
867 * EEPROM 24c64 size is 64Kbits or 8 Kbytes
868 * 24c02 size is 2Kbits or 256 bytes
869 */
870 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB);
871 at24c_eeprom_init(i2c[20], 0x50, 256);
872 at24c_eeprom_init(i2c[22], 0x52, 256);
873
874 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
875 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
876 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
877 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
878
879 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB);
880 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
881
882 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
883 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB);
884 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
885 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
886
887 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
888 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
889
890 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB);
891 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
892 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
893 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB);
894 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB);
895 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB);
896 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB);
897
898 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB);
899 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
900 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
901 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB);
902 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB);
903 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB);
904 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB);
905 at24c_eeprom_init(i2c[28], 0x50, 256);
906
907 for (int i = 0; i < 8; i++) {
908 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
909 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
910 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
911 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
912 }
913 }
914
915 #define TYPE_TMP421 "tmp421"
916
917 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
918 {
919 AspeedSoCState *soc = &bmc->soc;
920 I2CBus *i2c[13] = {};
921 for (int i = 0; i < 13; i++) {
922 if ((i == 8) || (i == 11)) {
923 continue;
924 }
925 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
926 }
927
928 /* Bus 0 - 5 all have the same config. */
929 for (int i = 0; i < 6; i++) {
930 /* Missing model: ti,ina230 @ 0x45 */
931 /* Missing model: mps,mp5023 @ 0x40 */
932 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f);
933 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */
934 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76);
935 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67);
936 /* Missing model: fsc,fusb302 @ 0x22 */
937 }
938
939 /* Bus 6 */
940 at24c_eeprom_init(i2c[6], 0x56, 65536);
941 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */
942 i2c_slave_create_simple(i2c[6], "ds1338", 0x51);
943
944
945 /* Bus 7 */
946 at24c_eeprom_init(i2c[7], 0x54, 65536);
947
948 /* Bus 9 */
949 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f);
950
951 /* Bus 10 */
952 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f);
953 /* Missing model: ti,hdc1080 @ 0x40 */
954 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67);
955
956 /* Bus 12 */
957 /* Missing model: adi,adm1278 @ 0x11 */
958 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c);
959 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d);
960 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
961 }
962
963 static void fby35_i2c_init(AspeedMachineState *bmc)
964 {
965 AspeedSoCState *soc = &bmc->soc;
966 I2CBus *i2c[16];
967
968 for (int i = 0; i < 16; i++) {
969 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
970 }
971
972 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f);
973 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f);
974 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */
975 i2c_slave_create_simple(i2c[11], "adm1272", 0x44);
976 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
977 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
978
979 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
980 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
981 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid,
982 fby35_nic_fruid_len);
983 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid,
984 fby35_bb_fruid_len);
985 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid,
986 fby35_bmc_fruid_len);
987
988 /*
989 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
990 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on
991 * each.
992 */
993 }
994
995 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
996 {
997 AspeedSoCState *soc = &bmc->soc;
998
999 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
1000 }
1001
1002 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
1003 {
1004 AspeedSoCState *soc = &bmc->soc;
1005 I2CSlave *therm_mux, *cpuvr_mux;
1006
1007 /* Create the generic DC-SCM hardware */
1008 qcom_dc_scm_bmc_i2c_init(bmc);
1009
1010 /* Now create the Firework specific hardware */
1011
1012 /* I2C7 CPUVR MUX */
1013 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
1014 "pca9546", 0x70);
1015 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72);
1016 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72);
1017 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72);
1018 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72);
1019
1020 /* I2C8 Thermal Diodes*/
1021 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
1022 "pca9548", 0x70);
1023 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C);
1024 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C);
1025 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48);
1026 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48);
1027 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48);
1028
1029 /* I2C9 Fan Controller (MAX31785) */
1030 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52);
1031 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54);
1032 }
1033
1034 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
1035 {
1036 return ASPEED_MACHINE(obj)->mmio_exec;
1037 }
1038
1039 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
1040 {
1041 ASPEED_MACHINE(obj)->mmio_exec = value;
1042 }
1043
1044 static void aspeed_machine_instance_init(Object *obj)
1045 {
1046 ASPEED_MACHINE(obj)->mmio_exec = false;
1047 }
1048
1049 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
1050 {
1051 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1052 return g_strdup(bmc->fmc_model);
1053 }
1054
1055 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
1056 {
1057 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1058
1059 g_free(bmc->fmc_model);
1060 bmc->fmc_model = g_strdup(value);
1061 }
1062
1063 static char *aspeed_get_spi_model(Object *obj, Error **errp)
1064 {
1065 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1066 return g_strdup(bmc->spi_model);
1067 }
1068
1069 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
1070 {
1071 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1072
1073 g_free(bmc->spi_model);
1074 bmc->spi_model = g_strdup(value);
1075 }
1076
1077 static void aspeed_machine_class_props_init(ObjectClass *oc)
1078 {
1079 object_class_property_add_bool(oc, "execute-in-place",
1080 aspeed_get_mmio_exec,
1081 aspeed_set_mmio_exec);
1082 object_class_property_set_description(oc, "execute-in-place",
1083 "boot directly from CE0 flash device");
1084
1085 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
1086 aspeed_set_fmc_model);
1087 object_class_property_set_description(oc, "fmc-model",
1088 "Change the FMC Flash model");
1089 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
1090 aspeed_set_spi_model);
1091 object_class_property_set_description(oc, "spi-model",
1092 "Change the SPI Flash model");
1093 }
1094
1095 static int aspeed_soc_num_cpus(const char *soc_name)
1096 {
1097 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
1098 return sc->num_cpus;
1099 }
1100
1101 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
1102 {
1103 MachineClass *mc = MACHINE_CLASS(oc);
1104 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1105
1106 mc->init = aspeed_machine_init;
1107 mc->no_floppy = 1;
1108 mc->no_cdrom = 1;
1109 mc->no_parallel = 1;
1110 mc->default_ram_id = "ram";
1111 amc->macs_mask = ASPEED_MAC0_ON;
1112 amc->uart_default = ASPEED_DEV_UART5;
1113
1114 aspeed_machine_class_props_init(oc);
1115 }
1116
1117 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
1118 {
1119 MachineClass *mc = MACHINE_CLASS(oc);
1120 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1121
1122 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
1123 amc->soc_name = "ast2400-a1";
1124 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
1125 amc->fmc_model = "n25q256a";
1126 amc->spi_model = "mx25l25635f";
1127 amc->num_cs = 1;
1128 amc->i2c_init = palmetto_bmc_i2c_init;
1129 mc->default_ram_size = 256 * MiB;
1130 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1131 aspeed_soc_num_cpus(amc->soc_name);
1132 };
1133
1134 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
1135 {
1136 MachineClass *mc = MACHINE_CLASS(oc);
1137 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1138
1139 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)";
1140 amc->soc_name = "ast2400-a1";
1141 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
1142 amc->fmc_model = "n25q256a";
1143 amc->spi_model = "mx25l25635e";
1144 amc->num_cs = 1;
1145 amc->i2c_init = quanta_q71l_bmc_i2c_init;
1146 mc->default_ram_size = 128 * MiB;
1147 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1148 aspeed_soc_num_cpus(amc->soc_name);
1149 }
1150
1151 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
1152 void *data)
1153 {
1154 MachineClass *mc = MACHINE_CLASS(oc);
1155 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1156
1157 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
1158 amc->soc_name = "ast2400-a1";
1159 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
1160 amc->fmc_model = "mx25l25635e";
1161 amc->spi_model = "mx25l25635e";
1162 amc->num_cs = 1;
1163 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1164 amc->i2c_init = palmetto_bmc_i2c_init;
1165 mc->default_ram_size = 256 * MiB;
1166 }
1167
1168 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
1169 void *data)
1170 {
1171 MachineClass *mc = MACHINE_CLASS(oc);
1172 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1173
1174 mc->desc = "Supermicro X11 SPI BMC (ARM1176)";
1175 amc->soc_name = "ast2500-a1";
1176 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1;
1177 amc->fmc_model = "mx25l25635e";
1178 amc->spi_model = "mx25l25635e";
1179 amc->num_cs = 1;
1180 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1181 amc->i2c_init = palmetto_bmc_i2c_init;
1182 mc->default_ram_size = 512 * MiB;
1183 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1184 aspeed_soc_num_cpus(amc->soc_name);
1185 }
1186
1187 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
1188 {
1189 MachineClass *mc = MACHINE_CLASS(oc);
1190 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1191
1192 mc->desc = "Aspeed AST2500 EVB (ARM1176)";
1193 amc->soc_name = "ast2500-a1";
1194 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1195 amc->fmc_model = "mx25l25635e";
1196 amc->spi_model = "mx25l25635f";
1197 amc->num_cs = 1;
1198 amc->i2c_init = ast2500_evb_i2c_init;
1199 mc->default_ram_size = 512 * MiB;
1200 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1201 aspeed_soc_num_cpus(amc->soc_name);
1202 };
1203
1204 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
1205 {
1206 MachineClass *mc = MACHINE_CLASS(oc);
1207 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1208
1209 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)";
1210 amc->soc_name = "ast2500-a1";
1211 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1212 amc->hw_strap2 = 0;
1213 amc->fmc_model = "n25q256a";
1214 amc->spi_model = "mx25l25635e";
1215 amc->num_cs = 2;
1216 amc->i2c_init = yosemitev2_bmc_i2c_init;
1217 mc->default_ram_size = 512 * MiB;
1218 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1219 aspeed_soc_num_cpus(amc->soc_name);
1220 };
1221
1222 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
1223 {
1224 MachineClass *mc = MACHINE_CLASS(oc);
1225 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1226
1227 mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
1228 amc->soc_name = "ast2500-a1";
1229 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
1230 amc->fmc_model = "n25q256a";
1231 amc->spi_model = "mx66l1g45g";
1232 amc->num_cs = 2;
1233 amc->i2c_init = romulus_bmc_i2c_init;
1234 mc->default_ram_size = 512 * MiB;
1235 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1236 aspeed_soc_num_cpus(amc->soc_name);
1237 };
1238
1239 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
1240 {
1241 MachineClass *mc = MACHINE_CLASS(oc);
1242 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1243
1244 mc->desc = "Facebook Tiogapass BMC (ARM1176)";
1245 amc->soc_name = "ast2500-a1";
1246 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1247 amc->hw_strap2 = 0;
1248 amc->fmc_model = "n25q256a";
1249 amc->spi_model = "mx25l25635e";
1250 amc->num_cs = 2;
1251 amc->i2c_init = tiogapass_bmc_i2c_init;
1252 mc->default_ram_size = 1 * GiB;
1253 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1254 aspeed_soc_num_cpus(amc->soc_name);
1255 aspeed_soc_num_cpus(amc->soc_name);
1256 };
1257
1258 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
1259 {
1260 MachineClass *mc = MACHINE_CLASS(oc);
1261 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1262
1263 mc->desc = "OCP SonoraPass BMC (ARM1176)";
1264 amc->soc_name = "ast2500-a1";
1265 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
1266 amc->fmc_model = "mx66l1g45g";
1267 amc->spi_model = "mx66l1g45g";
1268 amc->num_cs = 2;
1269 amc->i2c_init = sonorapass_bmc_i2c_init;
1270 mc->default_ram_size = 512 * MiB;
1271 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1272 aspeed_soc_num_cpus(amc->soc_name);
1273 };
1274
1275 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
1276 {
1277 MachineClass *mc = MACHINE_CLASS(oc);
1278 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1279
1280 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
1281 amc->soc_name = "ast2500-a1";
1282 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
1283 amc->fmc_model = "mx25l25635f";
1284 amc->spi_model = "mx66l1g45g";
1285 amc->num_cs = 2;
1286 amc->i2c_init = witherspoon_bmc_i2c_init;
1287 mc->default_ram_size = 512 * MiB;
1288 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1289 aspeed_soc_num_cpus(amc->soc_name);
1290 };
1291
1292 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
1293 {
1294 MachineClass *mc = MACHINE_CLASS(oc);
1295 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1296
1297 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)";
1298 amc->soc_name = "ast2600-a3";
1299 amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1300 amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
1301 amc->fmc_model = "mx66u51235f";
1302 amc->spi_model = "mx66u51235f";
1303 amc->num_cs = 1;
1304 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1305 ASPEED_MAC3_ON;
1306 amc->i2c_init = ast2600_evb_i2c_init;
1307 mc->default_ram_size = 1 * GiB;
1308 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1309 aspeed_soc_num_cpus(amc->soc_name);
1310 };
1311
1312 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
1313 {
1314 MachineClass *mc = MACHINE_CLASS(oc);
1315 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1316
1317 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)";
1318 amc->soc_name = "ast2600-a3";
1319 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
1320 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
1321 amc->fmc_model = "mx66l1g45g";
1322 amc->spi_model = "mx66l1g45g";
1323 amc->num_cs = 2;
1324 amc->macs_mask = ASPEED_MAC2_ON;
1325 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
1326 mc->default_ram_size = 1 * GiB;
1327 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1328 aspeed_soc_num_cpus(amc->soc_name);
1329 };
1330
1331 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
1332 {
1333 MachineClass *mc = MACHINE_CLASS(oc);
1334 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1335
1336 mc->desc = "Bytedance G220A BMC (ARM1176)";
1337 amc->soc_name = "ast2500-a1";
1338 amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1339 amc->fmc_model = "n25q512a";
1340 amc->spi_model = "mx25l25635e";
1341 amc->num_cs = 2;
1342 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1343 amc->i2c_init = g220a_bmc_i2c_init;
1344 mc->default_ram_size = 1024 * MiB;
1345 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1346 aspeed_soc_num_cpus(amc->soc_name);
1347 };
1348
1349 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
1350 {
1351 MachineClass *mc = MACHINE_CLASS(oc);
1352 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1353
1354 mc->desc = "Inspur FP5280G2 BMC (ARM1176)";
1355 amc->soc_name = "ast2500-a1";
1356 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
1357 amc->fmc_model = "n25q512a";
1358 amc->spi_model = "mx25l25635e";
1359 amc->num_cs = 2;
1360 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1361 amc->i2c_init = fp5280g2_bmc_i2c_init;
1362 mc->default_ram_size = 512 * MiB;
1363 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1364 aspeed_soc_num_cpus(amc->soc_name);
1365 };
1366
1367 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
1368 {
1369 MachineClass *mc = MACHINE_CLASS(oc);
1370 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1371
1372 mc->desc = "IBM Rainier BMC (Cortex-A7)";
1373 amc->soc_name = "ast2600-a3";
1374 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1375 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1376 amc->fmc_model = "mx66l1g45g";
1377 amc->spi_model = "mx66l1g45g";
1378 amc->num_cs = 2;
1379 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1380 amc->i2c_init = rainier_bmc_i2c_init;
1381 mc->default_ram_size = 1 * GiB;
1382 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1383 aspeed_soc_num_cpus(amc->soc_name);
1384 };
1385
1386 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1387 #if HOST_LONG_BITS == 32
1388 #define FUJI_BMC_RAM_SIZE (1 * GiB)
1389 #else
1390 #define FUJI_BMC_RAM_SIZE (2 * GiB)
1391 #endif
1392
1393 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
1394 {
1395 MachineClass *mc = MACHINE_CLASS(oc);
1396 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1397
1398 mc->desc = "Facebook Fuji BMC (Cortex-A7)";
1399 amc->soc_name = "ast2600-a3";
1400 amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
1401 amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
1402 amc->fmc_model = "mx66l1g45g";
1403 amc->spi_model = "mx66l1g45g";
1404 amc->num_cs = 2;
1405 amc->macs_mask = ASPEED_MAC3_ON;
1406 amc->i2c_init = fuji_bmc_i2c_init;
1407 amc->uart_default = ASPEED_DEV_UART1;
1408 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1409 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1410 aspeed_soc_num_cpus(amc->soc_name);
1411 };
1412
1413 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1414 #if HOST_LONG_BITS == 32
1415 #define BLETCHLEY_BMC_RAM_SIZE (1 * GiB)
1416 #else
1417 #define BLETCHLEY_BMC_RAM_SIZE (2 * GiB)
1418 #endif
1419
1420 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
1421 {
1422 MachineClass *mc = MACHINE_CLASS(oc);
1423 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1424
1425 mc->desc = "Facebook Bletchley BMC (Cortex-A7)";
1426 amc->soc_name = "ast2600-a3";
1427 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1;
1428 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2;
1429 amc->fmc_model = "w25q01jvq";
1430 amc->spi_model = NULL;
1431 amc->num_cs = 2;
1432 amc->macs_mask = ASPEED_MAC2_ON;
1433 amc->i2c_init = bletchley_bmc_i2c_init;
1434 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
1435 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1436 aspeed_soc_num_cpus(amc->soc_name);
1437 }
1438
1439 static void fby35_reset(MachineState *state, ShutdownCause reason)
1440 {
1441 AspeedMachineState *bmc = ASPEED_MACHINE(state);
1442 AspeedGPIOState *gpio = &bmc->soc.gpio;
1443
1444 qemu_devices_reset(reason);
1445
1446 /* Board ID: 7 (Class-1, 4 slots) */
1447 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);
1448 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);
1449 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);
1450 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);
1451
1452 /* Slot presence pins, inverse polarity. (False means present) */
1453 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal);
1454 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal);
1455 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal);
1456 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal);
1457
1458 /* Slot 12v power pins, normal polarity. (True means powered-on) */
1459 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal);
1460 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal);
1461 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal);
1462 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal);
1463 }
1464
1465 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
1466 {
1467 MachineClass *mc = MACHINE_CLASS(oc);
1468 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1469
1470 mc->desc = "Facebook fby35 BMC (Cortex-A7)";
1471 mc->reset = fby35_reset;
1472 amc->fmc_model = "mx66l1g45g";
1473 amc->num_cs = 2;
1474 amc->macs_mask = ASPEED_MAC3_ON;
1475 amc->i2c_init = fby35_i2c_init;
1476 /* FIXME: Replace this macro with something more general */
1477 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1478 }
1479
1480 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
1481 /* Main SYSCLK frequency in Hz (200MHz) */
1482 #define SYSCLK_FRQ 200000000ULL
1483
1484 static void aspeed_minibmc_machine_init(MachineState *machine)
1485 {
1486 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
1487 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
1488 Clock *sysclk;
1489
1490 sysclk = clock_new(OBJECT(machine), "SYSCLK");
1491 clock_set_hz(sysclk, SYSCLK_FRQ);
1492
1493 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
1494 qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
1495
1496 object_property_set_link(OBJECT(&bmc->soc), "memory",
1497 OBJECT(get_system_memory()), &error_abort);
1498 connect_serial_hds_to_uarts(bmc);
1499 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
1500
1501 aspeed_board_init_flashes(&bmc->soc.fmc,
1502 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
1503 amc->num_cs,
1504 0);
1505
1506 aspeed_board_init_flashes(&bmc->soc.spi[0],
1507 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1508 amc->num_cs, amc->num_cs);
1509
1510 aspeed_board_init_flashes(&bmc->soc.spi[1],
1511 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1512 amc->num_cs, (amc->num_cs * 2));
1513
1514 if (amc->i2c_init) {
1515 amc->i2c_init(bmc);
1516 }
1517
1518 armv7m_load_kernel(ARM_CPU(first_cpu),
1519 machine->kernel_filename,
1520 0,
1521 AST1030_INTERNAL_FLASH_SIZE);
1522 }
1523
1524 static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
1525 {
1526 AspeedSoCState *soc = &bmc->soc;
1527
1528 /* U10 24C08 connects to SDA/SCL Groupt 1 by default */
1529 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
1530 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
1531
1532 /* U11 LM75 connects to SDA/SCL Group 2 by default */
1533 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
1534 }
1535
1536 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
1537 void *data)
1538 {
1539 MachineClass *mc = MACHINE_CLASS(oc);
1540 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1541
1542 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
1543 amc->soc_name = "ast1030-a1";
1544 amc->hw_strap1 = 0;
1545 amc->hw_strap2 = 0;
1546 mc->init = aspeed_minibmc_machine_init;
1547 amc->i2c_init = ast1030_evb_i2c_init;
1548 mc->default_ram_size = 0;
1549 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
1550 amc->fmc_model = "sst25vf032b";
1551 amc->spi_model = "sst25vf032b";
1552 amc->num_cs = 2;
1553 amc->macs_mask = 0;
1554 }
1555
1556 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
1557 void *data)
1558 {
1559 MachineClass *mc = MACHINE_CLASS(oc);
1560 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1561
1562 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)";
1563 amc->soc_name = "ast2600-a3";
1564 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1565 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1566 amc->fmc_model = "n25q512a";
1567 amc->spi_model = "n25q512a";
1568 amc->num_cs = 2;
1569 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1570 amc->i2c_init = qcom_dc_scm_bmc_i2c_init;
1571 mc->default_ram_size = 1 * GiB;
1572 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1573 aspeed_soc_num_cpus(amc->soc_name);
1574 };
1575
1576 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
1577 void *data)
1578 {
1579 MachineClass *mc = MACHINE_CLASS(oc);
1580 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1581
1582 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)";
1583 amc->soc_name = "ast2600-a3";
1584 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1585 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1586 amc->fmc_model = "n25q512a";
1587 amc->spi_model = "n25q512a";
1588 amc->num_cs = 2;
1589 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1590 amc->i2c_init = qcom_dc_scm_firework_i2c_init;
1591 mc->default_ram_size = 1 * GiB;
1592 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1593 aspeed_soc_num_cpus(amc->soc_name);
1594 };
1595
1596 static const TypeInfo aspeed_machine_types[] = {
1597 {
1598 .name = MACHINE_TYPE_NAME("palmetto-bmc"),
1599 .parent = TYPE_ASPEED_MACHINE,
1600 .class_init = aspeed_machine_palmetto_class_init,
1601 }, {
1602 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
1603 .parent = TYPE_ASPEED_MACHINE,
1604 .class_init = aspeed_machine_supermicrox11_bmc_class_init,
1605 }, {
1606 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
1607 .parent = TYPE_ASPEED_MACHINE,
1608 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init,
1609 }, {
1610 .name = MACHINE_TYPE_NAME("ast2500-evb"),
1611 .parent = TYPE_ASPEED_MACHINE,
1612 .class_init = aspeed_machine_ast2500_evb_class_init,
1613 }, {
1614 .name = MACHINE_TYPE_NAME("romulus-bmc"),
1615 .parent = TYPE_ASPEED_MACHINE,
1616 .class_init = aspeed_machine_romulus_class_init,
1617 }, {
1618 .name = MACHINE_TYPE_NAME("sonorapass-bmc"),
1619 .parent = TYPE_ASPEED_MACHINE,
1620 .class_init = aspeed_machine_sonorapass_class_init,
1621 }, {
1622 .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
1623 .parent = TYPE_ASPEED_MACHINE,
1624 .class_init = aspeed_machine_witherspoon_class_init,
1625 }, {
1626 .name = MACHINE_TYPE_NAME("ast2600-evb"),
1627 .parent = TYPE_ASPEED_MACHINE,
1628 .class_init = aspeed_machine_ast2600_evb_class_init,
1629 }, {
1630 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"),
1631 .parent = TYPE_ASPEED_MACHINE,
1632 .class_init = aspeed_machine_yosemitev2_class_init,
1633 }, {
1634 .name = MACHINE_TYPE_NAME("tacoma-bmc"),
1635 .parent = TYPE_ASPEED_MACHINE,
1636 .class_init = aspeed_machine_tacoma_class_init,
1637 }, {
1638 .name = MACHINE_TYPE_NAME("tiogapass-bmc"),
1639 .parent = TYPE_ASPEED_MACHINE,
1640 .class_init = aspeed_machine_tiogapass_class_init,
1641 }, {
1642 .name = MACHINE_TYPE_NAME("g220a-bmc"),
1643 .parent = TYPE_ASPEED_MACHINE,
1644 .class_init = aspeed_machine_g220a_class_init,
1645 }, {
1646 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
1647 .parent = TYPE_ASPEED_MACHINE,
1648 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init,
1649 }, {
1650 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"),
1651 .parent = TYPE_ASPEED_MACHINE,
1652 .class_init = aspeed_machine_qcom_firework_class_init,
1653 }, {
1654 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"),
1655 .parent = TYPE_ASPEED_MACHINE,
1656 .class_init = aspeed_machine_fp5280g2_class_init,
1657 }, {
1658 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
1659 .parent = TYPE_ASPEED_MACHINE,
1660 .class_init = aspeed_machine_quanta_q71l_class_init,
1661 }, {
1662 .name = MACHINE_TYPE_NAME("rainier-bmc"),
1663 .parent = TYPE_ASPEED_MACHINE,
1664 .class_init = aspeed_machine_rainier_class_init,
1665 }, {
1666 .name = MACHINE_TYPE_NAME("fuji-bmc"),
1667 .parent = TYPE_ASPEED_MACHINE,
1668 .class_init = aspeed_machine_fuji_class_init,
1669 }, {
1670 .name = MACHINE_TYPE_NAME("bletchley-bmc"),
1671 .parent = TYPE_ASPEED_MACHINE,
1672 .class_init = aspeed_machine_bletchley_class_init,
1673 }, {
1674 .name = MACHINE_TYPE_NAME("fby35-bmc"),
1675 .parent = MACHINE_TYPE_NAME("ast2600-evb"),
1676 .class_init = aspeed_machine_fby35_class_init,
1677 }, {
1678 .name = MACHINE_TYPE_NAME("ast1030-evb"),
1679 .parent = TYPE_ASPEED_MACHINE,
1680 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
1681 }, {
1682 .name = TYPE_ASPEED_MACHINE,
1683 .parent = TYPE_MACHINE,
1684 .instance_size = sizeof(AspeedMachineState),
1685 .instance_init = aspeed_machine_instance_init,
1686 .class_size = sizeof(AspeedMachineClass),
1687 .class_init = aspeed_machine_class_init,
1688 .abstract = true,
1689 }
1690 };
1691
1692 DEFINE_TYPES(aspeed_machine_types)
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