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aspeed: Fix a potential memory leak bug in write_boot_rom()
[mirror_qemu.git] / hw / arm / aspeed.c
1 /*
2 * OpenPOWER Palmetto BMC
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "hw/arm/boot.h"
15 #include "hw/arm/aspeed.h"
16 #include "hw/arm/aspeed_soc.h"
17 #include "hw/i2c/i2c_mux_pca954x.h"
18 #include "hw/i2c/smbus_eeprom.h"
19 #include "hw/misc/pca9552.h"
20 #include "hw/sensor/tmp105.h"
21 #include "hw/misc/led.h"
22 #include "hw/qdev-properties.h"
23 #include "sysemu/block-backend.h"
24 #include "hw/loader.h"
25 #include "qemu/error-report.h"
26 #include "qemu/units.h"
27
28 static struct arm_boot_info aspeed_board_binfo = {
29 .board_id = -1, /* device-tree-only board */
30 };
31
32 struct AspeedMachineState {
33 /* Private */
34 MachineState parent_obj;
35 /* Public */
36
37 AspeedSoCState soc;
38 MemoryRegion ram_container;
39 MemoryRegion max_ram;
40 bool mmio_exec;
41 char *fmc_model;
42 char *spi_model;
43 };
44
45 /* Palmetto hardware value: 0x120CE416 */
46 #define PALMETTO_BMC_HW_STRAP1 ( \
47 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
48 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
49 SCU_AST2400_HW_STRAP_ACPI_DIS | \
50 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
51 SCU_HW_STRAP_VGA_CLASS_CODE | \
52 SCU_HW_STRAP_LPC_RESET_PIN | \
53 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
54 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
55 SCU_HW_STRAP_SPI_WIDTH | \
56 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
57 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
58
59 /* TODO: Find the actual hardware value */
60 #define SUPERMICROX11_BMC_HW_STRAP1 ( \
61 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
62 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
63 SCU_AST2400_HW_STRAP_ACPI_DIS | \
64 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
65 SCU_HW_STRAP_VGA_CLASS_CODE | \
66 SCU_HW_STRAP_LPC_RESET_PIN | \
67 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
68 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
69 SCU_HW_STRAP_SPI_WIDTH | \
70 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
71 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
72
73 /* AST2500 evb hardware value: 0xF100C2E6 */
74 #define AST2500_EVB_HW_STRAP1 (( \
75 AST2500_HW_STRAP1_DEFAULTS | \
76 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
77 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
78 SCU_AST2500_HW_STRAP_UART_DEBUG | \
79 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
80 SCU_HW_STRAP_MAC1_RGMII | \
81 SCU_HW_STRAP_MAC0_RGMII) & \
82 ~SCU_HW_STRAP_2ND_BOOT_WDT)
83
84 /* Romulus hardware value: 0xF10AD206 */
85 #define ROMULUS_BMC_HW_STRAP1 ( \
86 AST2500_HW_STRAP1_DEFAULTS | \
87 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
88 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
89 SCU_AST2500_HW_STRAP_UART_DEBUG | \
90 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
91 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
92 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
93
94 /* Sonorapass hardware value: 0xF100D216 */
95 #define SONORAPASS_BMC_HW_STRAP1 ( \
96 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
97 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
98 SCU_AST2500_HW_STRAP_UART_DEBUG | \
99 SCU_AST2500_HW_STRAP_RESERVED28 | \
100 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
101 SCU_HW_STRAP_VGA_CLASS_CODE | \
102 SCU_HW_STRAP_LPC_RESET_PIN | \
103 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
104 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
105 SCU_HW_STRAP_VGA_BIOS_ROM | \
106 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
107 SCU_AST2500_HW_STRAP_RESERVED1)
108
109 #define G220A_BMC_HW_STRAP1 ( \
110 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
111 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
112 SCU_AST2500_HW_STRAP_UART_DEBUG | \
113 SCU_AST2500_HW_STRAP_RESERVED28 | \
114 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
115 SCU_HW_STRAP_2ND_BOOT_WDT | \
116 SCU_HW_STRAP_VGA_CLASS_CODE | \
117 SCU_HW_STRAP_LPC_RESET_PIN | \
118 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
119 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
120 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \
121 SCU_AST2500_HW_STRAP_RESERVED1)
122
123 /* FP5280G2 hardware value: 0XF100D286 */
124 #define FP5280G2_BMC_HW_STRAP1 ( \
125 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
126 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
127 SCU_AST2500_HW_STRAP_UART_DEBUG | \
128 SCU_AST2500_HW_STRAP_RESERVED28 | \
129 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
130 SCU_HW_STRAP_VGA_CLASS_CODE | \
131 SCU_HW_STRAP_LPC_RESET_PIN | \
132 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
133 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
134 SCU_HW_STRAP_MAC1_RGMII | \
135 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
136 SCU_AST2500_HW_STRAP_RESERVED1)
137
138 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
139 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
140
141 /* Quanta-Q71l hardware value */
142 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \
143 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
144 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
145 SCU_AST2400_HW_STRAP_ACPI_DIS | \
146 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \
147 SCU_HW_STRAP_VGA_CLASS_CODE | \
148 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \
149 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
150 SCU_HW_STRAP_SPI_WIDTH | \
151 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \
152 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
153
154 /* AST2600 evb hardware value */
155 #define AST2600_EVB_HW_STRAP1 0x000000C0
156 #define AST2600_EVB_HW_STRAP2 0x00000003
157
158 /* Tacoma hardware value */
159 #define TACOMA_BMC_HW_STRAP1 0x00000000
160 #define TACOMA_BMC_HW_STRAP2 0x00000040
161
162 /* Rainier hardware value: (QEMU prototype) */
163 #define RAINIER_BMC_HW_STRAP1 0x00422016
164 #define RAINIER_BMC_HW_STRAP2 0x80000848
165
166 /* Fuji hardware value */
167 #define FUJI_BMC_HW_STRAP1 0x00000000
168 #define FUJI_BMC_HW_STRAP2 0x00000000
169
170 /*
171 * The max ram region is for firmwares that scan the address space
172 * with load/store to guess how much RAM the SoC has.
173 */
174 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size)
175 {
176 return 0;
177 }
178
179 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value,
180 unsigned size)
181 {
182 /* Discard writes */
183 }
184
185 static const MemoryRegionOps max_ram_ops = {
186 .read = max_ram_read,
187 .write = max_ram_write,
188 .endianness = DEVICE_NATIVE_ENDIAN,
189 };
190
191 #define AST_SMP_MAILBOX_BASE 0x1e6e2180
192 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
193 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
194 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
195 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
196 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
197 #define AST_SMP_MBOX_GOSIGN 0xabbaab00
198
199 static void aspeed_write_smpboot(ARMCPU *cpu,
200 const struct arm_boot_info *info)
201 {
202 static const uint32_t poll_mailbox_ready[] = {
203 /*
204 * r2 = per-cpu go sign value
205 * r1 = AST_SMP_MBOX_FIELD_ENTRY
206 * r0 = AST_SMP_MBOX_FIELD_GOSIGN
207 */
208 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
209 0xe21000ff, /* ands r0, r0, #255 */
210 0xe59f201c, /* ldr r2, [pc, #28] */
211 0xe1822000, /* orr r2, r2, r0 */
212
213 0xe59f1018, /* ldr r1, [pc, #24] */
214 0xe59f0018, /* ldr r0, [pc, #24] */
215
216 0xe320f002, /* wfe */
217 0xe5904000, /* ldr r4, [r0] */
218 0xe1520004, /* cmp r2, r4 */
219 0x1afffffb, /* bne <wfe> */
220 0xe591f000, /* ldr pc, [r1] */
221 AST_SMP_MBOX_GOSIGN,
222 AST_SMP_MBOX_FIELD_ENTRY,
223 AST_SMP_MBOX_FIELD_GOSIGN,
224 };
225
226 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
227 sizeof(poll_mailbox_ready),
228 info->smp_loader_start);
229 }
230
231 static void aspeed_reset_secondary(ARMCPU *cpu,
232 const struct arm_boot_info *info)
233 {
234 AddressSpace *as = arm_boot_address_space(cpu, info);
235 CPUState *cs = CPU(cpu);
236
237 /* info->smp_bootreg_addr */
238 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
239 MEMTXATTRS_UNSPECIFIED, NULL);
240 cpu_set_pc(cs, info->smp_loader_start);
241 }
242
243 #define FIRMWARE_ADDR 0x0
244
245 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
246 Error **errp)
247 {
248 BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
249 g_autofree void *storage = NULL;
250 int64_t size;
251
252 /* The block backend size should have already been 'validated' by
253 * the creation of the m25p80 object.
254 */
255 size = blk_getlength(blk);
256 if (size <= 0) {
257 error_setg(errp, "failed to get flash size");
258 return;
259 }
260
261 if (rom_size > size) {
262 rom_size = size;
263 }
264
265 storage = g_malloc0(rom_size);
266 if (blk_pread(blk, 0, storage, rom_size) < 0) {
267 error_setg(errp, "failed to read the initial flash content");
268 return;
269 }
270
271 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
272 }
273
274 static void aspeed_board_init_flashes(AspeedSMCState *s,
275 const char *flashtype,
276 int unit0)
277 {
278 int i ;
279
280 for (i = 0; i < s->num_cs; ++i) {
281 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
282 qemu_irq cs_line;
283 DeviceState *dev;
284
285 dev = qdev_new(flashtype);
286 if (dinfo) {
287 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
288 }
289 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
290
291 cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
292 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
293 }
294 }
295
296 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
297 {
298 DeviceState *card;
299
300 if (!dinfo) {
301 return;
302 }
303 card = qdev_new(TYPE_SD_CARD);
304 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
305 &error_fatal);
306 qdev_realize_and_unref(card,
307 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
308 &error_fatal);
309 }
310
311 static void aspeed_machine_init(MachineState *machine)
312 {
313 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
314 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
315 AspeedSoCClass *sc;
316 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
317 ram_addr_t max_ram_size;
318 int i;
319 NICInfo *nd = &nd_table[0];
320
321 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container",
322 4 * GiB);
323 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram);
324
325 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
326
327 sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
328
329 /*
330 * This will error out if isize is not supported by memory controller.
331 */
332 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
333 &error_fatal);
334
335 for (i = 0; i < sc->macs_num; i++) {
336 if ((amc->macs_mask & (1 << i)) && nd->used) {
337 qemu_check_nic_model(nd, TYPE_FTGMAC100);
338 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
339 nd++;
340 }
341 }
342
343 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
344 &error_abort);
345 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
346 &error_abort);
347 object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs,
348 &error_abort);
349 object_property_set_link(OBJECT(&bmc->soc), "dram",
350 OBJECT(machine->ram), &error_abort);
351 if (machine->kernel_filename) {
352 /*
353 * When booting with a -kernel command line there is no u-boot
354 * that runs to unlock the SCU. In this case set the default to
355 * be unlocked as the kernel expects
356 */
357 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
358 ASPEED_SCU_PROT_KEY, &error_abort);
359 }
360 qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default",
361 amc->uart_default);
362 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
363
364 memory_region_add_subregion(get_system_memory(),
365 sc->memmap[ASPEED_DEV_SDRAM],
366 &bmc->ram_container);
367
368 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
369 &error_abort);
370 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
371 "max_ram", max_ram_size - machine->ram_size);
372 memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram);
373
374 aspeed_board_init_flashes(&bmc->soc.fmc,
375 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
376 0);
377 aspeed_board_init_flashes(&bmc->soc.spi[0],
378 bmc->spi_model ? bmc->spi_model : amc->spi_model,
379 bmc->soc.fmc.num_cs);
380
381 /* Install first FMC flash content as a boot rom. */
382 if (drive0) {
383 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
384 MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
385 uint64_t size = memory_region_size(&fl->mmio);
386
387 /*
388 * create a ROM region using the default mapping window size of
389 * the flash module. The window size is 64MB for the AST2400
390 * SoC and 128MB for the AST2500 SoC, which is twice as big as
391 * needed by the flash modules of the Aspeed machines.
392 */
393 if (ASPEED_MACHINE(machine)->mmio_exec) {
394 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom",
395 &fl->mmio, 0, size);
396 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
397 boot_rom);
398 } else {
399 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom",
400 size, &error_abort);
401 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
402 boot_rom);
403 write_boot_rom(drive0, FIRMWARE_ADDR, size, &error_abort);
404 }
405 }
406
407 if (machine->kernel_filename && sc->num_cpus > 1) {
408 /* With no u-boot we must set up a boot stub for the secondary CPU */
409 MemoryRegion *smpboot = g_new(MemoryRegion, 1);
410 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
411 0x80, &error_abort);
412 memory_region_add_subregion(get_system_memory(),
413 AST_SMP_MAILBOX_BASE, smpboot);
414
415 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
416 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
417 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
418 }
419
420 aspeed_board_binfo.ram_size = machine->ram_size;
421 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
422
423 if (amc->i2c_init) {
424 amc->i2c_init(bmc);
425 }
426
427 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
428 sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
429 drive_get(IF_SD, 0, i));
430 }
431
432 if (bmc->soc.emmc.num_slots) {
433 sdhci_attach_drive(&bmc->soc.emmc.slots[0],
434 drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
435 }
436
437 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
438 }
439
440 static void at24c_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
441 {
442 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
443 DeviceState *dev = DEVICE(i2c_dev);
444
445 qdev_prop_set_uint32(dev, "rom-size", rsize);
446 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
447 }
448
449 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
450 {
451 AspeedSoCState *soc = &bmc->soc;
452 DeviceState *dev;
453 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
454
455 /* The palmetto platform expects a ds3231 RTC but a ds1338 is
456 * enough to provide basic RTC features. Alarms will be missing */
457 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
458
459 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
460 eeprom_buf);
461
462 /* add a TMP423 temperature sensor */
463 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
464 "tmp423", 0x4c));
465 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
466 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
467 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
468 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
469 }
470
471 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
472 {
473 AspeedSoCState *soc = &bmc->soc;
474
475 /*
476 * The quanta-q71l platform expects tmp75s which are compatible with
477 * tmp105s.
478 */
479 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
480 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
481 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
482
483 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
484 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
485 /* TODO: Add Memory Riser i2c mux and eeproms. */
486
487 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
488 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
489
490 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
491
492 /* i2c-7 */
493 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
494 /* - i2c@0: pmbus@59 */
495 /* - i2c@1: pmbus@58 */
496 /* - i2c@2: pmbus@58 */
497 /* - i2c@3: pmbus@59 */
498
499 /* TODO: i2c-7: Add PDB FRU eeprom@52 */
500 /* TODO: i2c-8: Add BMC FRU eeprom@50 */
501 }
502
503 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
504 {
505 AspeedSoCState *soc = &bmc->soc;
506 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
507
508 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
509 eeprom_buf);
510
511 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
512 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
513 TYPE_TMP105, 0x4d);
514
515 /* The AST2500 EVB does not have an RTC. Let's pretend that one is
516 * plugged on the I2C bus header */
517 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
518 }
519
520 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
521 {
522 /* Start with some devices on our I2C busses */
523 ast2500_evb_i2c_init(bmc);
524 }
525
526 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
527 {
528 AspeedSoCState *soc = &bmc->soc;
529
530 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
531 * good enough */
532 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
533 }
534
535 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
536 {
537 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
538 TYPE_PCA9552, addr);
539 }
540
541 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
542 {
543 AspeedSoCState *soc = &bmc->soc;
544
545 /* bus 2 : */
546 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
547 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
548 /* bus 2 : pca9546 @ 0x73 */
549
550 /* bus 3 : pca9548 @ 0x70 */
551
552 /* bus 4 : */
553 uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
554 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
555 eeprom4_54);
556 /* PCA9539 @ 0x76, but PCA9552 is compatible */
557 create_pca9552(soc, 4, 0x76);
558 /* PCA9539 @ 0x77, but PCA9552 is compatible */
559 create_pca9552(soc, 4, 0x77);
560
561 /* bus 6 : */
562 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
563 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
564 /* bus 6 : pca9546 @ 0x73 */
565
566 /* bus 8 : */
567 uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
568 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
569 eeprom8_56);
570 create_pca9552(soc, 8, 0x60);
571 create_pca9552(soc, 8, 0x61);
572 /* bus 8 : adc128d818 @ 0x1d */
573 /* bus 8 : adc128d818 @ 0x1f */
574
575 /*
576 * bus 13 : pca9548 @ 0x71
577 * - channel 3:
578 * - tmm421 @ 0x4c
579 * - tmp421 @ 0x4e
580 * - tmp421 @ 0x4f
581 */
582
583 }
584
585 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
586 {
587 static const struct {
588 unsigned gpio_id;
589 LEDColor color;
590 const char *description;
591 bool gpio_polarity;
592 } pca1_leds[] = {
593 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW},
594 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
595 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
596 };
597 AspeedSoCState *soc = &bmc->soc;
598 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
599 DeviceState *dev;
600 LEDState *led;
601
602 /* Bus 3: TODO bmp280@77 */
603 /* Bus 3: TODO max31785@52 */
604 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
605 qdev_prop_set_string(dev, "description", "pca1");
606 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
607 aspeed_i2c_get_bus(&soc->i2c, 3),
608 &error_fatal);
609
610 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
611 led = led_create_simple(OBJECT(bmc),
612 pca1_leds[i].gpio_polarity,
613 pca1_leds[i].color,
614 pca1_leds[i].description);
615 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
616 qdev_get_gpio_in(DEVICE(led), 0));
617 }
618 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
619 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
620 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
621
622 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
623 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
624 0x4a);
625
626 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
627 * good enough */
628 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
629
630 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
631 eeprom_buf);
632 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
633 qdev_prop_set_string(dev, "description", "pca0");
634 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
635 aspeed_i2c_get_bus(&soc->i2c, 11),
636 &error_fatal);
637 /* Bus 11: TODO ucd90160@64 */
638 }
639
640 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
641 {
642 AspeedSoCState *soc = &bmc->soc;
643 DeviceState *dev;
644
645 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
646 "emc1413", 0x4c));
647 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
648 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
649 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
650
651 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
652 "emc1413", 0x4c));
653 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
654 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
655 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
656
657 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
658 "emc1413", 0x4c));
659 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
660 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
661 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
662
663 static uint8_t eeprom_buf[2 * 1024] = {
664 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
665 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
666 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
667 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
668 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
669 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
670 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
671 };
672 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
673 eeprom_buf);
674 }
675
676 static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
677 {
678 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
679 DeviceState *dev = DEVICE(i2c_dev);
680
681 qdev_prop_set_uint32(dev, "rom-size", rsize);
682 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
683 }
684
685 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
686 {
687 AspeedSoCState *soc = &bmc->soc;
688 I2CSlave *i2c_mux;
689
690 /* The at24c256 */
691 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
692
693 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
694 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
695 0x48);
696 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
697 0x49);
698
699 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
700 "pca9546", 0x70);
701 /* It expects a TMP112 but a TMP105 is compatible */
702 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
703 0x4a);
704
705 /* It expects a ds3232 but a ds1338 is good enough */
706 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
707
708 /* It expects a pca9555 but a pca9552 is compatible */
709 create_pca9552(soc, 8, 0x30);
710 }
711
712 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
713 {
714 AspeedSoCState *soc = &bmc->soc;
715 I2CSlave *i2c_mux;
716
717 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
718
719 create_pca9552(soc, 3, 0x61);
720
721 /* The rainier expects a TMP275 but a TMP105 is compatible */
722 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
723 0x48);
724 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
725 0x49);
726 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
727 0x4a);
728 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
729 "pca9546", 0x70);
730 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
731 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
732 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
733 create_pca9552(soc, 4, 0x60);
734
735 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
736 0x48);
737 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
738 0x49);
739 create_pca9552(soc, 5, 0x60);
740 create_pca9552(soc, 5, 0x61);
741 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
742 "pca9546", 0x70);
743 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
744 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
745
746 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
747 0x48);
748 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
749 0x4a);
750 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
751 0x4b);
752 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
753 "pca9546", 0x70);
754 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
755 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
756 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
757 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
758
759 create_pca9552(soc, 7, 0x30);
760 create_pca9552(soc, 7, 0x31);
761 create_pca9552(soc, 7, 0x32);
762 create_pca9552(soc, 7, 0x33);
763 /* Bus 7: TODO max31785@52 */
764 create_pca9552(soc, 7, 0x60);
765 create_pca9552(soc, 7, 0x61);
766 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
767 /* Bus 7: TODO si7021-a20@20 */
768 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
769 0x48);
770 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
771 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
772
773 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
774 0x48);
775 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
776 0x4a);
777 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
778 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
779 create_pca9552(soc, 8, 0x60);
780 create_pca9552(soc, 8, 0x61);
781 /* Bus 8: ucd90320@11 */
782 /* Bus 8: ucd90320@b */
783 /* Bus 8: ucd90320@c */
784
785 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
786 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
787 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
788
789 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
790 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
791 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
792
793 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
794 0x48);
795 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
796 0x49);
797 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
798 "pca9546", 0x70);
799 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
800 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
801 create_pca9552(soc, 11, 0x60);
802
803
804 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
805 create_pca9552(soc, 13, 0x60);
806
807 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
808 create_pca9552(soc, 14, 0x60);
809
810 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
811 create_pca9552(soc, 15, 0x60);
812 }
813
814 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
815 I2CBus **channels)
816 {
817 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
818 for (int i = 0; i < 8; i++) {
819 channels[i] = pca954x_i2c_get_bus(mux, i);
820 }
821 }
822
823 #define TYPE_LM75 TYPE_TMP105
824 #define TYPE_TMP75 TYPE_TMP105
825 #define TYPE_TMP422 "tmp422"
826
827 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
828 {
829 AspeedSoCState *soc = &bmc->soc;
830 I2CBus *i2c[144] = {};
831
832 for (int i = 0; i < 16; i++) {
833 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
834 }
835 I2CBus *i2c180 = i2c[2];
836 I2CBus *i2c480 = i2c[8];
837 I2CBus *i2c600 = i2c[11];
838
839 get_pca9548_channels(i2c180, 0x70, &i2c[16]);
840 get_pca9548_channels(i2c480, 0x70, &i2c[24]);
841 /* NOTE: The device tree skips [32, 40) in the alias numbering */
842 get_pca9548_channels(i2c600, 0x77, &i2c[40]);
843 get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
844 get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
845 get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
846 get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
847 for (int i = 0; i < 8; i++) {
848 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
849 }
850
851 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
852 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
853
854 aspeed_eeprom_init(i2c[19], 0x52, 64 * KiB);
855 aspeed_eeprom_init(i2c[20], 0x50, 2 * KiB);
856 aspeed_eeprom_init(i2c[22], 0x52, 2 * KiB);
857
858 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
859 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
860 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
861 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
862
863 aspeed_eeprom_init(i2c[8], 0x51, 64 * KiB);
864 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
865
866 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
867 aspeed_eeprom_init(i2c[50], 0x52, 64 * KiB);
868 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
869 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
870
871 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
872 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
873
874 aspeed_eeprom_init(i2c[65], 0x53, 64 * KiB);
875 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
876 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
877 aspeed_eeprom_init(i2c[68], 0x52, 64 * KiB);
878 aspeed_eeprom_init(i2c[69], 0x52, 64 * KiB);
879 aspeed_eeprom_init(i2c[70], 0x52, 64 * KiB);
880 aspeed_eeprom_init(i2c[71], 0x52, 64 * KiB);
881
882 aspeed_eeprom_init(i2c[73], 0x53, 64 * KiB);
883 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
884 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
885 aspeed_eeprom_init(i2c[76], 0x52, 64 * KiB);
886 aspeed_eeprom_init(i2c[77], 0x52, 64 * KiB);
887 aspeed_eeprom_init(i2c[78], 0x52, 64 * KiB);
888 aspeed_eeprom_init(i2c[79], 0x52, 64 * KiB);
889 aspeed_eeprom_init(i2c[28], 0x50, 2 * KiB);
890
891 for (int i = 0; i < 8; i++) {
892 aspeed_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
893 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
894 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
895 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
896 }
897 }
898
899 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
900 {
901 return ASPEED_MACHINE(obj)->mmio_exec;
902 }
903
904 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
905 {
906 ASPEED_MACHINE(obj)->mmio_exec = value;
907 }
908
909 static void aspeed_machine_instance_init(Object *obj)
910 {
911 ASPEED_MACHINE(obj)->mmio_exec = false;
912 }
913
914 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
915 {
916 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
917 return g_strdup(bmc->fmc_model);
918 }
919
920 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
921 {
922 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
923
924 g_free(bmc->fmc_model);
925 bmc->fmc_model = g_strdup(value);
926 }
927
928 static char *aspeed_get_spi_model(Object *obj, Error **errp)
929 {
930 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
931 return g_strdup(bmc->spi_model);
932 }
933
934 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
935 {
936 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
937
938 g_free(bmc->spi_model);
939 bmc->spi_model = g_strdup(value);
940 }
941
942 static void aspeed_machine_class_props_init(ObjectClass *oc)
943 {
944 object_class_property_add_bool(oc, "execute-in-place",
945 aspeed_get_mmio_exec,
946 aspeed_set_mmio_exec);
947 object_class_property_set_description(oc, "execute-in-place",
948 "boot directly from CE0 flash device");
949
950 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
951 aspeed_set_fmc_model);
952 object_class_property_set_description(oc, "fmc-model",
953 "Change the FMC Flash model");
954 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
955 aspeed_set_spi_model);
956 object_class_property_set_description(oc, "spi-model",
957 "Change the SPI Flash model");
958 }
959
960 static int aspeed_soc_num_cpus(const char *soc_name)
961 {
962 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
963 return sc->num_cpus;
964 }
965
966 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
967 {
968 MachineClass *mc = MACHINE_CLASS(oc);
969 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
970
971 mc->init = aspeed_machine_init;
972 mc->no_floppy = 1;
973 mc->no_cdrom = 1;
974 mc->no_parallel = 1;
975 mc->default_ram_id = "ram";
976 amc->macs_mask = ASPEED_MAC0_ON;
977 amc->uart_default = ASPEED_DEV_UART5;
978
979 aspeed_machine_class_props_init(oc);
980 }
981
982 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
983 {
984 MachineClass *mc = MACHINE_CLASS(oc);
985 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
986
987 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
988 amc->soc_name = "ast2400-a1";
989 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
990 amc->fmc_model = "n25q256a";
991 amc->spi_model = "mx25l25635e";
992 amc->num_cs = 1;
993 amc->i2c_init = palmetto_bmc_i2c_init;
994 mc->default_ram_size = 256 * MiB;
995 mc->default_cpus = mc->min_cpus = mc->max_cpus =
996 aspeed_soc_num_cpus(amc->soc_name);
997 };
998
999 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
1000 {
1001 MachineClass *mc = MACHINE_CLASS(oc);
1002 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1003
1004 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)";
1005 amc->soc_name = "ast2400-a1";
1006 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
1007 amc->fmc_model = "n25q256a";
1008 amc->spi_model = "mx25l25635e";
1009 amc->num_cs = 1;
1010 amc->i2c_init = quanta_q71l_bmc_i2c_init;
1011 mc->default_ram_size = 128 * MiB;
1012 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1013 aspeed_soc_num_cpus(amc->soc_name);
1014 }
1015
1016 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
1017 void *data)
1018 {
1019 MachineClass *mc = MACHINE_CLASS(oc);
1020 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1021
1022 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
1023 amc->soc_name = "ast2400-a1";
1024 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
1025 amc->fmc_model = "mx25l25635e";
1026 amc->spi_model = "mx25l25635e";
1027 amc->num_cs = 1;
1028 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1029 amc->i2c_init = palmetto_bmc_i2c_init;
1030 mc->default_ram_size = 256 * MiB;
1031 }
1032
1033 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
1034 {
1035 MachineClass *mc = MACHINE_CLASS(oc);
1036 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1037
1038 mc->desc = "Aspeed AST2500 EVB (ARM1176)";
1039 amc->soc_name = "ast2500-a1";
1040 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1041 amc->fmc_model = "w25q256";
1042 amc->spi_model = "mx25l25635e";
1043 amc->num_cs = 1;
1044 amc->i2c_init = ast2500_evb_i2c_init;
1045 mc->default_ram_size = 512 * MiB;
1046 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1047 aspeed_soc_num_cpus(amc->soc_name);
1048 };
1049
1050 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
1051 {
1052 MachineClass *mc = MACHINE_CLASS(oc);
1053 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1054
1055 mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
1056 amc->soc_name = "ast2500-a1";
1057 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
1058 amc->fmc_model = "n25q256a";
1059 amc->spi_model = "mx66l1g45g";
1060 amc->num_cs = 2;
1061 amc->i2c_init = romulus_bmc_i2c_init;
1062 mc->default_ram_size = 512 * MiB;
1063 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1064 aspeed_soc_num_cpus(amc->soc_name);
1065 };
1066
1067 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
1068 {
1069 MachineClass *mc = MACHINE_CLASS(oc);
1070 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1071
1072 mc->desc = "OCP SonoraPass BMC (ARM1176)";
1073 amc->soc_name = "ast2500-a1";
1074 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
1075 amc->fmc_model = "mx66l1g45g";
1076 amc->spi_model = "mx66l1g45g";
1077 amc->num_cs = 2;
1078 amc->i2c_init = sonorapass_bmc_i2c_init;
1079 mc->default_ram_size = 512 * MiB;
1080 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1081 aspeed_soc_num_cpus(amc->soc_name);
1082 };
1083
1084 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
1085 {
1086 MachineClass *mc = MACHINE_CLASS(oc);
1087 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1088
1089 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
1090 amc->soc_name = "ast2500-a1";
1091 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
1092 amc->fmc_model = "mx25l25635e";
1093 amc->spi_model = "mx66l1g45g";
1094 amc->num_cs = 2;
1095 amc->i2c_init = witherspoon_bmc_i2c_init;
1096 mc->default_ram_size = 512 * MiB;
1097 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1098 aspeed_soc_num_cpus(amc->soc_name);
1099 };
1100
1101 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
1102 {
1103 MachineClass *mc = MACHINE_CLASS(oc);
1104 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1105
1106 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)";
1107 amc->soc_name = "ast2600-a3";
1108 amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1109 amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
1110 amc->fmc_model = "w25q512jv";
1111 amc->spi_model = "mx66u51235f";
1112 amc->num_cs = 1;
1113 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1114 ASPEED_MAC3_ON;
1115 amc->i2c_init = ast2600_evb_i2c_init;
1116 mc->default_ram_size = 1 * GiB;
1117 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1118 aspeed_soc_num_cpus(amc->soc_name);
1119 };
1120
1121 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
1122 {
1123 MachineClass *mc = MACHINE_CLASS(oc);
1124 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1125
1126 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)";
1127 amc->soc_name = "ast2600-a3";
1128 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
1129 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
1130 amc->fmc_model = "mx66l1g45g";
1131 amc->spi_model = "mx66l1g45g";
1132 amc->num_cs = 2;
1133 amc->macs_mask = ASPEED_MAC2_ON;
1134 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
1135 mc->default_ram_size = 1 * GiB;
1136 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1137 aspeed_soc_num_cpus(amc->soc_name);
1138 };
1139
1140 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
1141 {
1142 MachineClass *mc = MACHINE_CLASS(oc);
1143 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1144
1145 mc->desc = "Bytedance G220A BMC (ARM1176)";
1146 amc->soc_name = "ast2500-a1";
1147 amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1148 amc->fmc_model = "n25q512a";
1149 amc->spi_model = "mx25l25635e";
1150 amc->num_cs = 2;
1151 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1152 amc->i2c_init = g220a_bmc_i2c_init;
1153 mc->default_ram_size = 1024 * MiB;
1154 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1155 aspeed_soc_num_cpus(amc->soc_name);
1156 };
1157
1158 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
1159 {
1160 MachineClass *mc = MACHINE_CLASS(oc);
1161 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1162
1163 mc->desc = "Inspur FP5280G2 BMC (ARM1176)";
1164 amc->soc_name = "ast2500-a1";
1165 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
1166 amc->fmc_model = "n25q512a";
1167 amc->spi_model = "mx25l25635e";
1168 amc->num_cs = 2;
1169 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1170 amc->i2c_init = fp5280g2_bmc_i2c_init;
1171 mc->default_ram_size = 512 * MiB;
1172 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1173 aspeed_soc_num_cpus(amc->soc_name);
1174 };
1175
1176 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
1177 {
1178 MachineClass *mc = MACHINE_CLASS(oc);
1179 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1180
1181 mc->desc = "IBM Rainier BMC (Cortex-A7)";
1182 amc->soc_name = "ast2600-a3";
1183 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1184 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1185 amc->fmc_model = "mx66l1g45g";
1186 amc->spi_model = "mx66l1g45g";
1187 amc->num_cs = 2;
1188 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1189 amc->i2c_init = rainier_bmc_i2c_init;
1190 mc->default_ram_size = 1 * GiB;
1191 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1192 aspeed_soc_num_cpus(amc->soc_name);
1193 };
1194
1195 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1196 #if HOST_LONG_BITS == 32
1197 #define FUJI_BMC_RAM_SIZE (1 * GiB)
1198 #else
1199 #define FUJI_BMC_RAM_SIZE (2 * GiB)
1200 #endif
1201
1202 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
1203 {
1204 MachineClass *mc = MACHINE_CLASS(oc);
1205 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1206
1207 mc->desc = "Facebook Fuji BMC (Cortex-A7)";
1208 amc->soc_name = "ast2600-a3";
1209 amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
1210 amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
1211 amc->fmc_model = "mx66l1g45g";
1212 amc->spi_model = "mx66l1g45g";
1213 amc->num_cs = 2;
1214 amc->macs_mask = ASPEED_MAC3_ON;
1215 amc->i2c_init = fuji_bmc_i2c_init;
1216 amc->uart_default = ASPEED_DEV_UART1;
1217 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1218 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1219 aspeed_soc_num_cpus(amc->soc_name);
1220 };
1221
1222 static const TypeInfo aspeed_machine_types[] = {
1223 {
1224 .name = MACHINE_TYPE_NAME("palmetto-bmc"),
1225 .parent = TYPE_ASPEED_MACHINE,
1226 .class_init = aspeed_machine_palmetto_class_init,
1227 }, {
1228 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
1229 .parent = TYPE_ASPEED_MACHINE,
1230 .class_init = aspeed_machine_supermicrox11_bmc_class_init,
1231 }, {
1232 .name = MACHINE_TYPE_NAME("ast2500-evb"),
1233 .parent = TYPE_ASPEED_MACHINE,
1234 .class_init = aspeed_machine_ast2500_evb_class_init,
1235 }, {
1236 .name = MACHINE_TYPE_NAME("romulus-bmc"),
1237 .parent = TYPE_ASPEED_MACHINE,
1238 .class_init = aspeed_machine_romulus_class_init,
1239 }, {
1240 .name = MACHINE_TYPE_NAME("sonorapass-bmc"),
1241 .parent = TYPE_ASPEED_MACHINE,
1242 .class_init = aspeed_machine_sonorapass_class_init,
1243 }, {
1244 .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
1245 .parent = TYPE_ASPEED_MACHINE,
1246 .class_init = aspeed_machine_witherspoon_class_init,
1247 }, {
1248 .name = MACHINE_TYPE_NAME("ast2600-evb"),
1249 .parent = TYPE_ASPEED_MACHINE,
1250 .class_init = aspeed_machine_ast2600_evb_class_init,
1251 }, {
1252 .name = MACHINE_TYPE_NAME("tacoma-bmc"),
1253 .parent = TYPE_ASPEED_MACHINE,
1254 .class_init = aspeed_machine_tacoma_class_init,
1255 }, {
1256 .name = MACHINE_TYPE_NAME("g220a-bmc"),
1257 .parent = TYPE_ASPEED_MACHINE,
1258 .class_init = aspeed_machine_g220a_class_init,
1259 }, {
1260 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"),
1261 .parent = TYPE_ASPEED_MACHINE,
1262 .class_init = aspeed_machine_fp5280g2_class_init,
1263 }, {
1264 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
1265 .parent = TYPE_ASPEED_MACHINE,
1266 .class_init = aspeed_machine_quanta_q71l_class_init,
1267 }, {
1268 .name = MACHINE_TYPE_NAME("rainier-bmc"),
1269 .parent = TYPE_ASPEED_MACHINE,
1270 .class_init = aspeed_machine_rainier_class_init,
1271 }, {
1272 .name = MACHINE_TYPE_NAME("fuji-bmc"),
1273 .parent = TYPE_ASPEED_MACHINE,
1274 .class_init = aspeed_machine_fuji_class_init,
1275 }, {
1276 .name = TYPE_ASPEED_MACHINE,
1277 .parent = TYPE_MACHINE,
1278 .instance_size = sizeof(AspeedMachineState),
1279 .instance_init = aspeed_machine_instance_init,
1280 .class_size = sizeof(AspeedMachineClass),
1281 .class_init = aspeed_machine_class_init,
1282 .abstract = true,
1283 }
1284 };
1285
1286 DEFINE_TYPES(aspeed_machine_types)
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