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Merge tag 'pull-ppc-20221029' of https://gitlab.com/danielhb/qemu into staging
[mirror_qemu.git] / hw / arm / aspeed.c
1 /*
2 * OpenPOWER Palmetto BMC
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "hw/arm/boot.h"
15 #include "hw/arm/aspeed.h"
16 #include "hw/arm/aspeed_soc.h"
17 #include "hw/i2c/i2c_mux_pca954x.h"
18 #include "hw/i2c/smbus_eeprom.h"
19 #include "hw/misc/pca9552.h"
20 #include "hw/sensor/tmp105.h"
21 #include "hw/misc/led.h"
22 #include "hw/qdev-properties.h"
23 #include "sysemu/block-backend.h"
24 #include "sysemu/reset.h"
25 #include "hw/loader.h"
26 #include "qemu/error-report.h"
27 #include "qemu/units.h"
28 #include "hw/qdev-clock.h"
29 #include "sysemu/sysemu.h"
30
31 static struct arm_boot_info aspeed_board_binfo = {
32 .board_id = -1, /* device-tree-only board */
33 };
34
35 struct AspeedMachineState {
36 /* Private */
37 MachineState parent_obj;
38 /* Public */
39
40 AspeedSoCState soc;
41 bool mmio_exec;
42 char *fmc_model;
43 char *spi_model;
44 };
45
46 /* Palmetto hardware value: 0x120CE416 */
47 #define PALMETTO_BMC_HW_STRAP1 ( \
48 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
49 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
50 SCU_AST2400_HW_STRAP_ACPI_DIS | \
51 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
52 SCU_HW_STRAP_VGA_CLASS_CODE | \
53 SCU_HW_STRAP_LPC_RESET_PIN | \
54 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
55 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
56 SCU_HW_STRAP_SPI_WIDTH | \
57 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
58 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
59
60 /* TODO: Find the actual hardware value */
61 #define SUPERMICROX11_BMC_HW_STRAP1 ( \
62 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
63 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
64 SCU_AST2400_HW_STRAP_ACPI_DIS | \
65 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
66 SCU_HW_STRAP_VGA_CLASS_CODE | \
67 SCU_HW_STRAP_LPC_RESET_PIN | \
68 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
69 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
70 SCU_HW_STRAP_SPI_WIDTH | \
71 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
72 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
73
74 /* AST2500 evb hardware value: 0xF100C2E6 */
75 #define AST2500_EVB_HW_STRAP1 (( \
76 AST2500_HW_STRAP1_DEFAULTS | \
77 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
78 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
79 SCU_AST2500_HW_STRAP_UART_DEBUG | \
80 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
81 SCU_HW_STRAP_MAC1_RGMII | \
82 SCU_HW_STRAP_MAC0_RGMII) & \
83 ~SCU_HW_STRAP_2ND_BOOT_WDT)
84
85 /* Romulus hardware value: 0xF10AD206 */
86 #define ROMULUS_BMC_HW_STRAP1 ( \
87 AST2500_HW_STRAP1_DEFAULTS | \
88 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
89 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
90 SCU_AST2500_HW_STRAP_UART_DEBUG | \
91 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
92 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
93 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
94
95 /* Sonorapass hardware value: 0xF100D216 */
96 #define SONORAPASS_BMC_HW_STRAP1 ( \
97 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
98 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
99 SCU_AST2500_HW_STRAP_UART_DEBUG | \
100 SCU_AST2500_HW_STRAP_RESERVED28 | \
101 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
102 SCU_HW_STRAP_VGA_CLASS_CODE | \
103 SCU_HW_STRAP_LPC_RESET_PIN | \
104 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
105 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
106 SCU_HW_STRAP_VGA_BIOS_ROM | \
107 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
108 SCU_AST2500_HW_STRAP_RESERVED1)
109
110 #define G220A_BMC_HW_STRAP1 ( \
111 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
112 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
113 SCU_AST2500_HW_STRAP_UART_DEBUG | \
114 SCU_AST2500_HW_STRAP_RESERVED28 | \
115 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
116 SCU_HW_STRAP_2ND_BOOT_WDT | \
117 SCU_HW_STRAP_VGA_CLASS_CODE | \
118 SCU_HW_STRAP_LPC_RESET_PIN | \
119 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
120 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
121 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \
122 SCU_AST2500_HW_STRAP_RESERVED1)
123
124 /* FP5280G2 hardware value: 0XF100D286 */
125 #define FP5280G2_BMC_HW_STRAP1 ( \
126 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
127 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
128 SCU_AST2500_HW_STRAP_UART_DEBUG | \
129 SCU_AST2500_HW_STRAP_RESERVED28 | \
130 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
131 SCU_HW_STRAP_VGA_CLASS_CODE | \
132 SCU_HW_STRAP_LPC_RESET_PIN | \
133 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
134 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
135 SCU_HW_STRAP_MAC1_RGMII | \
136 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
137 SCU_AST2500_HW_STRAP_RESERVED1)
138
139 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
140 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
141
142 /* Quanta-Q71l hardware value */
143 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \
144 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
145 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
146 SCU_AST2400_HW_STRAP_ACPI_DIS | \
147 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \
148 SCU_HW_STRAP_VGA_CLASS_CODE | \
149 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \
150 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
151 SCU_HW_STRAP_SPI_WIDTH | \
152 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \
153 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
154
155 /* AST2600 evb hardware value */
156 #define AST2600_EVB_HW_STRAP1 0x000000C0
157 #define AST2600_EVB_HW_STRAP2 0x00000003
158
159 /* Tacoma hardware value */
160 #define TACOMA_BMC_HW_STRAP1 0x00000000
161 #define TACOMA_BMC_HW_STRAP2 0x00000040
162
163 /* Rainier hardware value: (QEMU prototype) */
164 #define RAINIER_BMC_HW_STRAP1 0x00422016
165 #define RAINIER_BMC_HW_STRAP2 0x80000848
166
167 /* Fuji hardware value */
168 #define FUJI_BMC_HW_STRAP1 0x00000000
169 #define FUJI_BMC_HW_STRAP2 0x00000000
170
171 /* Bletchley hardware value */
172 /* TODO: Leave same as EVB for now. */
173 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
174 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
175
176 /* Qualcomm DC-SCM hardware value */
177 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000
178 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041
179
180 #define AST_SMP_MAILBOX_BASE 0x1e6e2180
181 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
182 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
183 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
184 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
185 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
186 #define AST_SMP_MBOX_GOSIGN 0xabbaab00
187
188 static void aspeed_write_smpboot(ARMCPU *cpu,
189 const struct arm_boot_info *info)
190 {
191 static const uint32_t poll_mailbox_ready[] = {
192 /*
193 * r2 = per-cpu go sign value
194 * r1 = AST_SMP_MBOX_FIELD_ENTRY
195 * r0 = AST_SMP_MBOX_FIELD_GOSIGN
196 */
197 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
198 0xe21000ff, /* ands r0, r0, #255 */
199 0xe59f201c, /* ldr r2, [pc, #28] */
200 0xe1822000, /* orr r2, r2, r0 */
201
202 0xe59f1018, /* ldr r1, [pc, #24] */
203 0xe59f0018, /* ldr r0, [pc, #24] */
204
205 0xe320f002, /* wfe */
206 0xe5904000, /* ldr r4, [r0] */
207 0xe1520004, /* cmp r2, r4 */
208 0x1afffffb, /* bne <wfe> */
209 0xe591f000, /* ldr pc, [r1] */
210 AST_SMP_MBOX_GOSIGN,
211 AST_SMP_MBOX_FIELD_ENTRY,
212 AST_SMP_MBOX_FIELD_GOSIGN,
213 };
214
215 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
216 sizeof(poll_mailbox_ready),
217 info->smp_loader_start);
218 }
219
220 static void aspeed_reset_secondary(ARMCPU *cpu,
221 const struct arm_boot_info *info)
222 {
223 AddressSpace *as = arm_boot_address_space(cpu, info);
224 CPUState *cs = CPU(cpu);
225
226 /* info->smp_bootreg_addr */
227 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
228 MEMTXATTRS_UNSPECIFIED, NULL);
229 cpu_set_pc(cs, info->smp_loader_start);
230 }
231
232 #define FIRMWARE_ADDR 0x0
233
234 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
235 Error **errp)
236 {
237 BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
238 g_autofree void *storage = NULL;
239 int64_t size;
240
241 /* The block backend size should have already been 'validated' by
242 * the creation of the m25p80 object.
243 */
244 size = blk_getlength(blk);
245 if (size <= 0) {
246 error_setg(errp, "failed to get flash size");
247 return;
248 }
249
250 if (rom_size > size) {
251 rom_size = size;
252 }
253
254 storage = g_malloc0(rom_size);
255 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
256 error_setg(errp, "failed to read the initial flash content");
257 return;
258 }
259
260 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
261 }
262
263 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
264 unsigned int count, int unit0)
265 {
266 int i;
267
268 if (!flashtype) {
269 return;
270 }
271
272 for (i = 0; i < count; ++i) {
273 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
274 qemu_irq cs_line;
275 DeviceState *dev;
276
277 dev = qdev_new(flashtype);
278 if (dinfo) {
279 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
280 }
281 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
282
283 cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
284 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
285 }
286 }
287
288 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
289 {
290 DeviceState *card;
291
292 if (!dinfo) {
293 return;
294 }
295 card = qdev_new(TYPE_SD_CARD);
296 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
297 &error_fatal);
298 qdev_realize_and_unref(card,
299 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
300 &error_fatal);
301 }
302
303 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
304 {
305 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
306 AspeedSoCState *s = &bmc->soc;
307 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
308
309 aspeed_soc_uart_set_chr(s, amc->uart_default, serial_hd(0));
310 for (int i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
311 if (uart == amc->uart_default) {
312 continue;
313 }
314 aspeed_soc_uart_set_chr(s, uart, serial_hd(i));
315 }
316 }
317
318 static void aspeed_machine_init(MachineState *machine)
319 {
320 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
321 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
322 AspeedSoCClass *sc;
323 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
324 int i;
325 NICInfo *nd = &nd_table[0];
326
327 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
328
329 sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
330
331 /*
332 * This will error out if the RAM size is not supported by the
333 * memory controller of the SoC.
334 */
335 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
336 &error_fatal);
337
338 for (i = 0; i < sc->macs_num; i++) {
339 if ((amc->macs_mask & (1 << i)) && nd->used) {
340 qemu_check_nic_model(nd, TYPE_FTGMAC100);
341 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
342 nd++;
343 }
344 }
345
346 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
347 &error_abort);
348 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
349 &error_abort);
350 object_property_set_link(OBJECT(&bmc->soc), "memory",
351 OBJECT(get_system_memory()), &error_abort);
352 object_property_set_link(OBJECT(&bmc->soc), "dram",
353 OBJECT(machine->ram), &error_abort);
354 if (machine->kernel_filename) {
355 /*
356 * When booting with a -kernel command line there is no u-boot
357 * that runs to unlock the SCU. In this case set the default to
358 * be unlocked as the kernel expects
359 */
360 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
361 ASPEED_SCU_PROT_KEY, &error_abort);
362 }
363 connect_serial_hds_to_uarts(bmc);
364 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
365
366 aspeed_board_init_flashes(&bmc->soc.fmc,
367 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
368 amc->num_cs, 0);
369 aspeed_board_init_flashes(&bmc->soc.spi[0],
370 bmc->spi_model ? bmc->spi_model : amc->spi_model,
371 1, amc->num_cs);
372
373 /* Install first FMC flash content as a boot rom. */
374 if (drive0) {
375 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
376 MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
377 uint64_t size = memory_region_size(&fl->mmio);
378
379 /*
380 * create a ROM region using the default mapping window size of
381 * the flash module. The window size is 64MB for the AST2400
382 * SoC and 128MB for the AST2500 SoC, which is twice as big as
383 * needed by the flash modules of the Aspeed machines.
384 */
385 if (ASPEED_MACHINE(machine)->mmio_exec) {
386 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom",
387 &fl->mmio, 0, size);
388 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
389 boot_rom);
390 } else {
391 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom",
392 size, &error_abort);
393 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
394 boot_rom);
395 write_boot_rom(drive0, FIRMWARE_ADDR, size, &error_abort);
396 }
397 }
398
399 if (machine->kernel_filename && sc->num_cpus > 1) {
400 /* With no u-boot we must set up a boot stub for the secondary CPU */
401 MemoryRegion *smpboot = g_new(MemoryRegion, 1);
402 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
403 0x80, &error_abort);
404 memory_region_add_subregion(get_system_memory(),
405 AST_SMP_MAILBOX_BASE, smpboot);
406
407 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
408 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
409 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
410 }
411
412 aspeed_board_binfo.ram_size = machine->ram_size;
413 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
414
415 if (amc->i2c_init) {
416 amc->i2c_init(bmc);
417 }
418
419 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
420 sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
421 drive_get(IF_SD, 0, i));
422 }
423
424 if (bmc->soc.emmc.num_slots) {
425 sdhci_attach_drive(&bmc->soc.emmc.slots[0],
426 drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
427 }
428
429 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
430 }
431
432 static void at24c_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
433 {
434 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
435 DeviceState *dev = DEVICE(i2c_dev);
436
437 qdev_prop_set_uint32(dev, "rom-size", rsize);
438 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
439 }
440
441 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
442 {
443 AspeedSoCState *soc = &bmc->soc;
444 DeviceState *dev;
445 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
446
447 /* The palmetto platform expects a ds3231 RTC but a ds1338 is
448 * enough to provide basic RTC features. Alarms will be missing */
449 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
450
451 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
452 eeprom_buf);
453
454 /* add a TMP423 temperature sensor */
455 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
456 "tmp423", 0x4c));
457 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
458 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
459 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
460 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
461 }
462
463 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
464 {
465 AspeedSoCState *soc = &bmc->soc;
466
467 /*
468 * The quanta-q71l platform expects tmp75s which are compatible with
469 * tmp105s.
470 */
471 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
472 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
473 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
474
475 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
476 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
477 /* TODO: Add Memory Riser i2c mux and eeproms. */
478
479 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
480 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
481
482 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
483
484 /* i2c-7 */
485 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
486 /* - i2c@0: pmbus@59 */
487 /* - i2c@1: pmbus@58 */
488 /* - i2c@2: pmbus@58 */
489 /* - i2c@3: pmbus@59 */
490
491 /* TODO: i2c-7: Add PDB FRU eeprom@52 */
492 /* TODO: i2c-8: Add BMC FRU eeprom@50 */
493 }
494
495 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
496 {
497 AspeedSoCState *soc = &bmc->soc;
498 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
499
500 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
501 eeprom_buf);
502
503 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
504 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
505 TYPE_TMP105, 0x4d);
506 }
507
508 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
509 {
510 AspeedSoCState *soc = &bmc->soc;
511 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
512
513 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
514 eeprom_buf);
515
516 /* LM75 is compatible with TMP105 driver */
517 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
518 TYPE_TMP105, 0x4d);
519 }
520
521 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
522 {
523 AspeedSoCState *soc = &bmc->soc;
524
525 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
526 * good enough */
527 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
528 }
529
530 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
531 {
532 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
533 TYPE_PCA9552, addr);
534 }
535
536 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
537 {
538 AspeedSoCState *soc = &bmc->soc;
539
540 /* bus 2 : */
541 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
542 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
543 /* bus 2 : pca9546 @ 0x73 */
544
545 /* bus 3 : pca9548 @ 0x70 */
546
547 /* bus 4 : */
548 uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
549 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
550 eeprom4_54);
551 /* PCA9539 @ 0x76, but PCA9552 is compatible */
552 create_pca9552(soc, 4, 0x76);
553 /* PCA9539 @ 0x77, but PCA9552 is compatible */
554 create_pca9552(soc, 4, 0x77);
555
556 /* bus 6 : */
557 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
558 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
559 /* bus 6 : pca9546 @ 0x73 */
560
561 /* bus 8 : */
562 uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
563 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
564 eeprom8_56);
565 create_pca9552(soc, 8, 0x60);
566 create_pca9552(soc, 8, 0x61);
567 /* bus 8 : adc128d818 @ 0x1d */
568 /* bus 8 : adc128d818 @ 0x1f */
569
570 /*
571 * bus 13 : pca9548 @ 0x71
572 * - channel 3:
573 * - tmm421 @ 0x4c
574 * - tmp421 @ 0x4e
575 * - tmp421 @ 0x4f
576 */
577
578 }
579
580 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
581 {
582 static const struct {
583 unsigned gpio_id;
584 LEDColor color;
585 const char *description;
586 bool gpio_polarity;
587 } pca1_leds[] = {
588 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW},
589 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
590 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
591 };
592 AspeedSoCState *soc = &bmc->soc;
593 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
594 DeviceState *dev;
595 LEDState *led;
596
597 /* Bus 3: TODO bmp280@77 */
598 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
599 qdev_prop_set_string(dev, "description", "pca1");
600 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
601 aspeed_i2c_get_bus(&soc->i2c, 3),
602 &error_fatal);
603
604 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
605 led = led_create_simple(OBJECT(bmc),
606 pca1_leds[i].gpio_polarity,
607 pca1_leds[i].color,
608 pca1_leds[i].description);
609 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
610 qdev_get_gpio_in(DEVICE(led), 0));
611 }
612 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
613 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52);
614 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
615 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
616
617 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
618 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
619 0x4a);
620
621 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
622 * good enough */
623 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
624
625 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
626 eeprom_buf);
627 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
628 qdev_prop_set_string(dev, "description", "pca0");
629 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
630 aspeed_i2c_get_bus(&soc->i2c, 11),
631 &error_fatal);
632 /* Bus 11: TODO ucd90160@64 */
633 }
634
635 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
636 {
637 AspeedSoCState *soc = &bmc->soc;
638 DeviceState *dev;
639
640 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
641 "emc1413", 0x4c));
642 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
643 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
644 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
645
646 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
647 "emc1413", 0x4c));
648 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
649 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
650 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
651
652 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
653 "emc1413", 0x4c));
654 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
655 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
656 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
657
658 static uint8_t eeprom_buf[2 * 1024] = {
659 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
660 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
661 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
662 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
663 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
664 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
665 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
666 };
667 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
668 eeprom_buf);
669 }
670
671 static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
672 {
673 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
674 DeviceState *dev = DEVICE(i2c_dev);
675
676 qdev_prop_set_uint32(dev, "rom-size", rsize);
677 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
678 }
679
680 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
681 {
682 AspeedSoCState *soc = &bmc->soc;
683 I2CSlave *i2c_mux;
684
685 /* The at24c256 */
686 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
687
688 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
689 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
690 0x48);
691 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
692 0x49);
693
694 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
695 "pca9546", 0x70);
696 /* It expects a TMP112 but a TMP105 is compatible */
697 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
698 0x4a);
699
700 /* It expects a ds3232 but a ds1338 is good enough */
701 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
702
703 /* It expects a pca9555 but a pca9552 is compatible */
704 create_pca9552(soc, 8, 0x30);
705 }
706
707 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
708 {
709 AspeedSoCState *soc = &bmc->soc;
710 I2CSlave *i2c_mux;
711
712 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
713
714 create_pca9552(soc, 3, 0x61);
715
716 /* The rainier expects a TMP275 but a TMP105 is compatible */
717 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
718 0x48);
719 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
720 0x49);
721 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
722 0x4a);
723 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
724 "pca9546", 0x70);
725 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
726 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
727 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
728 create_pca9552(soc, 4, 0x60);
729
730 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
731 0x48);
732 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
733 0x49);
734 create_pca9552(soc, 5, 0x60);
735 create_pca9552(soc, 5, 0x61);
736 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
737 "pca9546", 0x70);
738 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
739 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
740
741 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
742 0x48);
743 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
744 0x4a);
745 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
746 0x4b);
747 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
748 "pca9546", 0x70);
749 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
750 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
751 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
752 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
753
754 create_pca9552(soc, 7, 0x30);
755 create_pca9552(soc, 7, 0x31);
756 create_pca9552(soc, 7, 0x32);
757 create_pca9552(soc, 7, 0x33);
758 create_pca9552(soc, 7, 0x60);
759 create_pca9552(soc, 7, 0x61);
760 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
761 /* Bus 7: TODO si7021-a20@20 */
762 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
763 0x48);
764 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
765 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
766 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
767
768 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
769 0x48);
770 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
771 0x4a);
772 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
773 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
774 create_pca9552(soc, 8, 0x60);
775 create_pca9552(soc, 8, 0x61);
776 /* Bus 8: ucd90320@11 */
777 /* Bus 8: ucd90320@b */
778 /* Bus 8: ucd90320@c */
779
780 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
781 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
782 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
783
784 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
785 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
786 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
787
788 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
789 0x48);
790 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
791 0x49);
792 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
793 "pca9546", 0x70);
794 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
795 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
796 create_pca9552(soc, 11, 0x60);
797
798
799 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
800 create_pca9552(soc, 13, 0x60);
801
802 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
803 create_pca9552(soc, 14, 0x60);
804
805 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
806 create_pca9552(soc, 15, 0x60);
807 }
808
809 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
810 I2CBus **channels)
811 {
812 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
813 for (int i = 0; i < 8; i++) {
814 channels[i] = pca954x_i2c_get_bus(mux, i);
815 }
816 }
817
818 #define TYPE_LM75 TYPE_TMP105
819 #define TYPE_TMP75 TYPE_TMP105
820 #define TYPE_TMP422 "tmp422"
821
822 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
823 {
824 AspeedSoCState *soc = &bmc->soc;
825 I2CBus *i2c[144] = {};
826
827 for (int i = 0; i < 16; i++) {
828 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
829 }
830 I2CBus *i2c180 = i2c[2];
831 I2CBus *i2c480 = i2c[8];
832 I2CBus *i2c600 = i2c[11];
833
834 get_pca9548_channels(i2c180, 0x70, &i2c[16]);
835 get_pca9548_channels(i2c480, 0x70, &i2c[24]);
836 /* NOTE: The device tree skips [32, 40) in the alias numbering */
837 get_pca9548_channels(i2c600, 0x77, &i2c[40]);
838 get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
839 get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
840 get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
841 get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
842 for (int i = 0; i < 8; i++) {
843 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
844 }
845
846 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
847 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
848
849 aspeed_eeprom_init(i2c[19], 0x52, 64 * KiB);
850 aspeed_eeprom_init(i2c[20], 0x50, 2 * KiB);
851 aspeed_eeprom_init(i2c[22], 0x52, 2 * KiB);
852
853 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
854 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
855 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
856 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
857
858 aspeed_eeprom_init(i2c[8], 0x51, 64 * KiB);
859 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
860
861 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
862 aspeed_eeprom_init(i2c[50], 0x52, 64 * KiB);
863 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
864 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
865
866 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
867 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
868
869 aspeed_eeprom_init(i2c[65], 0x53, 64 * KiB);
870 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
871 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
872 aspeed_eeprom_init(i2c[68], 0x52, 64 * KiB);
873 aspeed_eeprom_init(i2c[69], 0x52, 64 * KiB);
874 aspeed_eeprom_init(i2c[70], 0x52, 64 * KiB);
875 aspeed_eeprom_init(i2c[71], 0x52, 64 * KiB);
876
877 aspeed_eeprom_init(i2c[73], 0x53, 64 * KiB);
878 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
879 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
880 aspeed_eeprom_init(i2c[76], 0x52, 64 * KiB);
881 aspeed_eeprom_init(i2c[77], 0x52, 64 * KiB);
882 aspeed_eeprom_init(i2c[78], 0x52, 64 * KiB);
883 aspeed_eeprom_init(i2c[79], 0x52, 64 * KiB);
884 aspeed_eeprom_init(i2c[28], 0x50, 2 * KiB);
885
886 for (int i = 0; i < 8; i++) {
887 aspeed_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
888 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
889 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
890 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
891 }
892 }
893
894 #define TYPE_TMP421 "tmp421"
895
896 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
897 {
898 AspeedSoCState *soc = &bmc->soc;
899 I2CBus *i2c[13] = {};
900 for (int i = 0; i < 13; i++) {
901 if ((i == 8) || (i == 11)) {
902 continue;
903 }
904 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
905 }
906
907 /* Bus 0 - 5 all have the same config. */
908 for (int i = 0; i < 6; i++) {
909 /* Missing model: ti,ina230 @ 0x45 */
910 /* Missing model: mps,mp5023 @ 0x40 */
911 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f);
912 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */
913 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76);
914 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67);
915 /* Missing model: fsc,fusb302 @ 0x22 */
916 }
917
918 /* Bus 6 */
919 at24c_eeprom_init(i2c[6], 0x56, 65536);
920 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */
921 i2c_slave_create_simple(i2c[6], "ds1338", 0x51);
922
923
924 /* Bus 7 */
925 at24c_eeprom_init(i2c[7], 0x54, 65536);
926
927 /* Bus 9 */
928 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f);
929
930 /* Bus 10 */
931 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f);
932 /* Missing model: ti,hdc1080 @ 0x40 */
933 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67);
934
935 /* Bus 12 */
936 /* Missing model: adi,adm1278 @ 0x11 */
937 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c);
938 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d);
939 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
940 }
941
942 static void fby35_i2c_init(AspeedMachineState *bmc)
943 {
944 AspeedSoCState *soc = &bmc->soc;
945 I2CBus *i2c[16];
946
947 for (int i = 0; i < 16; i++) {
948 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
949 }
950
951 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f);
952 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f);
953 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */
954 i2c_slave_create_simple(i2c[11], "adm1272", 0x44);
955 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
956 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
957
958 aspeed_eeprom_init(i2c[4], 0x51, 128 * KiB);
959 aspeed_eeprom_init(i2c[6], 0x51, 128 * KiB);
960 aspeed_eeprom_init(i2c[8], 0x50, 32 * KiB);
961 aspeed_eeprom_init(i2c[11], 0x51, 128 * KiB);
962 aspeed_eeprom_init(i2c[11], 0x54, 128 * KiB);
963
964 /*
965 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
966 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on
967 * each.
968 */
969 }
970
971 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
972 {
973 AspeedSoCState *soc = &bmc->soc;
974
975 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
976 }
977
978 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
979 {
980 AspeedSoCState *soc = &bmc->soc;
981 I2CSlave *therm_mux, *cpuvr_mux;
982
983 /* Create the generic DC-SCM hardware */
984 qcom_dc_scm_bmc_i2c_init(bmc);
985
986 /* Now create the Firework specific hardware */
987
988 /* I2C7 CPUVR MUX */
989 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
990 "pca9546", 0x70);
991 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72);
992 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72);
993 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72);
994 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72);
995
996 /* I2C8 Thermal Diodes*/
997 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
998 "pca9548", 0x70);
999 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C);
1000 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C);
1001 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48);
1002 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48);
1003 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48);
1004
1005 /* I2C9 Fan Controller (MAX31785) */
1006 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52);
1007 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54);
1008 }
1009
1010 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
1011 {
1012 return ASPEED_MACHINE(obj)->mmio_exec;
1013 }
1014
1015 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
1016 {
1017 ASPEED_MACHINE(obj)->mmio_exec = value;
1018 }
1019
1020 static void aspeed_machine_instance_init(Object *obj)
1021 {
1022 ASPEED_MACHINE(obj)->mmio_exec = false;
1023 }
1024
1025 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
1026 {
1027 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1028 return g_strdup(bmc->fmc_model);
1029 }
1030
1031 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
1032 {
1033 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1034
1035 g_free(bmc->fmc_model);
1036 bmc->fmc_model = g_strdup(value);
1037 }
1038
1039 static char *aspeed_get_spi_model(Object *obj, Error **errp)
1040 {
1041 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1042 return g_strdup(bmc->spi_model);
1043 }
1044
1045 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
1046 {
1047 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1048
1049 g_free(bmc->spi_model);
1050 bmc->spi_model = g_strdup(value);
1051 }
1052
1053 static void aspeed_machine_class_props_init(ObjectClass *oc)
1054 {
1055 object_class_property_add_bool(oc, "execute-in-place",
1056 aspeed_get_mmio_exec,
1057 aspeed_set_mmio_exec);
1058 object_class_property_set_description(oc, "execute-in-place",
1059 "boot directly from CE0 flash device");
1060
1061 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
1062 aspeed_set_fmc_model);
1063 object_class_property_set_description(oc, "fmc-model",
1064 "Change the FMC Flash model");
1065 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
1066 aspeed_set_spi_model);
1067 object_class_property_set_description(oc, "spi-model",
1068 "Change the SPI Flash model");
1069 }
1070
1071 static int aspeed_soc_num_cpus(const char *soc_name)
1072 {
1073 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
1074 return sc->num_cpus;
1075 }
1076
1077 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
1078 {
1079 MachineClass *mc = MACHINE_CLASS(oc);
1080 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1081
1082 mc->init = aspeed_machine_init;
1083 mc->no_floppy = 1;
1084 mc->no_cdrom = 1;
1085 mc->no_parallel = 1;
1086 mc->default_ram_id = "ram";
1087 amc->macs_mask = ASPEED_MAC0_ON;
1088 amc->uart_default = ASPEED_DEV_UART5;
1089
1090 aspeed_machine_class_props_init(oc);
1091 }
1092
1093 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
1094 {
1095 MachineClass *mc = MACHINE_CLASS(oc);
1096 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1097
1098 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
1099 amc->soc_name = "ast2400-a1";
1100 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
1101 amc->fmc_model = "n25q256a";
1102 amc->spi_model = "mx25l25635f";
1103 amc->num_cs = 1;
1104 amc->i2c_init = palmetto_bmc_i2c_init;
1105 mc->default_ram_size = 256 * MiB;
1106 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1107 aspeed_soc_num_cpus(amc->soc_name);
1108 };
1109
1110 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
1111 {
1112 MachineClass *mc = MACHINE_CLASS(oc);
1113 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1114
1115 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)";
1116 amc->soc_name = "ast2400-a1";
1117 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
1118 amc->fmc_model = "n25q256a";
1119 amc->spi_model = "mx25l25635e";
1120 amc->num_cs = 1;
1121 amc->i2c_init = quanta_q71l_bmc_i2c_init;
1122 mc->default_ram_size = 128 * MiB;
1123 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1124 aspeed_soc_num_cpus(amc->soc_name);
1125 }
1126
1127 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
1128 void *data)
1129 {
1130 MachineClass *mc = MACHINE_CLASS(oc);
1131 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1132
1133 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
1134 amc->soc_name = "ast2400-a1";
1135 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
1136 amc->fmc_model = "mx25l25635e";
1137 amc->spi_model = "mx25l25635e";
1138 amc->num_cs = 1;
1139 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1140 amc->i2c_init = palmetto_bmc_i2c_init;
1141 mc->default_ram_size = 256 * MiB;
1142 }
1143
1144 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
1145 {
1146 MachineClass *mc = MACHINE_CLASS(oc);
1147 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1148
1149 mc->desc = "Aspeed AST2500 EVB (ARM1176)";
1150 amc->soc_name = "ast2500-a1";
1151 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1152 amc->fmc_model = "mx25l25635e";
1153 amc->spi_model = "mx25l25635f";
1154 amc->num_cs = 1;
1155 amc->i2c_init = ast2500_evb_i2c_init;
1156 mc->default_ram_size = 512 * MiB;
1157 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1158 aspeed_soc_num_cpus(amc->soc_name);
1159 };
1160
1161 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
1162 {
1163 MachineClass *mc = MACHINE_CLASS(oc);
1164 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1165
1166 mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
1167 amc->soc_name = "ast2500-a1";
1168 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
1169 amc->fmc_model = "n25q256a";
1170 amc->spi_model = "mx66l1g45g";
1171 amc->num_cs = 2;
1172 amc->i2c_init = romulus_bmc_i2c_init;
1173 mc->default_ram_size = 512 * MiB;
1174 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1175 aspeed_soc_num_cpus(amc->soc_name);
1176 };
1177
1178 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
1179 {
1180 MachineClass *mc = MACHINE_CLASS(oc);
1181 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1182
1183 mc->desc = "OCP SonoraPass BMC (ARM1176)";
1184 amc->soc_name = "ast2500-a1";
1185 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
1186 amc->fmc_model = "mx66l1g45g";
1187 amc->spi_model = "mx66l1g45g";
1188 amc->num_cs = 2;
1189 amc->i2c_init = sonorapass_bmc_i2c_init;
1190 mc->default_ram_size = 512 * MiB;
1191 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1192 aspeed_soc_num_cpus(amc->soc_name);
1193 };
1194
1195 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
1196 {
1197 MachineClass *mc = MACHINE_CLASS(oc);
1198 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1199
1200 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
1201 amc->soc_name = "ast2500-a1";
1202 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
1203 amc->fmc_model = "mx25l25635f";
1204 amc->spi_model = "mx66l1g45g";
1205 amc->num_cs = 2;
1206 amc->i2c_init = witherspoon_bmc_i2c_init;
1207 mc->default_ram_size = 512 * MiB;
1208 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1209 aspeed_soc_num_cpus(amc->soc_name);
1210 };
1211
1212 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
1213 {
1214 MachineClass *mc = MACHINE_CLASS(oc);
1215 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1216
1217 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)";
1218 amc->soc_name = "ast2600-a3";
1219 amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1220 amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
1221 amc->fmc_model = "mx66u51235f";
1222 amc->spi_model = "mx66u51235f";
1223 amc->num_cs = 1;
1224 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1225 ASPEED_MAC3_ON;
1226 amc->i2c_init = ast2600_evb_i2c_init;
1227 mc->default_ram_size = 1 * GiB;
1228 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1229 aspeed_soc_num_cpus(amc->soc_name);
1230 };
1231
1232 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
1233 {
1234 MachineClass *mc = MACHINE_CLASS(oc);
1235 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1236
1237 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)";
1238 amc->soc_name = "ast2600-a3";
1239 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
1240 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
1241 amc->fmc_model = "mx66l1g45g";
1242 amc->spi_model = "mx66l1g45g";
1243 amc->num_cs = 2;
1244 amc->macs_mask = ASPEED_MAC2_ON;
1245 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
1246 mc->default_ram_size = 1 * GiB;
1247 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1248 aspeed_soc_num_cpus(amc->soc_name);
1249 };
1250
1251 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
1252 {
1253 MachineClass *mc = MACHINE_CLASS(oc);
1254 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1255
1256 mc->desc = "Bytedance G220A BMC (ARM1176)";
1257 amc->soc_name = "ast2500-a1";
1258 amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1259 amc->fmc_model = "n25q512a";
1260 amc->spi_model = "mx25l25635e";
1261 amc->num_cs = 2;
1262 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1263 amc->i2c_init = g220a_bmc_i2c_init;
1264 mc->default_ram_size = 1024 * MiB;
1265 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1266 aspeed_soc_num_cpus(amc->soc_name);
1267 };
1268
1269 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
1270 {
1271 MachineClass *mc = MACHINE_CLASS(oc);
1272 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1273
1274 mc->desc = "Inspur FP5280G2 BMC (ARM1176)";
1275 amc->soc_name = "ast2500-a1";
1276 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
1277 amc->fmc_model = "n25q512a";
1278 amc->spi_model = "mx25l25635e";
1279 amc->num_cs = 2;
1280 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1281 amc->i2c_init = fp5280g2_bmc_i2c_init;
1282 mc->default_ram_size = 512 * MiB;
1283 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1284 aspeed_soc_num_cpus(amc->soc_name);
1285 };
1286
1287 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
1288 {
1289 MachineClass *mc = MACHINE_CLASS(oc);
1290 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1291
1292 mc->desc = "IBM Rainier BMC (Cortex-A7)";
1293 amc->soc_name = "ast2600-a3";
1294 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1295 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1296 amc->fmc_model = "mx66l1g45g";
1297 amc->spi_model = "mx66l1g45g";
1298 amc->num_cs = 2;
1299 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1300 amc->i2c_init = rainier_bmc_i2c_init;
1301 mc->default_ram_size = 1 * GiB;
1302 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1303 aspeed_soc_num_cpus(amc->soc_name);
1304 };
1305
1306 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1307 #if HOST_LONG_BITS == 32
1308 #define FUJI_BMC_RAM_SIZE (1 * GiB)
1309 #else
1310 #define FUJI_BMC_RAM_SIZE (2 * GiB)
1311 #endif
1312
1313 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
1314 {
1315 MachineClass *mc = MACHINE_CLASS(oc);
1316 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1317
1318 mc->desc = "Facebook Fuji BMC (Cortex-A7)";
1319 amc->soc_name = "ast2600-a3";
1320 amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
1321 amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
1322 amc->fmc_model = "mx66l1g45g";
1323 amc->spi_model = "mx66l1g45g";
1324 amc->num_cs = 2;
1325 amc->macs_mask = ASPEED_MAC3_ON;
1326 amc->i2c_init = fuji_bmc_i2c_init;
1327 amc->uart_default = ASPEED_DEV_UART1;
1328 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1329 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1330 aspeed_soc_num_cpus(amc->soc_name);
1331 };
1332
1333 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1334 #if HOST_LONG_BITS == 32
1335 #define BLETCHLEY_BMC_RAM_SIZE (1 * GiB)
1336 #else
1337 #define BLETCHLEY_BMC_RAM_SIZE (2 * GiB)
1338 #endif
1339
1340 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
1341 {
1342 MachineClass *mc = MACHINE_CLASS(oc);
1343 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1344
1345 mc->desc = "Facebook Bletchley BMC (Cortex-A7)";
1346 amc->soc_name = "ast2600-a3";
1347 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1;
1348 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2;
1349 amc->fmc_model = "w25q01jvq";
1350 amc->spi_model = NULL;
1351 amc->num_cs = 2;
1352 amc->macs_mask = ASPEED_MAC2_ON;
1353 amc->i2c_init = bletchley_bmc_i2c_init;
1354 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
1355 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1356 aspeed_soc_num_cpus(amc->soc_name);
1357 }
1358
1359 static void fby35_reset(MachineState *state, ShutdownCause reason)
1360 {
1361 AspeedMachineState *bmc = ASPEED_MACHINE(state);
1362 AspeedGPIOState *gpio = &bmc->soc.gpio;
1363
1364 qemu_devices_reset(reason);
1365
1366 /* Board ID: 7 (Class-1, 4 slots) */
1367 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);
1368 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);
1369 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);
1370 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);
1371
1372 /* Slot presence pins, inverse polarity. (False means present) */
1373 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal);
1374 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal);
1375 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal);
1376 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal);
1377
1378 /* Slot 12v power pins, normal polarity. (True means powered-on) */
1379 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal);
1380 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal);
1381 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal);
1382 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal);
1383 }
1384
1385 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
1386 {
1387 MachineClass *mc = MACHINE_CLASS(oc);
1388 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1389
1390 mc->desc = "Facebook fby35 BMC (Cortex-A7)";
1391 mc->reset = fby35_reset;
1392 amc->fmc_model = "mx66l1g45g";
1393 amc->num_cs = 2;
1394 amc->macs_mask = ASPEED_MAC3_ON;
1395 amc->i2c_init = fby35_i2c_init;
1396 /* FIXME: Replace this macro with something more general */
1397 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1398 }
1399
1400 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
1401 /* Main SYSCLK frequency in Hz (200MHz) */
1402 #define SYSCLK_FRQ 200000000ULL
1403
1404 static void aspeed_minibmc_machine_init(MachineState *machine)
1405 {
1406 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
1407 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
1408 Clock *sysclk;
1409
1410 sysclk = clock_new(OBJECT(machine), "SYSCLK");
1411 clock_set_hz(sysclk, SYSCLK_FRQ);
1412
1413 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
1414 qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
1415
1416 object_property_set_link(OBJECT(&bmc->soc), "memory",
1417 OBJECT(get_system_memory()), &error_abort);
1418 connect_serial_hds_to_uarts(bmc);
1419 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
1420
1421 aspeed_board_init_flashes(&bmc->soc.fmc,
1422 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
1423 amc->num_cs,
1424 0);
1425
1426 aspeed_board_init_flashes(&bmc->soc.spi[0],
1427 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1428 amc->num_cs, amc->num_cs);
1429
1430 aspeed_board_init_flashes(&bmc->soc.spi[1],
1431 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1432 amc->num_cs, (amc->num_cs * 2));
1433
1434 if (amc->i2c_init) {
1435 amc->i2c_init(bmc);
1436 }
1437
1438 armv7m_load_kernel(ARM_CPU(first_cpu),
1439 machine->kernel_filename,
1440 0,
1441 AST1030_INTERNAL_FLASH_SIZE);
1442 }
1443
1444 static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
1445 {
1446 AspeedSoCState *soc = &bmc->soc;
1447
1448 /* U10 24C08 connects to SDA/SCL Groupt 1 by default */
1449 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
1450 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
1451
1452 /* U11 LM75 connects to SDA/SCL Group 2 by default */
1453 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
1454 }
1455
1456 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
1457 void *data)
1458 {
1459 MachineClass *mc = MACHINE_CLASS(oc);
1460 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1461
1462 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
1463 amc->soc_name = "ast1030-a1";
1464 amc->hw_strap1 = 0;
1465 amc->hw_strap2 = 0;
1466 mc->init = aspeed_minibmc_machine_init;
1467 amc->i2c_init = ast1030_evb_i2c_init;
1468 mc->default_ram_size = 0;
1469 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
1470 amc->fmc_model = "sst25vf032b";
1471 amc->spi_model = "sst25vf032b";
1472 amc->num_cs = 2;
1473 amc->macs_mask = 0;
1474 }
1475
1476 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
1477 void *data)
1478 {
1479 MachineClass *mc = MACHINE_CLASS(oc);
1480 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1481
1482 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)";
1483 amc->soc_name = "ast2600-a3";
1484 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1485 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1486 amc->fmc_model = "n25q512a";
1487 amc->spi_model = "n25q512a";
1488 amc->num_cs = 2;
1489 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1490 amc->i2c_init = qcom_dc_scm_bmc_i2c_init;
1491 mc->default_ram_size = 1 * GiB;
1492 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1493 aspeed_soc_num_cpus(amc->soc_name);
1494 };
1495
1496 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
1497 void *data)
1498 {
1499 MachineClass *mc = MACHINE_CLASS(oc);
1500 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1501
1502 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)";
1503 amc->soc_name = "ast2600-a3";
1504 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1505 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1506 amc->fmc_model = "n25q512a";
1507 amc->spi_model = "n25q512a";
1508 amc->num_cs = 2;
1509 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1510 amc->i2c_init = qcom_dc_scm_firework_i2c_init;
1511 mc->default_ram_size = 1 * GiB;
1512 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1513 aspeed_soc_num_cpus(amc->soc_name);
1514 };
1515
1516 static const TypeInfo aspeed_machine_types[] = {
1517 {
1518 .name = MACHINE_TYPE_NAME("palmetto-bmc"),
1519 .parent = TYPE_ASPEED_MACHINE,
1520 .class_init = aspeed_machine_palmetto_class_init,
1521 }, {
1522 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
1523 .parent = TYPE_ASPEED_MACHINE,
1524 .class_init = aspeed_machine_supermicrox11_bmc_class_init,
1525 }, {
1526 .name = MACHINE_TYPE_NAME("ast2500-evb"),
1527 .parent = TYPE_ASPEED_MACHINE,
1528 .class_init = aspeed_machine_ast2500_evb_class_init,
1529 }, {
1530 .name = MACHINE_TYPE_NAME("romulus-bmc"),
1531 .parent = TYPE_ASPEED_MACHINE,
1532 .class_init = aspeed_machine_romulus_class_init,
1533 }, {
1534 .name = MACHINE_TYPE_NAME("sonorapass-bmc"),
1535 .parent = TYPE_ASPEED_MACHINE,
1536 .class_init = aspeed_machine_sonorapass_class_init,
1537 }, {
1538 .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
1539 .parent = TYPE_ASPEED_MACHINE,
1540 .class_init = aspeed_machine_witherspoon_class_init,
1541 }, {
1542 .name = MACHINE_TYPE_NAME("ast2600-evb"),
1543 .parent = TYPE_ASPEED_MACHINE,
1544 .class_init = aspeed_machine_ast2600_evb_class_init,
1545 }, {
1546 .name = MACHINE_TYPE_NAME("tacoma-bmc"),
1547 .parent = TYPE_ASPEED_MACHINE,
1548 .class_init = aspeed_machine_tacoma_class_init,
1549 }, {
1550 .name = MACHINE_TYPE_NAME("g220a-bmc"),
1551 .parent = TYPE_ASPEED_MACHINE,
1552 .class_init = aspeed_machine_g220a_class_init,
1553 }, {
1554 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
1555 .parent = TYPE_ASPEED_MACHINE,
1556 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init,
1557 }, {
1558 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"),
1559 .parent = TYPE_ASPEED_MACHINE,
1560 .class_init = aspeed_machine_qcom_firework_class_init,
1561 }, {
1562 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"),
1563 .parent = TYPE_ASPEED_MACHINE,
1564 .class_init = aspeed_machine_fp5280g2_class_init,
1565 }, {
1566 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
1567 .parent = TYPE_ASPEED_MACHINE,
1568 .class_init = aspeed_machine_quanta_q71l_class_init,
1569 }, {
1570 .name = MACHINE_TYPE_NAME("rainier-bmc"),
1571 .parent = TYPE_ASPEED_MACHINE,
1572 .class_init = aspeed_machine_rainier_class_init,
1573 }, {
1574 .name = MACHINE_TYPE_NAME("fuji-bmc"),
1575 .parent = TYPE_ASPEED_MACHINE,
1576 .class_init = aspeed_machine_fuji_class_init,
1577 }, {
1578 .name = MACHINE_TYPE_NAME("bletchley-bmc"),
1579 .parent = TYPE_ASPEED_MACHINE,
1580 .class_init = aspeed_machine_bletchley_class_init,
1581 }, {
1582 .name = MACHINE_TYPE_NAME("fby35-bmc"),
1583 .parent = MACHINE_TYPE_NAME("ast2600-evb"),
1584 .class_init = aspeed_machine_fby35_class_init,
1585 }, {
1586 .name = MACHINE_TYPE_NAME("ast1030-evb"),
1587 .parent = TYPE_ASPEED_MACHINE,
1588 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
1589 }, {
1590 .name = TYPE_ASPEED_MACHINE,
1591 .parent = TYPE_MACHINE,
1592 .instance_size = sizeof(AspeedMachineState),
1593 .instance_init = aspeed_machine_instance_init,
1594 .class_size = sizeof(AspeedMachineClass),
1595 .class_init = aspeed_machine_class_init,
1596 .abstract = true,
1597 }
1598 };
1599
1600 DEFINE_TYPES(aspeed_machine_types)
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