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hw/sd: Configure number of slots exposed by the ASPEED SDHCI model
[mirror_qemu.git] / hw / arm / aspeed_ast2600.c
1 /*
2 * ASPEED SoC 2600 family
3 *
4 * Copyright (c) 2016-2019, IBM Corporation.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 */
9
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "cpu.h"
13 #include "exec/address-spaces.h"
14 #include "hw/misc/unimp.h"
15 #include "hw/arm/aspeed_soc.h"
16 #include "hw/char/serial.h"
17 #include "qemu/log.h"
18 #include "qemu/module.h"
19 #include "qemu/error-report.h"
20 #include "hw/i2c/aspeed_i2c.h"
21 #include "net/net.h"
22 #include "sysemu/sysemu.h"
23
24 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
25
26 static const hwaddr aspeed_soc_ast2600_memmap[] = {
27 [ASPEED_SRAM] = 0x10000000,
28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
29 [ASPEED_IOMEM] = 0x1E600000,
30 [ASPEED_PWM] = 0x1E610000,
31 [ASPEED_FMC] = 0x1E620000,
32 [ASPEED_SPI1] = 0x1E630000,
33 [ASPEED_SPI2] = 0x1E641000,
34 [ASPEED_MII1] = 0x1E650000,
35 [ASPEED_MII2] = 0x1E650008,
36 [ASPEED_MII3] = 0x1E650010,
37 [ASPEED_MII4] = 0x1E650018,
38 [ASPEED_ETH1] = 0x1E660000,
39 [ASPEED_ETH3] = 0x1E670000,
40 [ASPEED_ETH2] = 0x1E680000,
41 [ASPEED_ETH4] = 0x1E690000,
42 [ASPEED_VIC] = 0x1E6C0000,
43 [ASPEED_SDMC] = 0x1E6E0000,
44 [ASPEED_SCU] = 0x1E6E2000,
45 [ASPEED_XDMA] = 0x1E6E7000,
46 [ASPEED_ADC] = 0x1E6E9000,
47 [ASPEED_VIDEO] = 0x1E700000,
48 [ASPEED_SDHCI] = 0x1E740000,
49 [ASPEED_GPIO] = 0x1E780000,
50 [ASPEED_GPIO_1_8V] = 0x1E780800,
51 [ASPEED_RTC] = 0x1E781000,
52 [ASPEED_TIMER1] = 0x1E782000,
53 [ASPEED_WDT] = 0x1E785000,
54 [ASPEED_LPC] = 0x1E789000,
55 [ASPEED_IBT] = 0x1E789140,
56 [ASPEED_I2C] = 0x1E78A000,
57 [ASPEED_UART1] = 0x1E783000,
58 [ASPEED_UART5] = 0x1E784000,
59 [ASPEED_VUART] = 0x1E787000,
60 [ASPEED_SDRAM] = 0x80000000,
61 };
62
63 #define ASPEED_A7MPCORE_ADDR 0x40460000
64
65 #define ASPEED_SOC_AST2600_MAX_IRQ 128
66
67 static const int aspeed_soc_ast2600_irqmap[] = {
68 [ASPEED_UART1] = 47,
69 [ASPEED_UART2] = 48,
70 [ASPEED_UART3] = 49,
71 [ASPEED_UART4] = 50,
72 [ASPEED_UART5] = 8,
73 [ASPEED_VUART] = 8,
74 [ASPEED_FMC] = 39,
75 [ASPEED_SDMC] = 0,
76 [ASPEED_SCU] = 12,
77 [ASPEED_ADC] = 78,
78 [ASPEED_XDMA] = 6,
79 [ASPEED_SDHCI] = 43,
80 [ASPEED_GPIO] = 40,
81 [ASPEED_GPIO_1_8V] = 11,
82 [ASPEED_RTC] = 13,
83 [ASPEED_TIMER1] = 16,
84 [ASPEED_TIMER2] = 17,
85 [ASPEED_TIMER3] = 18,
86 [ASPEED_TIMER4] = 19,
87 [ASPEED_TIMER5] = 20,
88 [ASPEED_TIMER6] = 21,
89 [ASPEED_TIMER7] = 22,
90 [ASPEED_TIMER8] = 23,
91 [ASPEED_WDT] = 24,
92 [ASPEED_PWM] = 44,
93 [ASPEED_LPC] = 35,
94 [ASPEED_IBT] = 35, /* LPC */
95 [ASPEED_I2C] = 110, /* 110 -> 125 */
96 [ASPEED_ETH1] = 2,
97 [ASPEED_ETH2] = 3,
98 [ASPEED_ETH3] = 32,
99 [ASPEED_ETH4] = 33,
100
101 };
102
103 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
104 {
105 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
106
107 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]);
108 }
109
110 static void aspeed_soc_ast2600_init(Object *obj)
111 {
112 AspeedSoCState *s = ASPEED_SOC(obj);
113 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
114 int i;
115 char socname[8];
116 char typename[64];
117
118 if (sscanf(sc->name, "%7s", socname) != 1) {
119 g_assert_not_reached();
120 }
121
122 for (i = 0; i < sc->num_cpus; i++) {
123 object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
124 sizeof(s->cpu[i]), sc->cpu_type,
125 &error_abort, NULL);
126 }
127
128 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
129 sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
130 typename);
131 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
132 sc->silicon_rev);
133 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
134 "hw-strap1", &error_abort);
135 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
136 "hw-strap2", &error_abort);
137 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
138 "hw-prot-key", &error_abort);
139
140 sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore,
141 sizeof(s->a7mpcore), TYPE_A15MPCORE_PRIV);
142
143 sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
144 TYPE_ASPEED_RTC);
145
146 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
147 sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
148 sizeof(s->timerctrl), typename);
149
150 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
151 sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
152 typename);
153
154 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
155 sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
156 typename);
157 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
158 &error_abort);
159
160 for (i = 0; i < sc->spis_num; i++) {
161 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
162 sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
163 sizeof(s->spi[i]), typename);
164 }
165
166 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
167 sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
168 typename);
169 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
170 "ram-size", &error_abort);
171 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
172 "max-ram-size", &error_abort);
173
174 for (i = 0; i < sc->wdts_num; i++) {
175 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
176 sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
177 sizeof(s->wdt[i]), typename);
178 }
179
180 for (i = 0; i < sc->macs_num; i++) {
181 sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
182 sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
183
184 sysbus_init_child_obj(obj, "mii[*]", &s->mii[i], sizeof(s->mii[i]),
185 TYPE_ASPEED_MII);
186 }
187
188 sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
189 TYPE_ASPEED_XDMA);
190
191 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
192 sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio),
193 typename);
194
195 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname);
196 sysbus_init_child_obj(obj, "gpio_1_8v", OBJECT(&s->gpio_1_8v),
197 sizeof(s->gpio_1_8v), typename);
198
199 sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),
200 TYPE_ASPEED_SDHCI);
201
202 object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
203
204 /* Init sd card slot class here so that they're under the correct parent */
205 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
206 sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),
207 sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
208 }
209 }
210
211 /*
212 * ASPEED ast2600 has 0xf as cluster ID
213 *
214 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html
215 */
216 static uint64_t aspeed_calc_affinity(int cpu)
217 {
218 return (0xf << ARM_AFF1_SHIFT) | cpu;
219 }
220
221 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
222 {
223 int i;
224 AspeedSoCState *s = ASPEED_SOC(dev);
225 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
226 Error *err = NULL, *local_err = NULL;
227 qemu_irq irq;
228
229 /* IO space */
230 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM],
231 ASPEED_SOC_IOMEM_SIZE);
232
233 /* Video engine stub */
234 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO],
235 0x1000);
236
237 if (s->num_cpus > sc->num_cpus) {
238 warn_report("%s: invalid number of CPUs %d, using default %d",
239 sc->name, s->num_cpus, sc->num_cpus);
240 s->num_cpus = sc->num_cpus;
241 }
242
243 /* CPU */
244 for (i = 0; i < s->num_cpus; i++) {
245 object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC,
246 "psci-conduit", &error_abort);
247 if (s->num_cpus > 1) {
248 object_property_set_int(OBJECT(&s->cpu[i]),
249 ASPEED_A7MPCORE_ADDR,
250 "reset-cbar", &error_abort);
251 }
252 object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinity(i),
253 "mp-affinity", &error_abort);
254
255 object_property_set_int(OBJECT(&s->cpu[i]), 1125000000, "cntfrq",
256 &error_abort);
257
258 /*
259 * TODO: the secondary CPUs are started and a boot helper
260 * is needed when using -kernel
261 */
262
263 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
264 if (err) {
265 error_propagate(errp, err);
266 return;
267 }
268 }
269
270 /* A7MPCORE */
271 object_property_set_int(OBJECT(&s->a7mpcore), s->num_cpus, "num-cpu",
272 &error_abort);
273 object_property_set_int(OBJECT(&s->a7mpcore),
274 ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL,
275 "num-irq", &error_abort);
276
277 object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
278 &error_abort);
279 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
280
281 for (i = 0; i < s->num_cpus; i++) {
282 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
283 DeviceState *d = DEVICE(qemu_get_cpu(i));
284
285 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
286 sysbus_connect_irq(sbd, i, irq);
287 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
288 sysbus_connect_irq(sbd, i + s->num_cpus, irq);
289 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
290 sysbus_connect_irq(sbd, i + 2 * s->num_cpus, irq);
291 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
292 sysbus_connect_irq(sbd, i + 3 * s->num_cpus, irq);
293 }
294
295 /* SRAM */
296 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
297 sc->sram_size, &err);
298 if (err) {
299 error_propagate(errp, err);
300 return;
301 }
302 memory_region_add_subregion(get_system_memory(),
303 sc->memmap[ASPEED_SRAM], &s->sram);
304
305 /* SCU */
306 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
307 if (err) {
308 error_propagate(errp, err);
309 return;
310 }
311 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);
312
313 /* RTC */
314 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
315 if (err) {
316 error_propagate(errp, err);
317 return;
318 }
319 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]);
320 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
321 aspeed_soc_get_irq(s, ASPEED_RTC));
322
323 /* Timer */
324 object_property_set_link(OBJECT(&s->timerctrl),
325 OBJECT(&s->scu), "scu", &error_abort);
326 object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
327 if (err) {
328 error_propagate(errp, err);
329 return;
330 }
331 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
332 sc->memmap[ASPEED_TIMER1]);
333 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
334 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
335 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
336 }
337
338 /* UART - attach an 8250 to the IO space as our UART5 */
339 if (serial_hd(0)) {
340 qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
341 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2,
342 uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
343 }
344
345 /* I2C */
346 object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err);
347 if (err) {
348 error_propagate(errp, err);
349 return;
350 }
351 object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
352 if (err) {
353 error_propagate(errp, err);
354 return;
355 }
356 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]);
357 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
358 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
359 sc->irqmap[ASPEED_I2C] + i);
360 /*
361 * The AST2600 SoC has one IRQ per I2C bus. Skip the common
362 * IRQ (AST2400 and AST2500) and connect all bussses.
363 */
364 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq);
365 }
366
367 /* FMC, The number of CS is set at the board level */
368 object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err);
369 if (err) {
370 error_propagate(errp, err);
371 return;
372 }
373 object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM],
374 "sdram-base", &err);
375 if (err) {
376 error_propagate(errp, err);
377 return;
378 }
379 object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
380 if (err) {
381 error_propagate(errp, err);
382 return;
383 }
384 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]);
385 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
386 s->fmc.ctrl->flash_window_base);
387 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
388 aspeed_soc_get_irq(s, ASPEED_FMC));
389
390 /* SPI */
391 for (i = 0; i < sc->spis_num; i++) {
392 object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
393 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
394 &local_err);
395 error_propagate(&err, local_err);
396 if (err) {
397 error_propagate(errp, err);
398 return;
399 }
400 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
401 sc->memmap[ASPEED_SPI1 + i]);
402 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
403 s->spi[i].ctrl->flash_window_base);
404 }
405
406 /* SDMC - SDRAM Memory Controller */
407 object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
408 if (err) {
409 error_propagate(errp, err);
410 return;
411 }
412 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]);
413
414 /* Watch dog */
415 for (i = 0; i < sc->wdts_num; i++) {
416 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
417
418 object_property_set_link(OBJECT(&s->wdt[i]),
419 OBJECT(&s->scu), "scu", &error_abort);
420 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
421 if (err) {
422 error_propagate(errp, err);
423 return;
424 }
425 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
426 sc->memmap[ASPEED_WDT] + i * awc->offset);
427 }
428
429 /* Net */
430 for (i = 0; i < nb_nics && i < sc->macs_num; i++) {
431 qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
432 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
433 &err);
434 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
435 &local_err);
436 error_propagate(&err, local_err);
437 if (err) {
438 error_propagate(errp, err);
439 return;
440 }
441 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
442 sc->memmap[ASPEED_ETH1 + i]);
443 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
444 aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
445
446 object_property_set_link(OBJECT(&s->mii[i]), OBJECT(&s->ftgmac100[i]),
447 "nic", &error_abort);
448 object_property_set_bool(OBJECT(&s->mii[i]), true, "realized",
449 &err);
450 if (err) {
451 error_propagate(errp, err);
452 return;
453 }
454
455 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0,
456 sc->memmap[ASPEED_MII1 + i]);
457 }
458
459 /* XDMA */
460 object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
461 if (err) {
462 error_propagate(errp, err);
463 return;
464 }
465 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
466 sc->memmap[ASPEED_XDMA]);
467 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
468 aspeed_soc_get_irq(s, ASPEED_XDMA));
469
470 /* GPIO */
471 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
472 if (err) {
473 error_propagate(errp, err);
474 return;
475 }
476 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]);
477 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
478 aspeed_soc_get_irq(s, ASPEED_GPIO));
479
480 object_property_set_bool(OBJECT(&s->gpio_1_8v), true, "realized", &err);
481 if (err) {
482 error_propagate(errp, err);
483 return;
484 }
485 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
486 sc->memmap[ASPEED_GPIO_1_8V]);
487 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
488 aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V));
489
490 /* SDHCI */
491 object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
492 if (err) {
493 error_propagate(errp, err);
494 return;
495 }
496 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
497 sc->memmap[ASPEED_SDHCI]);
498 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
499 aspeed_soc_get_irq(s, ASPEED_SDHCI));
500 }
501
502 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
503 {
504 DeviceClass *dc = DEVICE_CLASS(oc);
505 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
506
507 dc->realize = aspeed_soc_ast2600_realize;
508
509 sc->name = "ast2600-a0";
510 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
511 sc->silicon_rev = AST2600_A0_SILICON_REV;
512 sc->sram_size = 0x10000;
513 sc->spis_num = 2;
514 sc->wdts_num = 4;
515 sc->macs_num = 4;
516 sc->irqmap = aspeed_soc_ast2600_irqmap;
517 sc->memmap = aspeed_soc_ast2600_memmap;
518 sc->num_cpus = 2;
519 }
520
521 static const TypeInfo aspeed_soc_ast2600_type_info = {
522 .name = "ast2600-a0",
523 .parent = TYPE_ASPEED_SOC,
524 .instance_size = sizeof(AspeedSoCState),
525 .instance_init = aspeed_soc_ast2600_init,
526 .class_init = aspeed_soc_ast2600_class_init,
527 .class_size = sizeof(AspeedSoCClass),
528 };
529
530 static void aspeed_soc_register_types(void)
531 {
532 type_register_static(&aspeed_soc_ast2600_type_info);
533 };
534
535 type_init(aspeed_soc_register_types)
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