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[mirror_qemu.git] / hw / arm / aspeed_ast2600.c
1 /*
2 * ASPEED SoC 2600 family
3 *
4 * Copyright (c) 2016-2019, IBM Corporation.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 */
9
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "hw/misc/unimp.h"
13 #include "hw/arm/aspeed_soc.h"
14 #include "qemu/module.h"
15 #include "qemu/error-report.h"
16 #include "hw/i2c/aspeed_i2c.h"
17 #include "net/net.h"
18 #include "sysemu/sysemu.h"
19
20 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
21 #define ASPEED_SOC_DPMCU_SIZE 0x00040000
22
23 static const hwaddr aspeed_soc_ast2600_memmap[] = {
24 [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR,
25 [ASPEED_DEV_SRAM] = 0x10000000,
26 [ASPEED_DEV_DPMCU] = 0x18000000,
27 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
28 [ASPEED_DEV_IOMEM] = 0x1E600000,
29 [ASPEED_DEV_PWM] = 0x1E610000,
30 [ASPEED_DEV_FMC] = 0x1E620000,
31 [ASPEED_DEV_SPI1] = 0x1E630000,
32 [ASPEED_DEV_SPI2] = 0x1E631000,
33 [ASPEED_DEV_EHCI1] = 0x1E6A1000,
34 [ASPEED_DEV_EHCI2] = 0x1E6A3000,
35 [ASPEED_DEV_MII1] = 0x1E650000,
36 [ASPEED_DEV_MII2] = 0x1E650008,
37 [ASPEED_DEV_MII3] = 0x1E650010,
38 [ASPEED_DEV_MII4] = 0x1E650018,
39 [ASPEED_DEV_ETH1] = 0x1E660000,
40 [ASPEED_DEV_ETH3] = 0x1E670000,
41 [ASPEED_DEV_ETH2] = 0x1E680000,
42 [ASPEED_DEV_ETH4] = 0x1E690000,
43 [ASPEED_DEV_VIC] = 0x1E6C0000,
44 [ASPEED_DEV_HACE] = 0x1E6D0000,
45 [ASPEED_DEV_SDMC] = 0x1E6E0000,
46 [ASPEED_DEV_SCU] = 0x1E6E2000,
47 [ASPEED_DEV_XDMA] = 0x1E6E7000,
48 [ASPEED_DEV_ADC] = 0x1E6E9000,
49 [ASPEED_DEV_DP] = 0x1E6EB000,
50 [ASPEED_DEV_SBC] = 0x1E6F2000,
51 [ASPEED_DEV_EMMC_BC] = 0x1E6f5000,
52 [ASPEED_DEV_VIDEO] = 0x1E700000,
53 [ASPEED_DEV_SDHCI] = 0x1E740000,
54 [ASPEED_DEV_EMMC] = 0x1E750000,
55 [ASPEED_DEV_GPIO] = 0x1E780000,
56 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800,
57 [ASPEED_DEV_RTC] = 0x1E781000,
58 [ASPEED_DEV_TIMER1] = 0x1E782000,
59 [ASPEED_DEV_WDT] = 0x1E785000,
60 [ASPEED_DEV_LPC] = 0x1E789000,
61 [ASPEED_DEV_IBT] = 0x1E789140,
62 [ASPEED_DEV_I2C] = 0x1E78A000,
63 [ASPEED_DEV_PECI] = 0x1E78B000,
64 [ASPEED_DEV_UART1] = 0x1E783000,
65 [ASPEED_DEV_UART2] = 0x1E78D000,
66 [ASPEED_DEV_UART3] = 0x1E78E000,
67 [ASPEED_DEV_UART4] = 0x1E78F000,
68 [ASPEED_DEV_UART5] = 0x1E784000,
69 [ASPEED_DEV_UART6] = 0x1E790000,
70 [ASPEED_DEV_UART7] = 0x1E790100,
71 [ASPEED_DEV_UART8] = 0x1E790200,
72 [ASPEED_DEV_UART9] = 0x1E790300,
73 [ASPEED_DEV_UART10] = 0x1E790400,
74 [ASPEED_DEV_UART11] = 0x1E790500,
75 [ASPEED_DEV_UART12] = 0x1E790600,
76 [ASPEED_DEV_UART13] = 0x1E790700,
77 [ASPEED_DEV_VUART] = 0x1E787000,
78 [ASPEED_DEV_I3C] = 0x1E7A0000,
79 [ASPEED_DEV_SDRAM] = 0x80000000,
80 };
81
82 #define ASPEED_A7MPCORE_ADDR 0x40460000
83
84 #define AST2600_MAX_IRQ 197
85
86 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
87 static const int aspeed_soc_ast2600_irqmap[] = {
88 [ASPEED_DEV_UART1] = 47,
89 [ASPEED_DEV_UART2] = 48,
90 [ASPEED_DEV_UART3] = 49,
91 [ASPEED_DEV_UART4] = 50,
92 [ASPEED_DEV_UART5] = 8,
93 [ASPEED_DEV_UART6] = 57,
94 [ASPEED_DEV_UART7] = 58,
95 [ASPEED_DEV_UART8] = 59,
96 [ASPEED_DEV_UART9] = 60,
97 [ASPEED_DEV_UART10] = 61,
98 [ASPEED_DEV_UART11] = 62,
99 [ASPEED_DEV_UART12] = 63,
100 [ASPEED_DEV_UART13] = 64,
101 [ASPEED_DEV_VUART] = 8,
102 [ASPEED_DEV_FMC] = 39,
103 [ASPEED_DEV_SDMC] = 0,
104 [ASPEED_DEV_SCU] = 12,
105 [ASPEED_DEV_ADC] = 78,
106 [ASPEED_DEV_XDMA] = 6,
107 [ASPEED_DEV_SDHCI] = 43,
108 [ASPEED_DEV_EHCI1] = 5,
109 [ASPEED_DEV_EHCI2] = 9,
110 [ASPEED_DEV_EMMC] = 15,
111 [ASPEED_DEV_GPIO] = 40,
112 [ASPEED_DEV_GPIO_1_8V] = 11,
113 [ASPEED_DEV_RTC] = 13,
114 [ASPEED_DEV_TIMER1] = 16,
115 [ASPEED_DEV_TIMER2] = 17,
116 [ASPEED_DEV_TIMER3] = 18,
117 [ASPEED_DEV_TIMER4] = 19,
118 [ASPEED_DEV_TIMER5] = 20,
119 [ASPEED_DEV_TIMER6] = 21,
120 [ASPEED_DEV_TIMER7] = 22,
121 [ASPEED_DEV_TIMER8] = 23,
122 [ASPEED_DEV_WDT] = 24,
123 [ASPEED_DEV_PWM] = 44,
124 [ASPEED_DEV_LPC] = 35,
125 [ASPEED_DEV_IBT] = 143,
126 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */
127 [ASPEED_DEV_PECI] = 38,
128 [ASPEED_DEV_ETH1] = 2,
129 [ASPEED_DEV_ETH2] = 3,
130 [ASPEED_DEV_HACE] = 4,
131 [ASPEED_DEV_ETH3] = 32,
132 [ASPEED_DEV_ETH4] = 33,
133 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
134 [ASPEED_DEV_DP] = 62,
135 [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */
136 };
137
138 static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev)
139 {
140 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
141
142 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]);
143 }
144
145 static void aspeed_soc_ast2600_init(Object *obj)
146 {
147 AspeedSoCState *s = ASPEED_SOC(obj);
148 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
149 int i;
150 char socname[8];
151 char typename[64];
152
153 if (sscanf(sc->name, "%7s", socname) != 1) {
154 g_assert_not_reached();
155 }
156
157 for (i = 0; i < sc->num_cpus; i++) {
158 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
159 }
160
161 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
162 object_initialize_child(obj, "scu", &s->scu, typename);
163 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
164 sc->silicon_rev);
165 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
166 "hw-strap1");
167 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
168 "hw-strap2");
169 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
170 "hw-prot-key");
171
172 object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
173 TYPE_A15MPCORE_PRIV);
174
175 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
176
177 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
178 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
179
180 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
181 object_initialize_child(obj, "adc", &s->adc, typename);
182
183 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
184 object_initialize_child(obj, "i2c", &s->i2c, typename);
185
186 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
187
188 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
189 object_initialize_child(obj, "fmc", &s->fmc, typename);
190
191 for (i = 0; i < sc->spis_num; i++) {
192 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
193 object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
194 }
195
196 for (i = 0; i < sc->ehcis_num; i++) {
197 object_initialize_child(obj, "ehci[*]", &s->ehci[i],
198 TYPE_PLATFORM_EHCI);
199 }
200
201 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
202 object_initialize_child(obj, "sdmc", &s->sdmc, typename);
203 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
204 "ram-size");
205
206 for (i = 0; i < sc->wdts_num; i++) {
207 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
208 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
209 }
210
211 for (i = 0; i < sc->macs_num; i++) {
212 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
213 TYPE_FTGMAC100);
214
215 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII);
216 }
217
218 for (i = 0; i < sc->uarts_num; i++) {
219 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
220 }
221
222 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname);
223 object_initialize_child(obj, "xdma", &s->xdma, typename);
224
225 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
226 object_initialize_child(obj, "gpio", &s->gpio, typename);
227
228 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname);
229 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename);
230
231 object_initialize_child(obj, "sd-controller", &s->sdhci,
232 TYPE_ASPEED_SDHCI);
233
234 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort);
235
236 /* Init sd card slot class here so that they're under the correct parent */
237 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
238 object_initialize_child(obj, "sd-controller.sdhci[*]",
239 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI);
240 }
241
242 object_initialize_child(obj, "emmc-controller", &s->emmc,
243 TYPE_ASPEED_SDHCI);
244
245 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort);
246
247 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0],
248 TYPE_SYSBUS_SDHCI);
249
250 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
251
252 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
253 object_initialize_child(obj, "hace", &s->hace, typename);
254
255 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
256
257 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
258
259 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
260 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
261 object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE);
262 object_initialize_child(obj, "emmc-boot-controller",
263 &s->emmc_boot_controller,
264 TYPE_UNIMPLEMENTED_DEVICE);
265 }
266
267 /*
268 * ASPEED ast2600 has 0xf as cluster ID
269 *
270 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register
271 */
272 static uint64_t aspeed_calc_affinity(int cpu)
273 {
274 return (0xf << ARM_AFF1_SHIFT) | cpu;
275 }
276
277 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
278 {
279 int i;
280 AspeedSoCState *s = ASPEED_SOC(dev);
281 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
282 Error *err = NULL;
283 qemu_irq irq;
284 g_autofree char *sram_name = NULL;
285
286 /* Default boot region (SPI memory or ROMs) */
287 memory_region_init(&s->spi_boot_container, OBJECT(s),
288 "aspeed.spi_boot_container", 0x10000000);
289 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT],
290 &s->spi_boot_container);
291
292 /* IO space */
293 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
294 sc->memmap[ASPEED_DEV_IOMEM],
295 ASPEED_SOC_IOMEM_SIZE);
296
297 /* Video engine stub */
298 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video",
299 sc->memmap[ASPEED_DEV_VIDEO], 0x1000);
300
301 /* eMMC Boot Controller stub */
302 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->emmc_boot_controller),
303 "aspeed.emmc-boot-controller",
304 sc->memmap[ASPEED_DEV_EMMC_BC], 0x1000);
305
306 /* CPU */
307 for (i = 0; i < sc->num_cpus; i++) {
308 if (sc->num_cpus > 1) {
309 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
310 ASPEED_A7MPCORE_ADDR, &error_abort);
311 }
312 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
313 aspeed_calc_affinity(i), &error_abort);
314
315 object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
316 &error_abort);
317 object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false,
318 &error_abort);
319 object_property_set_bool(OBJECT(&s->cpu[i]), "vfp-d32", false,
320 &error_abort);
321 object_property_set_link(OBJECT(&s->cpu[i]), "memory",
322 OBJECT(s->memory), &error_abort);
323
324 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
325 return;
326 }
327 }
328
329 /* A7MPCORE */
330 object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus,
331 &error_abort);
332 object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
333 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),
334 &error_abort);
335
336 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
337 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
338
339 for (i = 0; i < sc->num_cpus; i++) {
340 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
341 DeviceState *d = DEVICE(&s->cpu[i]);
342
343 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
344 sysbus_connect_irq(sbd, i, irq);
345 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
346 sysbus_connect_irq(sbd, i + sc->num_cpus, irq);
347 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
348 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq);
349 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
350 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq);
351 }
352
353 /* SRAM */
354 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
355 memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
356 if (err) {
357 error_propagate(errp, err);
358 return;
359 }
360 memory_region_add_subregion(s->memory,
361 sc->memmap[ASPEED_DEV_SRAM], &s->sram);
362
363 /* DPMCU */
364 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu",
365 sc->memmap[ASPEED_DEV_DPMCU],
366 ASPEED_SOC_DPMCU_SIZE);
367
368 /* SCU */
369 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
370 return;
371 }
372 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
373
374 /* RTC */
375 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
376 return;
377 }
378 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
379 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
380 aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
381
382 /* Timer */
383 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
384 &error_abort);
385 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
386 return;
387 }
388 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
389 sc->memmap[ASPEED_DEV_TIMER1]);
390 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
391 irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
392 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
393 }
394
395 /* ADC */
396 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
397 return;
398 }
399 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
400 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
401 aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
402
403 /* UART */
404 if (!aspeed_soc_uart_realize(s, errp)) {
405 return;
406 }
407
408 /* I2C */
409 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
410 &error_abort);
411 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
412 return;
413 }
414 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
415 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
416 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
417 sc->irqmap[ASPEED_DEV_I2C] + i);
418 /* The AST2600 I2C controller has one IRQ per bus. */
419 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
420 }
421
422 /* PECI */
423 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
424 return;
425 }
426 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0,
427 sc->memmap[ASPEED_DEV_PECI]);
428 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
429 aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
430
431 /* FMC, The number of CS is set at the board level */
432 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
433 &error_abort);
434 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
435 return;
436 }
437 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
438 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
439 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
440 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
441 aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
442
443 /* Set up an alias on the FMC CE0 region (boot default) */
444 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio;
445 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot",
446 fmc0_mmio, 0, memory_region_size(fmc0_mmio));
447 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot);
448
449 /* SPI */
450 for (i = 0; i < sc->spis_num; i++) {
451 object_property_set_link(OBJECT(&s->spi[i]), "dram",
452 OBJECT(s->dram_mr), &error_abort);
453 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
454 return;
455 }
456 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
457 sc->memmap[ASPEED_DEV_SPI1 + i]);
458 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
459 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
460 }
461
462 /* EHCI */
463 for (i = 0; i < sc->ehcis_num; i++) {
464 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
465 return;
466 }
467 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0,
468 sc->memmap[ASPEED_DEV_EHCI1 + i]);
469 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
470 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
471 }
472
473 /* SDMC - SDRAM Memory Controller */
474 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
475 return;
476 }
477 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
478 sc->memmap[ASPEED_DEV_SDMC]);
479
480 /* Watch dog */
481 for (i = 0; i < sc->wdts_num; i++) {
482 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
483 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
484
485 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
486 &error_abort);
487 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
488 return;
489 }
490 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
491 }
492
493 /* RAM */
494 if (!aspeed_soc_dram_init(s, errp)) {
495 return;
496 }
497
498 /* Net */
499 for (i = 0; i < sc->macs_num; i++) {
500 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
501 &error_abort);
502 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
503 return;
504 }
505 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
506 sc->memmap[ASPEED_DEV_ETH1 + i]);
507 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
508 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
509
510 object_property_set_link(OBJECT(&s->mii[i]), "nic",
511 OBJECT(&s->ftgmac100[i]), &error_abort);
512 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) {
513 return;
514 }
515
516 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0,
517 sc->memmap[ASPEED_DEV_MII1 + i]);
518 }
519
520 /* XDMA */
521 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) {
522 return;
523 }
524 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0,
525 sc->memmap[ASPEED_DEV_XDMA]);
526 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
527 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA));
528
529 /* GPIO */
530 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
531 return;
532 }
533 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]);
534 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
535 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
536
537 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) {
538 return;
539 }
540 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
541 sc->memmap[ASPEED_DEV_GPIO_1_8V]);
542 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
543 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V));
544
545 /* SDHCI */
546 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
547 return;
548 }
549 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0,
550 sc->memmap[ASPEED_DEV_SDHCI]);
551 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
552 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
553
554 /* eMMC */
555 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) {
556 return;
557 }
558 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0,
559 sc->memmap[ASPEED_DEV_EMMC]);
560 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
561 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC));
562
563 /* LPC */
564 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
565 return;
566 }
567 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
568
569 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */
570 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
571 aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
572
573 /*
574 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC.
575 *
576 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters
577 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ
578 * shared across the subdevices, and the shared IRQ output to the VIC is at
579 * offset 0.
580 */
581 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
582 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
583 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
584
585 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
586 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
587 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
588
589 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
590 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
591 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
592
593 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
594 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
595 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
596
597 /* HACE */
598 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),
599 &error_abort);
600 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
601 return;
602 }
603 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
604 sc->memmap[ASPEED_DEV_HACE]);
605 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
606 aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
607
608 /* I3C */
609 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) {
610 return;
611 }
612 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
613 for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
614 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
615 sc->irqmap[ASPEED_DEV_I3C] + i);
616 /* The AST2600 I3C controller has one IRQ per bus. */
617 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
618 }
619
620 /* Secure Boot Controller */
621 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
622 return;
623 }
624 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
625 }
626
627 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
628 {
629 DeviceClass *dc = DEVICE_CLASS(oc);
630 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
631
632 dc->realize = aspeed_soc_ast2600_realize;
633
634 sc->name = "ast2600-a3";
635 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
636 sc->silicon_rev = AST2600_A3_SILICON_REV;
637 sc->sram_size = 0x16400;
638 sc->spis_num = 2;
639 sc->ehcis_num = 2;
640 sc->wdts_num = 4;
641 sc->macs_num = 4;
642 sc->uarts_num = 13;
643 sc->irqmap = aspeed_soc_ast2600_irqmap;
644 sc->memmap = aspeed_soc_ast2600_memmap;
645 sc->num_cpus = 2;
646 sc->get_irq = aspeed_soc_ast2600_get_irq;
647 }
648
649 static const TypeInfo aspeed_soc_ast2600_type_info = {
650 .name = "ast2600-a3",
651 .parent = TYPE_ASPEED_SOC,
652 .instance_size = sizeof(AspeedSoCState),
653 .instance_init = aspeed_soc_ast2600_init,
654 .class_init = aspeed_soc_ast2600_class_init,
655 .class_size = sizeof(AspeedSoCClass),
656 };
657
658 static void aspeed_soc_register_types(void)
659 {
660 type_register_static(&aspeed_soc_ast2600_type_info);
661 };
662
663 type_init(aspeed_soc_register_types)
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