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hw: aspeed: Add uarts_num SoC attribute
[mirror_qemu.git] / hw / arm / aspeed_ast2600.c
1 /*
2 * ASPEED SoC 2600 family
3 *
4 * Copyright (c) 2016-2019, IBM Corporation.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 */
9
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "hw/misc/unimp.h"
13 #include "hw/arm/aspeed_soc.h"
14 #include "hw/char/serial.h"
15 #include "qemu/module.h"
16 #include "qemu/error-report.h"
17 #include "hw/i2c/aspeed_i2c.h"
18 #include "net/net.h"
19 #include "sysemu/sysemu.h"
20
21 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
22 #define ASPEED_SOC_DPMCU_SIZE 0x00040000
23
24 static const hwaddr aspeed_soc_ast2600_memmap[] = {
25 [ASPEED_DEV_SRAM] = 0x10000000,
26 [ASPEED_DEV_DPMCU] = 0x18000000,
27 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
28 [ASPEED_DEV_IOMEM] = 0x1E600000,
29 [ASPEED_DEV_PWM] = 0x1E610000,
30 [ASPEED_DEV_FMC] = 0x1E620000,
31 [ASPEED_DEV_SPI1] = 0x1E630000,
32 [ASPEED_DEV_SPI2] = 0x1E631000,
33 [ASPEED_DEV_EHCI1] = 0x1E6A1000,
34 [ASPEED_DEV_EHCI2] = 0x1E6A3000,
35 [ASPEED_DEV_MII1] = 0x1E650000,
36 [ASPEED_DEV_MII2] = 0x1E650008,
37 [ASPEED_DEV_MII3] = 0x1E650010,
38 [ASPEED_DEV_MII4] = 0x1E650018,
39 [ASPEED_DEV_ETH1] = 0x1E660000,
40 [ASPEED_DEV_ETH3] = 0x1E670000,
41 [ASPEED_DEV_ETH2] = 0x1E680000,
42 [ASPEED_DEV_ETH4] = 0x1E690000,
43 [ASPEED_DEV_VIC] = 0x1E6C0000,
44 [ASPEED_DEV_HACE] = 0x1E6D0000,
45 [ASPEED_DEV_SDMC] = 0x1E6E0000,
46 [ASPEED_DEV_SCU] = 0x1E6E2000,
47 [ASPEED_DEV_XDMA] = 0x1E6E7000,
48 [ASPEED_DEV_ADC] = 0x1E6E9000,
49 [ASPEED_DEV_DP] = 0x1E6EB000,
50 [ASPEED_DEV_SBC] = 0x1E6F2000,
51 [ASPEED_DEV_EMMC_BC] = 0x1E6f5000,
52 [ASPEED_DEV_VIDEO] = 0x1E700000,
53 [ASPEED_DEV_SDHCI] = 0x1E740000,
54 [ASPEED_DEV_EMMC] = 0x1E750000,
55 [ASPEED_DEV_GPIO] = 0x1E780000,
56 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800,
57 [ASPEED_DEV_RTC] = 0x1E781000,
58 [ASPEED_DEV_TIMER1] = 0x1E782000,
59 [ASPEED_DEV_WDT] = 0x1E785000,
60 [ASPEED_DEV_LPC] = 0x1E789000,
61 [ASPEED_DEV_IBT] = 0x1E789140,
62 [ASPEED_DEV_I2C] = 0x1E78A000,
63 [ASPEED_DEV_UART1] = 0x1E783000,
64 [ASPEED_DEV_UART2] = 0x1E78D000,
65 [ASPEED_DEV_UART3] = 0x1E78E000,
66 [ASPEED_DEV_UART4] = 0x1E78F000,
67 [ASPEED_DEV_UART5] = 0x1E784000,
68 [ASPEED_DEV_UART6] = 0x1E790000,
69 [ASPEED_DEV_UART7] = 0x1E790100,
70 [ASPEED_DEV_UART8] = 0x1E790200,
71 [ASPEED_DEV_UART9] = 0x1E790300,
72 [ASPEED_DEV_UART10] = 0x1E790400,
73 [ASPEED_DEV_UART11] = 0x1E790500,
74 [ASPEED_DEV_UART12] = 0x1E790600,
75 [ASPEED_DEV_UART13] = 0x1E790700,
76 [ASPEED_DEV_VUART] = 0x1E787000,
77 [ASPEED_DEV_I3C] = 0x1E7A0000,
78 [ASPEED_DEV_SDRAM] = 0x80000000,
79 };
80
81 #define ASPEED_A7MPCORE_ADDR 0x40460000
82
83 #define AST2600_MAX_IRQ 197
84
85 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
86 static const int aspeed_soc_ast2600_irqmap[] = {
87 [ASPEED_DEV_UART1] = 47,
88 [ASPEED_DEV_UART2] = 48,
89 [ASPEED_DEV_UART3] = 49,
90 [ASPEED_DEV_UART4] = 50,
91 [ASPEED_DEV_UART5] = 8,
92 [ASPEED_DEV_UART6] = 57,
93 [ASPEED_DEV_UART7] = 58,
94 [ASPEED_DEV_UART8] = 59,
95 [ASPEED_DEV_UART9] = 60,
96 [ASPEED_DEV_UART10] = 61,
97 [ASPEED_DEV_UART11] = 62,
98 [ASPEED_DEV_UART12] = 63,
99 [ASPEED_DEV_UART13] = 64,
100 [ASPEED_DEV_VUART] = 8,
101 [ASPEED_DEV_FMC] = 39,
102 [ASPEED_DEV_SDMC] = 0,
103 [ASPEED_DEV_SCU] = 12,
104 [ASPEED_DEV_ADC] = 78,
105 [ASPEED_DEV_XDMA] = 6,
106 [ASPEED_DEV_SDHCI] = 43,
107 [ASPEED_DEV_EHCI1] = 5,
108 [ASPEED_DEV_EHCI2] = 9,
109 [ASPEED_DEV_EMMC] = 15,
110 [ASPEED_DEV_GPIO] = 40,
111 [ASPEED_DEV_GPIO_1_8V] = 11,
112 [ASPEED_DEV_RTC] = 13,
113 [ASPEED_DEV_TIMER1] = 16,
114 [ASPEED_DEV_TIMER2] = 17,
115 [ASPEED_DEV_TIMER3] = 18,
116 [ASPEED_DEV_TIMER4] = 19,
117 [ASPEED_DEV_TIMER5] = 20,
118 [ASPEED_DEV_TIMER6] = 21,
119 [ASPEED_DEV_TIMER7] = 22,
120 [ASPEED_DEV_TIMER8] = 23,
121 [ASPEED_DEV_WDT] = 24,
122 [ASPEED_DEV_PWM] = 44,
123 [ASPEED_DEV_LPC] = 35,
124 [ASPEED_DEV_IBT] = 143,
125 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */
126 [ASPEED_DEV_ETH1] = 2,
127 [ASPEED_DEV_ETH2] = 3,
128 [ASPEED_DEV_HACE] = 4,
129 [ASPEED_DEV_ETH3] = 32,
130 [ASPEED_DEV_ETH4] = 33,
131 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
132 [ASPEED_DEV_DP] = 62,
133 [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */
134 };
135
136 static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev)
137 {
138 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
139
140 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]);
141 }
142
143 static void aspeed_soc_ast2600_init(Object *obj)
144 {
145 AspeedSoCState *s = ASPEED_SOC(obj);
146 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
147 int i;
148 char socname[8];
149 char typename[64];
150
151 if (sscanf(sc->name, "%7s", socname) != 1) {
152 g_assert_not_reached();
153 }
154
155 for (i = 0; i < sc->num_cpus; i++) {
156 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
157 }
158
159 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
160 object_initialize_child(obj, "scu", &s->scu, typename);
161 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
162 sc->silicon_rev);
163 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
164 "hw-strap1");
165 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
166 "hw-strap2");
167 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
168 "hw-prot-key");
169
170 object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
171 TYPE_A15MPCORE_PRIV);
172
173 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
174
175 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
176 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
177
178 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
179 object_initialize_child(obj, "adc", &s->adc, typename);
180
181 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
182 object_initialize_child(obj, "i2c", &s->i2c, typename);
183
184 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
185 object_initialize_child(obj, "fmc", &s->fmc, typename);
186
187 for (i = 0; i < sc->spis_num; i++) {
188 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
189 object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
190 }
191
192 for (i = 0; i < sc->ehcis_num; i++) {
193 object_initialize_child(obj, "ehci[*]", &s->ehci[i],
194 TYPE_PLATFORM_EHCI);
195 }
196
197 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
198 object_initialize_child(obj, "sdmc", &s->sdmc, typename);
199 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
200 "ram-size");
201 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
202 "max-ram-size");
203
204 for (i = 0; i < sc->wdts_num; i++) {
205 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
206 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
207 }
208
209 for (i = 0; i < sc->macs_num; i++) {
210 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
211 TYPE_FTGMAC100);
212
213 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII);
214 }
215
216 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname);
217 object_initialize_child(obj, "xdma", &s->xdma, typename);
218
219 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
220 object_initialize_child(obj, "gpio", &s->gpio, typename);
221
222 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname);
223 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename);
224
225 object_initialize_child(obj, "sd-controller", &s->sdhci,
226 TYPE_ASPEED_SDHCI);
227
228 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort);
229
230 /* Init sd card slot class here so that they're under the correct parent */
231 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
232 object_initialize_child(obj, "sd-controller.sdhci[*]",
233 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI);
234 }
235
236 object_initialize_child(obj, "emmc-controller", &s->emmc,
237 TYPE_ASPEED_SDHCI);
238
239 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort);
240
241 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0],
242 TYPE_SYSBUS_SDHCI);
243
244 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
245
246 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
247 object_initialize_child(obj, "hace", &s->hace, typename);
248
249 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
250
251 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
252 }
253
254 /*
255 * ASPEED ast2600 has 0xf as cluster ID
256 *
257 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register
258 */
259 static uint64_t aspeed_calc_affinity(int cpu)
260 {
261 return (0xf << ARM_AFF1_SHIFT) | cpu;
262 }
263
264 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
265 {
266 int i;
267 AspeedSoCState *s = ASPEED_SOC(dev);
268 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
269 Error *err = NULL;
270 qemu_irq irq;
271
272 /* IO space */
273 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOMEM],
274 ASPEED_SOC_IOMEM_SIZE);
275
276 /* Video engine stub */
277 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDEO],
278 0x1000);
279
280 /* eMMC Boot Controller stub */
281 create_unimplemented_device("aspeed.emmc-boot-controller",
282 sc->memmap[ASPEED_DEV_EMMC_BC],
283 0x1000);
284
285 /* CPU */
286 for (i = 0; i < sc->num_cpus; i++) {
287 if (sc->num_cpus > 1) {
288 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
289 ASPEED_A7MPCORE_ADDR, &error_abort);
290 }
291 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
292 aspeed_calc_affinity(i), &error_abort);
293
294 object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
295 &error_abort);
296
297 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
298 return;
299 }
300 }
301
302 /* A7MPCORE */
303 object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus,
304 &error_abort);
305 object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
306 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),
307 &error_abort);
308
309 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
310 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
311
312 for (i = 0; i < sc->num_cpus; i++) {
313 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
314 DeviceState *d = DEVICE(qemu_get_cpu(i));
315
316 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
317 sysbus_connect_irq(sbd, i, irq);
318 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
319 sysbus_connect_irq(sbd, i + sc->num_cpus, irq);
320 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
321 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq);
322 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
323 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq);
324 }
325
326 /* SRAM */
327 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
328 sc->sram_size, &err);
329 if (err) {
330 error_propagate(errp, err);
331 return;
332 }
333 memory_region_add_subregion(get_system_memory(),
334 sc->memmap[ASPEED_DEV_SRAM], &s->sram);
335
336 /* DPMCU */
337 create_unimplemented_device("aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU],
338 ASPEED_SOC_DPMCU_SIZE);
339
340 /* SCU */
341 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
342 return;
343 }
344 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
345
346 /* RTC */
347 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
348 return;
349 }
350 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
351 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
352 aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
353
354 /* Timer */
355 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
356 &error_abort);
357 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
358 return;
359 }
360 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
361 sc->memmap[ASPEED_DEV_TIMER1]);
362 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
363 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
364 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
365 }
366
367 /* ADC */
368 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
369 return;
370 }
371 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
372 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
373 aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
374
375 /* UART - attach an 8250 to the IO space as our UART */
376 serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
377 aspeed_soc_get_irq(s, s->uart_default), 38400,
378 serial_hd(0), DEVICE_LITTLE_ENDIAN);
379
380 /* I2C */
381 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
382 &error_abort);
383 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
384 return;
385 }
386 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
387 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
388 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
389 sc->irqmap[ASPEED_DEV_I2C] + i);
390 /* The AST2600 I2C controller has one IRQ per bus. */
391 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
392 }
393
394 /* FMC, The number of CS is set at the board level */
395 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
396 &error_abort);
397 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
398 return;
399 }
400 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
401 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
402 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
403 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
404 aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
405
406 /* SPI */
407 for (i = 0; i < sc->spis_num; i++) {
408 object_property_set_link(OBJECT(&s->spi[i]), "dram",
409 OBJECT(s->dram_mr), &error_abort);
410 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
411 return;
412 }
413 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
414 sc->memmap[ASPEED_DEV_SPI1 + i]);
415 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
416 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
417 }
418
419 /* EHCI */
420 for (i = 0; i < sc->ehcis_num; i++) {
421 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
422 return;
423 }
424 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
425 sc->memmap[ASPEED_DEV_EHCI1 + i]);
426 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
427 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
428 }
429
430 /* SDMC - SDRAM Memory Controller */
431 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
432 return;
433 }
434 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]);
435
436 /* Watch dog */
437 for (i = 0; i < sc->wdts_num; i++) {
438 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
439
440 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
441 &error_abort);
442 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
443 return;
444 }
445 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
446 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
447 }
448
449 /* Net */
450 for (i = 0; i < sc->macs_num; i++) {
451 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
452 &error_abort);
453 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
454 return;
455 }
456 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
457 sc->memmap[ASPEED_DEV_ETH1 + i]);
458 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
459 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
460
461 object_property_set_link(OBJECT(&s->mii[i]), "nic",
462 OBJECT(&s->ftgmac100[i]), &error_abort);
463 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) {
464 return;
465 }
466
467 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0,
468 sc->memmap[ASPEED_DEV_MII1 + i]);
469 }
470
471 /* XDMA */
472 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) {
473 return;
474 }
475 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
476 sc->memmap[ASPEED_DEV_XDMA]);
477 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
478 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA));
479
480 /* GPIO */
481 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
482 return;
483 }
484 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]);
485 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
486 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
487
488 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) {
489 return;
490 }
491 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
492 sc->memmap[ASPEED_DEV_GPIO_1_8V]);
493 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
494 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V));
495
496 /* SDHCI */
497 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
498 return;
499 }
500 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
501 sc->memmap[ASPEED_DEV_SDHCI]);
502 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
503 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
504
505 /* eMMC */
506 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) {
507 return;
508 }
509 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]);
510 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
511 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC));
512
513 /* LPC */
514 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
515 return;
516 }
517 sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
518
519 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */
520 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
521 aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
522
523 /*
524 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC.
525 *
526 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters
527 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ
528 * shared across the subdevices, and the shared IRQ output to the VIC is at
529 * offset 0.
530 */
531 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
532 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
533 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
534
535 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
536 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
537 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
538
539 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
540 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
541 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
542
543 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
544 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
545 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
546
547 /* HACE */
548 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),
549 &error_abort);
550 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
551 return;
552 }
553 sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]);
554 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
555 aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
556
557 /* I3C */
558 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) {
559 return;
560 }
561 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
562 for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
563 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
564 sc->irqmap[ASPEED_DEV_I3C] + i);
565 /* The AST2600 I3C controller has one IRQ per bus. */
566 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
567 }
568
569 /* Secure Boot Controller */
570 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
571 return;
572 }
573 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
574 }
575
576 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
577 {
578 DeviceClass *dc = DEVICE_CLASS(oc);
579 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
580
581 dc->realize = aspeed_soc_ast2600_realize;
582
583 sc->name = "ast2600-a3";
584 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
585 sc->silicon_rev = AST2600_A3_SILICON_REV;
586 sc->sram_size = 0x16400;
587 sc->spis_num = 2;
588 sc->ehcis_num = 2;
589 sc->wdts_num = 4;
590 sc->macs_num = 4;
591 sc->uarts_num = 13;
592 sc->irqmap = aspeed_soc_ast2600_irqmap;
593 sc->memmap = aspeed_soc_ast2600_memmap;
594 sc->num_cpus = 2;
595 sc->get_irq = aspeed_soc_ast2600_get_irq;
596 }
597
598 static const TypeInfo aspeed_soc_ast2600_type_info = {
599 .name = "ast2600-a3",
600 .parent = TYPE_ASPEED_SOC,
601 .instance_size = sizeof(AspeedSoCState),
602 .instance_init = aspeed_soc_ast2600_init,
603 .class_init = aspeed_soc_ast2600_class_init,
604 .class_size = sizeof(AspeedSoCClass),
605 };
606
607 static void aspeed_soc_register_types(void)
608 {
609 type_register_static(&aspeed_soc_ast2600_type_info);
610 };
611
612 type_init(aspeed_soc_register_types)
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