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aspeed: Parameterise number of MACs
[mirror_qemu.git] / hw / arm / aspeed_ast2600.c
1 /*
2 * ASPEED SoC 2600 family
3 *
4 * Copyright (c) 2016-2019, IBM Corporation.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 */
9
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "cpu.h"
13 #include "exec/address-spaces.h"
14 #include "hw/misc/unimp.h"
15 #include "hw/arm/aspeed_soc.h"
16 #include "hw/char/serial.h"
17 #include "qemu/log.h"
18 #include "qemu/module.h"
19 #include "qemu/error-report.h"
20 #include "hw/i2c/aspeed_i2c.h"
21 #include "net/net.h"
22 #include "sysemu/sysemu.h"
23
24 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
25
26 static const hwaddr aspeed_soc_ast2600_memmap[] = {
27 [ASPEED_SRAM] = 0x10000000,
28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
29 [ASPEED_IOMEM] = 0x1E600000,
30 [ASPEED_PWM] = 0x1E610000,
31 [ASPEED_FMC] = 0x1E620000,
32 [ASPEED_SPI1] = 0x1E630000,
33 [ASPEED_SPI2] = 0x1E641000,
34 [ASPEED_ETH1] = 0x1E660000,
35 [ASPEED_ETH3] = 0x1E670000,
36 [ASPEED_ETH2] = 0x1E680000,
37 [ASPEED_ETH4] = 0x1E690000,
38 [ASPEED_VIC] = 0x1E6C0000,
39 [ASPEED_SDMC] = 0x1E6E0000,
40 [ASPEED_SCU] = 0x1E6E2000,
41 [ASPEED_XDMA] = 0x1E6E7000,
42 [ASPEED_ADC] = 0x1E6E9000,
43 [ASPEED_SDHCI] = 0x1E740000,
44 [ASPEED_GPIO] = 0x1E780000,
45 [ASPEED_GPIO_1_8V] = 0x1E780800,
46 [ASPEED_RTC] = 0x1E781000,
47 [ASPEED_TIMER1] = 0x1E782000,
48 [ASPEED_WDT] = 0x1E785000,
49 [ASPEED_LPC] = 0x1E789000,
50 [ASPEED_IBT] = 0x1E789140,
51 [ASPEED_I2C] = 0x1E78A000,
52 [ASPEED_UART1] = 0x1E783000,
53 [ASPEED_UART5] = 0x1E784000,
54 [ASPEED_VUART] = 0x1E787000,
55 [ASPEED_SDRAM] = 0x80000000,
56 };
57
58 #define ASPEED_A7MPCORE_ADDR 0x40460000
59
60 #define ASPEED_SOC_AST2600_MAX_IRQ 128
61
62 static const int aspeed_soc_ast2600_irqmap[] = {
63 [ASPEED_UART1] = 47,
64 [ASPEED_UART2] = 48,
65 [ASPEED_UART3] = 49,
66 [ASPEED_UART4] = 50,
67 [ASPEED_UART5] = 8,
68 [ASPEED_VUART] = 8,
69 [ASPEED_FMC] = 39,
70 [ASPEED_SDMC] = 0,
71 [ASPEED_SCU] = 12,
72 [ASPEED_ADC] = 78,
73 [ASPEED_XDMA] = 6,
74 [ASPEED_SDHCI] = 43,
75 [ASPEED_GPIO] = 40,
76 [ASPEED_GPIO_1_8V] = 11,
77 [ASPEED_RTC] = 13,
78 [ASPEED_TIMER1] = 16,
79 [ASPEED_TIMER2] = 17,
80 [ASPEED_TIMER3] = 18,
81 [ASPEED_TIMER4] = 19,
82 [ASPEED_TIMER5] = 20,
83 [ASPEED_TIMER6] = 21,
84 [ASPEED_TIMER7] = 22,
85 [ASPEED_TIMER8] = 23,
86 [ASPEED_WDT] = 24,
87 [ASPEED_PWM] = 44,
88 [ASPEED_LPC] = 35,
89 [ASPEED_IBT] = 35, /* LPC */
90 [ASPEED_I2C] = 110, /* 110 -> 125 */
91 [ASPEED_ETH1] = 2,
92 [ASPEED_ETH2] = 3,
93 [ASPEED_ETH3] = 32,
94 [ASPEED_ETH4] = 33,
95
96 };
97
98 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
99 {
100 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
101
102 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]);
103 }
104
105 static void aspeed_soc_ast2600_init(Object *obj)
106 {
107 AspeedSoCState *s = ASPEED_SOC(obj);
108 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
109 int i;
110 char socname[8];
111 char typename[64];
112
113 if (sscanf(sc->name, "%7s", socname) != 1) {
114 g_assert_not_reached();
115 }
116
117 for (i = 0; i < sc->num_cpus; i++) {
118 object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
119 sizeof(s->cpu[i]), sc->cpu_type,
120 &error_abort, NULL);
121 }
122
123 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
124 sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
125 typename);
126 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
127 sc->silicon_rev);
128 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
129 "hw-strap1", &error_abort);
130 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
131 "hw-strap2", &error_abort);
132 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
133 "hw-prot-key", &error_abort);
134
135 sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore,
136 sizeof(s->a7mpcore), TYPE_A15MPCORE_PRIV);
137
138 sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
139 TYPE_ASPEED_RTC);
140
141 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
142 sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
143 sizeof(s->timerctrl), typename);
144 object_property_add_const_link(OBJECT(&s->timerctrl), "scu",
145 OBJECT(&s->scu), &error_abort);
146
147 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
148 sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
149 typename);
150
151 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
152 sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
153 typename);
154 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
155 &error_abort);
156 object_property_add_alias(obj, "dram", OBJECT(&s->fmc), "dram",
157 &error_abort);
158
159 for (i = 0; i < sc->spis_num; i++) {
160 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
161 sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
162 sizeof(s->spi[i]), typename);
163 }
164
165 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
166 sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
167 typename);
168 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
169 "ram-size", &error_abort);
170 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
171 "max-ram-size", &error_abort);
172
173 for (i = 0; i < sc->wdts_num; i++) {
174 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
175 sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
176 sizeof(s->wdt[i]), typename);
177 object_property_add_const_link(OBJECT(&s->wdt[i]), "scu",
178 OBJECT(&s->scu), &error_abort);
179 }
180
181 for (i = 0; i < sc->macs_num; i++) {
182 sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
183 sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
184 }
185
186 sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
187 TYPE_ASPEED_XDMA);
188
189 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
190 sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio),
191 typename);
192
193 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname);
194 sysbus_init_child_obj(obj, "gpio_1_8v", OBJECT(&s->gpio_1_8v),
195 sizeof(s->gpio_1_8v), typename);
196
197 sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),
198 TYPE_ASPEED_SDHCI);
199
200 /* Init sd card slot class here so that they're under the correct parent */
201 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
202 sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),
203 sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
204 }
205 }
206
207 /*
208 * ASPEED ast2600 has 0xf as cluster ID
209 *
210 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html
211 */
212 static uint64_t aspeed_calc_affinity(int cpu)
213 {
214 return (0xf << ARM_AFF1_SHIFT) | cpu;
215 }
216
217 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
218 {
219 int i;
220 AspeedSoCState *s = ASPEED_SOC(dev);
221 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
222 Error *err = NULL, *local_err = NULL;
223 qemu_irq irq;
224
225 /* IO space */
226 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM],
227 ASPEED_SOC_IOMEM_SIZE);
228
229 if (s->num_cpus > sc->num_cpus) {
230 warn_report("%s: invalid number of CPUs %d, using default %d",
231 sc->name, s->num_cpus, sc->num_cpus);
232 s->num_cpus = sc->num_cpus;
233 }
234
235 /* CPU */
236 for (i = 0; i < s->num_cpus; i++) {
237 object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC,
238 "psci-conduit", &error_abort);
239 if (s->num_cpus > 1) {
240 object_property_set_int(OBJECT(&s->cpu[i]),
241 ASPEED_A7MPCORE_ADDR,
242 "reset-cbar", &error_abort);
243 }
244 object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinity(i),
245 "mp-affinity", &error_abort);
246
247 /*
248 * TODO: the secondary CPUs are started and a boot helper
249 * is needed when using -kernel
250 */
251
252 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
253 if (err) {
254 error_propagate(errp, err);
255 return;
256 }
257 }
258
259 /* A7MPCORE */
260 object_property_set_int(OBJECT(&s->a7mpcore), s->num_cpus, "num-cpu",
261 &error_abort);
262 object_property_set_int(OBJECT(&s->a7mpcore),
263 ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL,
264 "num-irq", &error_abort);
265
266 object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
267 &error_abort);
268 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
269
270 for (i = 0; i < s->num_cpus; i++) {
271 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
272 DeviceState *d = DEVICE(qemu_get_cpu(i));
273
274 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
275 sysbus_connect_irq(sbd, i, irq);
276 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
277 sysbus_connect_irq(sbd, i + s->num_cpus, irq);
278 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
279 sysbus_connect_irq(sbd, i + 2 * s->num_cpus, irq);
280 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
281 sysbus_connect_irq(sbd, i + 3 * s->num_cpus, irq);
282 }
283
284 /* SRAM */
285 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
286 sc->sram_size, &err);
287 if (err) {
288 error_propagate(errp, err);
289 return;
290 }
291 memory_region_add_subregion(get_system_memory(),
292 sc->memmap[ASPEED_SRAM], &s->sram);
293
294 /* SCU */
295 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
296 if (err) {
297 error_propagate(errp, err);
298 return;
299 }
300 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);
301
302 /* RTC */
303 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
304 if (err) {
305 error_propagate(errp, err);
306 return;
307 }
308 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]);
309 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
310 aspeed_soc_get_irq(s, ASPEED_RTC));
311
312 /* Timer */
313 object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
314 if (err) {
315 error_propagate(errp, err);
316 return;
317 }
318 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
319 sc->memmap[ASPEED_TIMER1]);
320 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
321 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
322 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
323 }
324
325 /* UART - attach an 8250 to the IO space as our UART5 */
326 if (serial_hd(0)) {
327 qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
328 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2,
329 uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
330 }
331
332 /* I2C */
333 object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
334 if (err) {
335 error_propagate(errp, err);
336 return;
337 }
338 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]);
339 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
340 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
341 sc->irqmap[ASPEED_I2C] + i);
342 /*
343 * The AST2600 SoC has one IRQ per I2C bus. Skip the common
344 * IRQ (AST2400 and AST2500) and connect all bussses.
345 */
346 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq);
347 }
348
349 /* FMC, The number of CS is set at the board level */
350 object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM],
351 "sdram-base", &err);
352 if (err) {
353 error_propagate(errp, err);
354 return;
355 }
356 object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
357 if (err) {
358 error_propagate(errp, err);
359 return;
360 }
361 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]);
362 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
363 s->fmc.ctrl->flash_window_base);
364 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
365 aspeed_soc_get_irq(s, ASPEED_FMC));
366
367 /* SPI */
368 for (i = 0; i < sc->spis_num; i++) {
369 object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
370 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
371 &local_err);
372 error_propagate(&err, local_err);
373 if (err) {
374 error_propagate(errp, err);
375 return;
376 }
377 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
378 sc->memmap[ASPEED_SPI1 + i]);
379 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
380 s->spi[i].ctrl->flash_window_base);
381 }
382
383 /* SDMC - SDRAM Memory Controller */
384 object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
385 if (err) {
386 error_propagate(errp, err);
387 return;
388 }
389 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]);
390
391 /* Watch dog */
392 for (i = 0; i < sc->wdts_num; i++) {
393 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
394
395 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
396 if (err) {
397 error_propagate(errp, err);
398 return;
399 }
400 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
401 sc->memmap[ASPEED_WDT] + i * awc->offset);
402 }
403
404 /* Net */
405 for (i = 0; i < nb_nics && i < sc->macs_num; i++) {
406 qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
407 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
408 &err);
409 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
410 &local_err);
411 error_propagate(&err, local_err);
412 if (err) {
413 error_propagate(errp, err);
414 return;
415 }
416 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
417 sc->memmap[ASPEED_ETH1 + i]);
418 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
419 aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
420 }
421
422 /* XDMA */
423 object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
424 if (err) {
425 error_propagate(errp, err);
426 return;
427 }
428 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
429 sc->memmap[ASPEED_XDMA]);
430 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
431 aspeed_soc_get_irq(s, ASPEED_XDMA));
432
433 /* GPIO */
434 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
435 if (err) {
436 error_propagate(errp, err);
437 return;
438 }
439 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]);
440 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
441 aspeed_soc_get_irq(s, ASPEED_GPIO));
442
443 object_property_set_bool(OBJECT(&s->gpio_1_8v), true, "realized", &err);
444 if (err) {
445 error_propagate(errp, err);
446 return;
447 }
448 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
449 sc->memmap[ASPEED_GPIO_1_8V]);
450 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
451 aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V));
452
453 /* SDHCI */
454 object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
455 if (err) {
456 error_propagate(errp, err);
457 return;
458 }
459 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
460 sc->memmap[ASPEED_SDHCI]);
461 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
462 aspeed_soc_get_irq(s, ASPEED_SDHCI));
463 }
464
465 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
466 {
467 DeviceClass *dc = DEVICE_CLASS(oc);
468 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
469
470 dc->realize = aspeed_soc_ast2600_realize;
471
472 sc->name = "ast2600-a0";
473 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
474 sc->silicon_rev = AST2600_A0_SILICON_REV;
475 sc->sram_size = 0x10000;
476 sc->spis_num = 2;
477 sc->wdts_num = 4;
478 sc->macs_num = 4;
479 sc->irqmap = aspeed_soc_ast2600_irqmap;
480 sc->memmap = aspeed_soc_ast2600_memmap;
481 sc->num_cpus = 2;
482 }
483
484 static const TypeInfo aspeed_soc_ast2600_type_info = {
485 .name = "ast2600-a0",
486 .parent = TYPE_ASPEED_SOC,
487 .instance_size = sizeof(AspeedSoCState),
488 .instance_init = aspeed_soc_ast2600_init,
489 .class_init = aspeed_soc_ast2600_class_init,
490 .class_size = sizeof(AspeedSoCClass),
491 };
492
493 static void aspeed_soc_register_types(void)
494 {
495 type_register_static(&aspeed_soc_ast2600_type_info);
496 };
497
498 type_init(aspeed_soc_register_types)
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