hw/arm/aspeed_soc.c

   1 /*
   2  * ASPEED SoC family
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  * Jeremy Kerr <jk@ozlabs.org>
   6  *
   7  * Copyright 2016 IBM Corp.
   8  *
   9  * This code is licensed under the GPL version 2 or later.  See
  10  * the COPYING file in the top-level directory.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qapi/error.h"
  15 #include "cpu.h"
  16 #include "exec/address-spaces.h"
  17 #include "hw/misc/unimp.h"
  18 #include "hw/arm/aspeed_soc.h"
  19 #include "hw/char/serial.h"
  20 #include "qemu/log.h"
  21 #include "qemu/module.h"
  22 #include "hw/i2c/aspeed_i2c.h"
  23 #include "net/net.h"
  24
  25 #define ASPEED_SOC_UART_5_BASE      0x00184000
  26 #define ASPEED_SOC_IOMEM_SIZE       0x00200000
  27 #define ASPEED_SOC_IOMEM_BASE       0x1E600000
  28 #define ASPEED_SOC_FMC_BASE         0x1E620000
  29 #define ASPEED_SOC_SPI_BASE         0x1E630000
  30 #define ASPEED_SOC_SPI2_BASE        0x1E631000
  31 #define ASPEED_SOC_VIC_BASE         0x1E6C0000
  32 #define ASPEED_SOC_SDMC_BASE        0x1E6E0000
  33 #define ASPEED_SOC_SCU_BASE         0x1E6E2000
  34 #define ASPEED_SOC_SRAM_BASE        0x1E720000
  35 #define ASPEED_SOC_TIMER_BASE       0x1E782000
  36 #define ASPEED_SOC_WDT_BASE         0x1E785000
  37 #define ASPEED_SOC_I2C_BASE         0x1E78A000
  38 #define ASPEED_SOC_ETH1_BASE        0x1E660000
  39 #define ASPEED_SOC_ETH2_BASE        0x1E680000
  40
  41 static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
  42 static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
  43
  44 #define AST2400_SDRAM_BASE       0x40000000
  45 #define AST2500_SDRAM_BASE       0x80000000
  46
  47 static const hwaddr aspeed_soc_ast2400_spi_bases[] = { ASPEED_SOC_SPI_BASE };
  48 static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };
  49
  50 static const hwaddr aspeed_soc_ast2500_spi_bases[] = { ASPEED_SOC_SPI_BASE,
  51                                                        ASPEED_SOC_SPI2_BASE};
  52 static const char *aspeed_soc_ast2500_typenames[] = {
  53     "aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };
  54
  55 static const AspeedSoCInfo aspeed_socs[] = {
  56     {
  57         .name         = "ast2400-a0",
  58         .cpu_type     = ARM_CPU_TYPE_NAME("arm926"),
  59         .silicon_rev  = AST2400_A0_SILICON_REV,
  60         .sdram_base   = AST2400_SDRAM_BASE,
  61         .sram_size    = 0x8000,
  62         .spis_num     = 1,
  63         .spi_bases    = aspeed_soc_ast2400_spi_bases,
  64         .fmc_typename = "aspeed.smc.fmc",
  65         .spi_typename = aspeed_soc_ast2400_typenames,
  66         .wdts_num     = 2,
  67     }, {
  68         .name         = "ast2400-a1",
  69         .cpu_type     = ARM_CPU_TYPE_NAME("arm926"),
  70         .silicon_rev  = AST2400_A1_SILICON_REV,
  71         .sdram_base   = AST2400_SDRAM_BASE,
  72         .sram_size    = 0x8000,
  73         .spis_num     = 1,
  74         .spi_bases    = aspeed_soc_ast2400_spi_bases,
  75         .fmc_typename = "aspeed.smc.fmc",
  76         .spi_typename = aspeed_soc_ast2400_typenames,
  77         .wdts_num     = 2,
  78     }, {
  79         .name         = "ast2400",
  80         .cpu_type     = ARM_CPU_TYPE_NAME("arm926"),
  81         .silicon_rev  = AST2400_A0_SILICON_REV,
  82         .sdram_base   = AST2400_SDRAM_BASE,
  83         .sram_size    = 0x8000,
  84         .spis_num     = 1,
  85         .spi_bases    = aspeed_soc_ast2400_spi_bases,
  86         .fmc_typename = "aspeed.smc.fmc",
  87         .spi_typename = aspeed_soc_ast2400_typenames,
  88         .wdts_num     = 2,
  89     }, {
  90         .name         = "ast2500-a1",
  91         .cpu_type     = ARM_CPU_TYPE_NAME("arm1176"),
  92         .silicon_rev  = AST2500_A1_SILICON_REV,
  93         .sdram_base   = AST2500_SDRAM_BASE,
  94         .sram_size    = 0x9000,
  95         .spis_num     = 2,
  96         .spi_bases    = aspeed_soc_ast2500_spi_bases,
  97         .fmc_typename = "aspeed.smc.ast2500-fmc",
  98         .spi_typename = aspeed_soc_ast2500_typenames,
  99         .wdts_num     = 3,
 100     },
 101 };
 102
 103 static void aspeed_soc_init(Object *obj)
 104 {
 105     AspeedSoCState *s = ASPEED_SOC(obj);
 106     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 107     int i;
 108
 109     object_initialize_child(obj, "cpu", OBJECT(&s->cpu), sizeof(s->cpu),
 110                             sc->info->cpu_type, &error_abort, NULL);
 111
 112     sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
 113                           TYPE_ASPEED_SCU);
 114     qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
 115                          sc->info->silicon_rev);
 116     object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
 117                               "hw-strap1", &error_abort);
 118     object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
 119                               "hw-strap2", &error_abort);
 120     object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
 121                               "hw-prot-key", &error_abort);
 122
 123     sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic),
 124                           TYPE_ASPEED_VIC);
 125
 126     sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
 127                           sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
 128     object_property_add_const_link(OBJECT(&s->timerctrl), "scu",
 129                                    OBJECT(&s->scu), &error_abort);
 130
 131     sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
 132                           TYPE_ASPEED_I2C);
 133
 134     sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
 135                           sc->info->fmc_typename);
 136     object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
 137                               &error_abort);
 138
 139     for (i = 0; i < sc->info->spis_num; i++) {
 140         sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
 141                               sizeof(s->spi[i]), sc->info->spi_typename[i]);
 142     }
 143
 144     sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
 145                           TYPE_ASPEED_SDMC);
 146     qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",
 147                          sc->info->silicon_rev);
 148     object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
 149                               "ram-size", &error_abort);
 150     object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
 151                               "max-ram-size", &error_abort);
 152
 153     for (i = 0; i < sc->info->wdts_num; i++) {
 154         sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
 155                               sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
 156         qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev",
 157                                     sc->info->silicon_rev);
 158     }
 159
 160     sysbus_init_child_obj(obj, "ftgmac100", OBJECT(&s->ftgmac100),
 161                           sizeof(s->ftgmac100), TYPE_FTGMAC100);
 162 }
 163
 164 static void aspeed_soc_realize(DeviceState *dev, Error **errp)
 165 {
 166     int i;
 167     AspeedSoCState *s = ASPEED_SOC(dev);
 168     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 169     Error *err = NULL, *local_err = NULL;
 170
 171     /* IO space */
 172     create_unimplemented_device("aspeed_soc.io",
 173                                 ASPEED_SOC_IOMEM_BASE, ASPEED_SOC_IOMEM_SIZE);
 174
 175     /* CPU */
 176     object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
 177     if (err) {
 178         error_propagate(errp, err);
 179         return;
 180     }
 181
 182     /* SRAM */
 183     memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
 184                            sc->info->sram_size, &err);
 185     if (err) {
 186         error_propagate(errp, err);
 187         return;
 188     }
 189     memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE,
 190                                 &s->sram);
 191
 192     /* SCU */
 193     object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
 194     if (err) {
 195         error_propagate(errp, err);
 196         return;
 197     }
 198     sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE);
 199
 200     /* VIC */
 201     object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
 202     if (err) {
 203         error_propagate(errp, err);
 204         return;
 205     }
 206     sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, ASPEED_SOC_VIC_BASE);
 207     sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
 208                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
 209     sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
 210                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
 211
 212     /* Timer */
 213     object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
 214     if (err) {
 215         error_propagate(errp, err);
 216         return;
 217     }
 218     sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BASE);
 219     for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {
 220         qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]);
 221         sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
 222     }
 223
 224     /* UART - attach an 8250 to the IO space as our UART5 */
 225     if (serial_hd(0)) {
 226         qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
 227         serial_mm_init(get_system_memory(),
 228                        ASPEED_SOC_IOMEM_BASE + ASPEED_SOC_UART_5_BASE, 2,
 229                        uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
 230     }
 231
 232     /* I2C */
 233     object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
 234     if (err) {
 235         error_propagate(errp, err);
 236         return;
 237     }
 238     sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE);
 239     sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
 240                        qdev_get_gpio_in(DEVICE(&s->vic), 12));
 241
 242     /* FMC, The number of CS is set at the board level */
 243     object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
 244     if (err) {
 245         error_propagate(errp, err);
 246         return;
 247     }
 248     sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, ASPEED_SOC_FMC_BASE);
 249     sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
 250                     s->fmc.ctrl->flash_window_base);
 251     sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
 252                        qdev_get_gpio_in(DEVICE(&s->vic), 19));
 253
 254     /* SPI */
 255     for (i = 0; i < sc->info->spis_num; i++) {
 256         object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
 257         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
 258                                  &local_err);
 259         error_propagate(&err, local_err);
 260         if (err) {
 261             error_propagate(errp, err);
 262             return;
 263         }
 264         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, sc->info->spi_bases[i]);
 265         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
 266                         s->spi[i].ctrl->flash_window_base);
 267     }
 268
 269     /* SDMC - SDRAM Memory Controller */
 270     object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
 271     if (err) {
 272         error_propagate(errp, err);
 273         return;
 274     }
 275     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
 276
 277     /* Watch dog */
 278     for (i = 0; i < sc->info->wdts_num; i++) {
 279         object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
 280         if (err) {
 281             error_propagate(errp, err);
 282             return;
 283         }
 284         sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
 285                         ASPEED_SOC_WDT_BASE + i * 0x20);
 286     }
 287
 288     /* Net */
 289     qdev_set_nic_properties(DEVICE(&s->ftgmac100), &nd_table[0]);
 290     object_property_set_bool(OBJECT(&s->ftgmac100), true, "aspeed", &err);
 291     object_property_set_bool(OBJECT(&s->ftgmac100), true, "realized",
 292                              &local_err);
 293     error_propagate(&err, local_err);
 294     if (err) {
 295         error_propagate(errp, err);
 296         return;
 297     }
 298     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0, ASPEED_SOC_ETH1_BASE);
 299     sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0,
 300                        qdev_get_gpio_in(DEVICE(&s->vic), 2));
 301 }
 302
 303 static void aspeed_soc_class_init(ObjectClass *oc, void *data)
 304 {
 305     DeviceClass *dc = DEVICE_CLASS(oc);
 306     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
 307
 308     sc->info = (AspeedSoCInfo *) data;
 309     dc->realize = aspeed_soc_realize;
 310     /* Reason: Uses serial_hds and nd_table in realize() directly */
 311     dc->user_creatable = false;
 312 }
 313
 314 static const TypeInfo aspeed_soc_type_info = {
 315     .name           = TYPE_ASPEED_SOC,
 316     .parent         = TYPE_DEVICE,
 317     .instance_init  = aspeed_soc_init,
 318     .instance_size  = sizeof(AspeedSoCState),
 319     .class_size     = sizeof(AspeedSoCClass),
 320     .abstract       = true,
 321 };
 322
 323 static void aspeed_soc_register_types(void)
 324 {
 325     int i;
 326
 327     type_register_static(&aspeed_soc_type_info);
 328     for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) {
 329         TypeInfo ti = {
 330             .name       = aspeed_socs[i].name,
 331             .parent     = TYPE_ASPEED_SOC,
 332             .class_init = aspeed_soc_class_init,
 333             .class_data = (void *) &aspeed_socs[i],
 334         };
 335         type_register(&ti);
 336     }
 337 }
 338
 339 type_init(aspeed_soc_register_types)