]> git.proxmox.com Git - mirror_qemu.git/blob - hw/arm/aspeed_soc.c
projects / mirror_qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge remote-tracking branch 'remotes/armbru/tags/pull-qom-2020-05-15' into staging
[mirror_qemu.git] / hw / arm / aspeed_soc.c
1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
6 *
7 * Copyright 2016 IBM Corp.
8 *
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
11 */
12
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "cpu.h"
16 #include "exec/address-spaces.h"
17 #include "hw/misc/unimp.h"
18 #include "hw/arm/aspeed_soc.h"
19 #include "hw/char/serial.h"
20 #include "qemu/log.h"
21 #include "qemu/module.h"
22 #include "qemu/error-report.h"
23 #include "hw/i2c/aspeed_i2c.h"
24 #include "net/net.h"
25 #include "sysemu/sysemu.h"
26
27 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
28
29 static const hwaddr aspeed_soc_ast2400_memmap[] = {
30 [ASPEED_IOMEM] = 0x1E600000,
31 [ASPEED_FMC] = 0x1E620000,
32 [ASPEED_SPI1] = 0x1E630000,
33 [ASPEED_EHCI1] = 0x1E6A1000,
34 [ASPEED_VIC] = 0x1E6C0000,
35 [ASPEED_SDMC] = 0x1E6E0000,
36 [ASPEED_SCU] = 0x1E6E2000,
37 [ASPEED_XDMA] = 0x1E6E7000,
38 [ASPEED_VIDEO] = 0x1E700000,
39 [ASPEED_ADC] = 0x1E6E9000,
40 [ASPEED_SRAM] = 0x1E720000,
41 [ASPEED_SDHCI] = 0x1E740000,
42 [ASPEED_GPIO] = 0x1E780000,
43 [ASPEED_RTC] = 0x1E781000,
44 [ASPEED_TIMER1] = 0x1E782000,
45 [ASPEED_WDT] = 0x1E785000,
46 [ASPEED_PWM] = 0x1E786000,
47 [ASPEED_LPC] = 0x1E789000,
48 [ASPEED_IBT] = 0x1E789140,
49 [ASPEED_I2C] = 0x1E78A000,
50 [ASPEED_ETH1] = 0x1E660000,
51 [ASPEED_ETH2] = 0x1E680000,
52 [ASPEED_UART1] = 0x1E783000,
53 [ASPEED_UART5] = 0x1E784000,
54 [ASPEED_VUART] = 0x1E787000,
55 [ASPEED_SDRAM] = 0x40000000,
56 };
57
58 static const hwaddr aspeed_soc_ast2500_memmap[] = {
59 [ASPEED_IOMEM] = 0x1E600000,
60 [ASPEED_FMC] = 0x1E620000,
61 [ASPEED_SPI1] = 0x1E630000,
62 [ASPEED_SPI2] = 0x1E631000,
63 [ASPEED_EHCI1] = 0x1E6A1000,
64 [ASPEED_EHCI2] = 0x1E6A3000,
65 [ASPEED_VIC] = 0x1E6C0000,
66 [ASPEED_SDMC] = 0x1E6E0000,
67 [ASPEED_SCU] = 0x1E6E2000,
68 [ASPEED_XDMA] = 0x1E6E7000,
69 [ASPEED_ADC] = 0x1E6E9000,
70 [ASPEED_VIDEO] = 0x1E700000,
71 [ASPEED_SRAM] = 0x1E720000,
72 [ASPEED_SDHCI] = 0x1E740000,
73 [ASPEED_GPIO] = 0x1E780000,
74 [ASPEED_RTC] = 0x1E781000,
75 [ASPEED_TIMER1] = 0x1E782000,
76 [ASPEED_WDT] = 0x1E785000,
77 [ASPEED_PWM] = 0x1E786000,
78 [ASPEED_LPC] = 0x1E789000,
79 [ASPEED_IBT] = 0x1E789140,
80 [ASPEED_I2C] = 0x1E78A000,
81 [ASPEED_ETH1] = 0x1E660000,
82 [ASPEED_ETH2] = 0x1E680000,
83 [ASPEED_UART1] = 0x1E783000,
84 [ASPEED_UART5] = 0x1E784000,
85 [ASPEED_VUART] = 0x1E787000,
86 [ASPEED_SDRAM] = 0x80000000,
87 };
88
89 static const int aspeed_soc_ast2400_irqmap[] = {
90 [ASPEED_UART1] = 9,
91 [ASPEED_UART2] = 32,
92 [ASPEED_UART3] = 33,
93 [ASPEED_UART4] = 34,
94 [ASPEED_UART5] = 10,
95 [ASPEED_VUART] = 8,
96 [ASPEED_FMC] = 19,
97 [ASPEED_EHCI1] = 5,
98 [ASPEED_EHCI2] = 13,
99 [ASPEED_SDMC] = 0,
100 [ASPEED_SCU] = 21,
101 [ASPEED_ADC] = 31,
102 [ASPEED_GPIO] = 20,
103 [ASPEED_RTC] = 22,
104 [ASPEED_TIMER1] = 16,
105 [ASPEED_TIMER2] = 17,
106 [ASPEED_TIMER3] = 18,
107 [ASPEED_TIMER4] = 35,
108 [ASPEED_TIMER5] = 36,
109 [ASPEED_TIMER6] = 37,
110 [ASPEED_TIMER7] = 38,
111 [ASPEED_TIMER8] = 39,
112 [ASPEED_WDT] = 27,
113 [ASPEED_PWM] = 28,
114 [ASPEED_LPC] = 8,
115 [ASPEED_IBT] = 8, /* LPC */
116 [ASPEED_I2C] = 12,
117 [ASPEED_ETH1] = 2,
118 [ASPEED_ETH2] = 3,
119 [ASPEED_XDMA] = 6,
120 [ASPEED_SDHCI] = 26,
121 };
122
123 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
124
125 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
126 {
127 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
128
129 return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[ctrl]);
130 }
131
132 static void aspeed_soc_init(Object *obj)
133 {
134 AspeedSoCState *s = ASPEED_SOC(obj);
135 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
136 int i;
137 char socname[8];
138 char typename[64];
139
140 if (sscanf(sc->name, "%7s", socname) != 1) {
141 g_assert_not_reached();
142 }
143
144 for (i = 0; i < sc->num_cpus; i++) {
145 object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
146 sizeof(s->cpu[i]), sc->cpu_type,
147 &error_abort, NULL);
148 }
149
150 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
151 sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
152 typename);
153 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
154 sc->silicon_rev);
155 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
156 "hw-strap1");
157 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
158 "hw-strap2");
159 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
160 "hw-prot-key");
161
162 sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic),
163 TYPE_ASPEED_VIC);
164
165 sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
166 TYPE_ASPEED_RTC);
167
168 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
169 sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
170 sizeof(s->timerctrl), typename);
171
172 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
173 sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
174 typename);
175
176 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
177 sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
178 typename);
179 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs");
180
181 for (i = 0; i < sc->spis_num; i++) {
182 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
183 sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
184 sizeof(s->spi[i]), typename);
185 }
186
187 for (i = 0; i < sc->ehcis_num; i++) {
188 sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]),
189 sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI);
190 }
191
192 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
193 sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
194 typename);
195 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
196 "ram-size");
197 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
198 "max-ram-size");
199
200 for (i = 0; i < sc->wdts_num; i++) {
201 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
202 sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
203 sizeof(s->wdt[i]), typename);
204 }
205
206 for (i = 0; i < sc->macs_num; i++) {
207 sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
208 sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
209 }
210
211 sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
212 TYPE_ASPEED_XDMA);
213
214 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
215 sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio),
216 typename);
217
218 sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),
219 TYPE_ASPEED_SDHCI);
220
221 object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
222
223 /* Init sd card slot class here so that they're under the correct parent */
224 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
225 sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),
226 sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
227 }
228 }
229
230 static void aspeed_soc_realize(DeviceState *dev, Error **errp)
231 {
232 int i;
233 AspeedSoCState *s = ASPEED_SOC(dev);
234 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
235 Error *err = NULL, *local_err = NULL;
236
237 /* IO space */
238 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM],
239 ASPEED_SOC_IOMEM_SIZE);
240
241 /* Video engine stub */
242 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO],
243 0x1000);
244
245 if (s->num_cpus > sc->num_cpus) {
246 warn_report("%s: invalid number of CPUs %d, using default %d",
247 sc->name, s->num_cpus, sc->num_cpus);
248 s->num_cpus = sc->num_cpus;
249 }
250
251 /* CPU */
252 for (i = 0; i < s->num_cpus; i++) {
253 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
254 if (err) {
255 error_propagate(errp, err);
256 return;
257 }
258 }
259
260 /* SRAM */
261 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
262 sc->sram_size, &err);
263 if (err) {
264 error_propagate(errp, err);
265 return;
266 }
267 memory_region_add_subregion(get_system_memory(),
268 sc->memmap[ASPEED_SRAM], &s->sram);
269
270 /* SCU */
271 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
272 if (err) {
273 error_propagate(errp, err);
274 return;
275 }
276 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);
277
278 /* VIC */
279 object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
280 if (err) {
281 error_propagate(errp, err);
282 return;
283 }
284 sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_VIC]);
285 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
286 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
287 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
288 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
289
290 /* RTC */
291 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
292 if (err) {
293 error_propagate(errp, err);
294 return;
295 }
296 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]);
297 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
298 aspeed_soc_get_irq(s, ASPEED_RTC));
299
300 /* Timer */
301 object_property_set_link(OBJECT(&s->timerctrl),
302 OBJECT(&s->scu), "scu", &error_abort);
303 object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
304 if (err) {
305 error_propagate(errp, err);
306 return;
307 }
308 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
309 sc->memmap[ASPEED_TIMER1]);
310 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
311 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
312 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
313 }
314
315 /* UART - attach an 8250 to the IO space as our UART5 */
316 if (serial_hd(0)) {
317 qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
318 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2,
319 uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
320 }
321
322 /* I2C */
323 object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err);
324 if (err) {
325 error_propagate(errp, err);
326 return;
327 }
328 object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
329 if (err) {
330 error_propagate(errp, err);
331 return;
332 }
333 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]);
334 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
335 aspeed_soc_get_irq(s, ASPEED_I2C));
336
337 /* FMC, The number of CS is set at the board level */
338 object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err);
339 if (err) {
340 error_propagate(errp, err);
341 return;
342 }
343 object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM],
344 "sdram-base", &err);
345 if (err) {
346 error_propagate(errp, err);
347 return;
348 }
349 object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
350 if (err) {
351 error_propagate(errp, err);
352 return;
353 }
354 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]);
355 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
356 s->fmc.ctrl->flash_window_base);
357 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
358 aspeed_soc_get_irq(s, ASPEED_FMC));
359
360 /* SPI */
361 for (i = 0; i < sc->spis_num; i++) {
362 object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
363 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
364 &local_err);
365 error_propagate(&err, local_err);
366 if (err) {
367 error_propagate(errp, err);
368 return;
369 }
370 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
371 sc->memmap[ASPEED_SPI1 + i]);
372 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
373 s->spi[i].ctrl->flash_window_base);
374 }
375
376 /* EHCI */
377 for (i = 0; i < sc->ehcis_num; i++) {
378 object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", &err);
379 if (err) {
380 error_propagate(errp, err);
381 return;
382 }
383 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
384 sc->memmap[ASPEED_EHCI1 + i]);
385 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
386 aspeed_soc_get_irq(s, ASPEED_EHCI1 + i));
387 }
388
389 /* SDMC - SDRAM Memory Controller */
390 object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
391 if (err) {
392 error_propagate(errp, err);
393 return;
394 }
395 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]);
396
397 /* Watch dog */
398 for (i = 0; i < sc->wdts_num; i++) {
399 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
400
401 object_property_set_link(OBJECT(&s->wdt[i]),
402 OBJECT(&s->scu), "scu", &error_abort);
403 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
404 if (err) {
405 error_propagate(errp, err);
406 return;
407 }
408 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
409 sc->memmap[ASPEED_WDT] + i * awc->offset);
410 }
411
412 /* Net */
413 for (i = 0; i < nb_nics && i < sc->macs_num; i++) {
414 qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
415 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
416 &err);
417 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
418 &local_err);
419 error_propagate(&err, local_err);
420 if (err) {
421 error_propagate(errp, err);
422 return;
423 }
424 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
425 sc->memmap[ASPEED_ETH1 + i]);
426 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
427 aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
428 }
429
430 /* XDMA */
431 object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
432 if (err) {
433 error_propagate(errp, err);
434 return;
435 }
436 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
437 sc->memmap[ASPEED_XDMA]);
438 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
439 aspeed_soc_get_irq(s, ASPEED_XDMA));
440
441 /* GPIO */
442 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
443 if (err) {
444 error_propagate(errp, err);
445 return;
446 }
447 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]);
448 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
449 aspeed_soc_get_irq(s, ASPEED_GPIO));
450
451 /* SDHCI */
452 object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
453 if (err) {
454 error_propagate(errp, err);
455 return;
456 }
457 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
458 sc->memmap[ASPEED_SDHCI]);
459 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
460 aspeed_soc_get_irq(s, ASPEED_SDHCI));
461 }
462 static Property aspeed_soc_properties[] = {
463 DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
464 DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
465 MemoryRegion *),
466 DEFINE_PROP_END_OF_LIST(),
467 };
468
469 static void aspeed_soc_class_init(ObjectClass *oc, void *data)
470 {
471 DeviceClass *dc = DEVICE_CLASS(oc);
472
473 dc->realize = aspeed_soc_realize;
474 /* Reason: Uses serial_hds and nd_table in realize() directly */
475 dc->user_creatable = false;
476 device_class_set_props(dc, aspeed_soc_properties);
477 }
478
479 static const TypeInfo aspeed_soc_type_info = {
480 .name = TYPE_ASPEED_SOC,
481 .parent = TYPE_DEVICE,
482 .instance_size = sizeof(AspeedSoCState),
483 .class_size = sizeof(AspeedSoCClass),
484 .class_init = aspeed_soc_class_init,
485 .abstract = true,
486 };
487
488 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
489 {
490 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
491
492 sc->name = "ast2400-a1";
493 sc->cpu_type = ARM_CPU_TYPE_NAME("arm926");
494 sc->silicon_rev = AST2400_A1_SILICON_REV;
495 sc->sram_size = 0x8000;
496 sc->spis_num = 1;
497 sc->ehcis_num = 1;
498 sc->wdts_num = 2;
499 sc->macs_num = 2;
500 sc->irqmap = aspeed_soc_ast2400_irqmap;
501 sc->memmap = aspeed_soc_ast2400_memmap;
502 sc->num_cpus = 1;
503 }
504
505 static const TypeInfo aspeed_soc_ast2400_type_info = {
506 .name = "ast2400-a1",
507 .parent = TYPE_ASPEED_SOC,
508 .instance_init = aspeed_soc_init,
509 .instance_size = sizeof(AspeedSoCState),
510 .class_init = aspeed_soc_ast2400_class_init,
511 };
512
513 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
514 {
515 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
516
517 sc->name = "ast2500-a1";
518 sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
519 sc->silicon_rev = AST2500_A1_SILICON_REV;
520 sc->sram_size = 0x9000;
521 sc->spis_num = 2;
522 sc->ehcis_num = 2;
523 sc->wdts_num = 3;
524 sc->macs_num = 2;
525 sc->irqmap = aspeed_soc_ast2500_irqmap;
526 sc->memmap = aspeed_soc_ast2500_memmap;
527 sc->num_cpus = 1;
528 }
529
530 static const TypeInfo aspeed_soc_ast2500_type_info = {
531 .name = "ast2500-a1",
532 .parent = TYPE_ASPEED_SOC,
533 .instance_init = aspeed_soc_init,
534 .instance_size = sizeof(AspeedSoCState),
535 .class_init = aspeed_soc_ast2500_class_init,
536 };
537 static void aspeed_soc_register_types(void)
538 {
539 type_register_static(&aspeed_soc_type_info);
540 type_register_static(&aspeed_soc_ast2400_type_info);
541 type_register_static(&aspeed_soc_ast2500_type_info);
542 };
543
544 type_init(aspeed_soc_register_types)
QEMU mirror