4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
7 * Copyright 2016 IBM Corp.
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "qemu-common.h"
17 #include "exec/address-spaces.h"
18 #include "hw/arm/aspeed_soc.h"
19 #include "hw/char/serial.h"
21 #include "hw/i2c/aspeed_i2c.h"
23 #define ASPEED_SOC_UART_5_BASE 0x00184000
24 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
25 #define ASPEED_SOC_IOMEM_BASE 0x1E600000
26 #define ASPEED_SOC_FMC_BASE 0x1E620000
27 #define ASPEED_SOC_SPI_BASE 0x1E630000
28 #define ASPEED_SOC_VIC_BASE 0x1E6C0000
29 #define ASPEED_SOC_SDMC_BASE 0x1E6E0000
30 #define ASPEED_SOC_SCU_BASE 0x1E6E2000
31 #define ASPEED_SOC_TIMER_BASE 0x1E782000
32 #define ASPEED_SOC_I2C_BASE 0x1E78A000
34 #define ASPEED_SOC_FMC_FLASH_BASE 0x20000000
35 #define ASPEED_SOC_SPI_FLASH_BASE 0x30000000
37 static const int uart_irqs
[] = { 9, 32, 33, 34, 10 };
38 static const int timer_irqs
[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
40 #define AST2400_SDRAM_BASE 0x40000000
41 #define AST2500_SDRAM_BASE 0x80000000
43 static const AspeedSoCInfo aspeed_socs
[] = {
44 { "ast2400-a0", "arm926", AST2400_A0_SILICON_REV
, AST2400_SDRAM_BASE
},
45 { "ast2400", "arm926", AST2400_A0_SILICON_REV
, AST2400_SDRAM_BASE
},
46 { "ast2500-a1", "arm1176", AST2500_A1_SILICON_REV
, AST2500_SDRAM_BASE
},
50 * IO handlers: simply catch any reads/writes to IO addresses that aren't
51 * handled by a device mapping.
54 static uint64_t aspeed_soc_io_read(void *p
, hwaddr offset
, unsigned size
)
56 qemu_log_mask(LOG_UNIMP
, "%s: 0x%" HWADDR_PRIx
" [%u]\n",
57 __func__
, offset
, size
);
61 static void aspeed_soc_io_write(void *opaque
, hwaddr offset
, uint64_t value
,
64 qemu_log_mask(LOG_UNIMP
, "%s: 0x%" HWADDR_PRIx
" <- 0x%" PRIx64
" [%u]\n",
65 __func__
, offset
, value
, size
);
68 static const MemoryRegionOps aspeed_soc_io_ops
= {
69 .read
= aspeed_soc_io_read
,
70 .write
= aspeed_soc_io_write
,
71 .endianness
= DEVICE_LITTLE_ENDIAN
,
74 static void aspeed_soc_init(Object
*obj
)
76 AspeedSoCState
*s
= ASPEED_SOC(obj
);
77 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
79 s
->cpu
= cpu_arm_init(sc
->info
->cpu_model
);
81 object_initialize(&s
->vic
, sizeof(s
->vic
), TYPE_ASPEED_VIC
);
82 object_property_add_child(obj
, "vic", OBJECT(&s
->vic
), NULL
);
83 qdev_set_parent_bus(DEVICE(&s
->vic
), sysbus_get_default());
85 object_initialize(&s
->timerctrl
, sizeof(s
->timerctrl
), TYPE_ASPEED_TIMER
);
86 object_property_add_child(obj
, "timerctrl", OBJECT(&s
->timerctrl
), NULL
);
87 qdev_set_parent_bus(DEVICE(&s
->timerctrl
), sysbus_get_default());
89 object_initialize(&s
->i2c
, sizeof(s
->i2c
), TYPE_ASPEED_I2C
);
90 object_property_add_child(obj
, "i2c", OBJECT(&s
->i2c
), NULL
);
91 qdev_set_parent_bus(DEVICE(&s
->i2c
), sysbus_get_default());
93 object_initialize(&s
->scu
, sizeof(s
->scu
), TYPE_ASPEED_SCU
);
94 object_property_add_child(obj
, "scu", OBJECT(&s
->scu
), NULL
);
95 qdev_set_parent_bus(DEVICE(&s
->scu
), sysbus_get_default());
96 qdev_prop_set_uint32(DEVICE(&s
->scu
), "silicon-rev",
97 sc
->info
->silicon_rev
);
98 object_property_add_alias(obj
, "hw-strap1", OBJECT(&s
->scu
),
99 "hw-strap1", &error_abort
);
100 object_property_add_alias(obj
, "hw-strap2", OBJECT(&s
->scu
),
101 "hw-strap2", &error_abort
);
103 object_initialize(&s
->fmc
, sizeof(s
->fmc
), "aspeed.smc.fmc");
104 object_property_add_child(obj
, "fmc", OBJECT(&s
->fmc
), NULL
);
105 qdev_set_parent_bus(DEVICE(&s
->fmc
), sysbus_get_default());
107 object_initialize(&s
->spi
, sizeof(s
->spi
), "aspeed.smc.spi");
108 object_property_add_child(obj
, "spi", OBJECT(&s
->spi
), NULL
);
109 qdev_set_parent_bus(DEVICE(&s
->spi
), sysbus_get_default());
111 object_initialize(&s
->sdmc
, sizeof(s
->sdmc
), TYPE_ASPEED_SDMC
);
112 object_property_add_child(obj
, "sdmc", OBJECT(&s
->sdmc
), NULL
);
113 qdev_set_parent_bus(DEVICE(&s
->sdmc
), sysbus_get_default());
114 qdev_prop_set_uint32(DEVICE(&s
->sdmc
), "silicon-rev",
115 sc
->info
->silicon_rev
);
116 object_property_add_alias(obj
, "ram-size", OBJECT(&s
->sdmc
),
117 "ram-size", &error_abort
);
120 static void aspeed_soc_realize(DeviceState
*dev
, Error
**errp
)
123 AspeedSoCState
*s
= ASPEED_SOC(dev
);
124 Error
*err
= NULL
, *local_err
= NULL
;
127 memory_region_init_io(&s
->iomem
, NULL
, &aspeed_soc_io_ops
, NULL
,
128 "aspeed_soc.io", ASPEED_SOC_IOMEM_SIZE
);
129 memory_region_add_subregion_overlap(get_system_memory(),
130 ASPEED_SOC_IOMEM_BASE
, &s
->iomem
, -1);
133 object_property_set_bool(OBJECT(&s
->vic
), true, "realized", &err
);
135 error_propagate(errp
, err
);
138 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->vic
), 0, ASPEED_SOC_VIC_BASE
);
139 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->vic
), 0,
140 qdev_get_gpio_in(DEVICE(s
->cpu
), ARM_CPU_IRQ
));
141 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->vic
), 1,
142 qdev_get_gpio_in(DEVICE(s
->cpu
), ARM_CPU_FIQ
));
145 object_property_set_bool(OBJECT(&s
->timerctrl
), true, "realized", &err
);
147 error_propagate(errp
, err
);
150 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->timerctrl
), 0, ASPEED_SOC_TIMER_BASE
);
151 for (i
= 0; i
< ARRAY_SIZE(timer_irqs
); i
++) {
152 qemu_irq irq
= qdev_get_gpio_in(DEVICE(&s
->vic
), timer_irqs
[i
]);
153 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->timerctrl
), i
, irq
);
157 object_property_set_bool(OBJECT(&s
->scu
), true, "realized", &err
);
159 error_propagate(errp
, err
);
162 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->scu
), 0, ASPEED_SOC_SCU_BASE
);
164 /* UART - attach an 8250 to the IO space as our UART5 */
166 qemu_irq uart5
= qdev_get_gpio_in(DEVICE(&s
->vic
), uart_irqs
[4]);
167 serial_mm_init(&s
->iomem
, ASPEED_SOC_UART_5_BASE
, 2,
168 uart5
, 38400, serial_hds
[0], DEVICE_LITTLE_ENDIAN
);
172 object_property_set_bool(OBJECT(&s
->i2c
), true, "realized", &err
);
174 error_propagate(errp
, err
);
177 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->i2c
), 0, ASPEED_SOC_I2C_BASE
);
178 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->i2c
), 0,
179 qdev_get_gpio_in(DEVICE(&s
->vic
), 12));
182 object_property_set_int(OBJECT(&s
->fmc
), 1, "num-cs", &err
);
183 object_property_set_bool(OBJECT(&s
->fmc
), true, "realized", &local_err
);
184 error_propagate(&err
, local_err
);
186 error_propagate(errp
, err
);
189 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->fmc
), 0, ASPEED_SOC_FMC_BASE
);
190 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->fmc
), 1, ASPEED_SOC_FMC_FLASH_BASE
);
191 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->fmc
), 0,
192 qdev_get_gpio_in(DEVICE(&s
->vic
), 19));
195 object_property_set_int(OBJECT(&s
->spi
), 1, "num-cs", &err
);
196 object_property_set_bool(OBJECT(&s
->spi
), true, "realized", &local_err
);
197 error_propagate(&err
, local_err
);
199 error_propagate(errp
, err
);
202 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
), 0, ASPEED_SOC_SPI_BASE
);
203 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
), 1, ASPEED_SOC_SPI_FLASH_BASE
);
205 /* SDMC - SDRAM Memory Controller */
206 object_property_set_bool(OBJECT(&s
->sdmc
), true, "realized", &err
);
208 error_propagate(errp
, err
);
211 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sdmc
), 0, ASPEED_SOC_SDMC_BASE
);
214 static void aspeed_soc_class_init(ObjectClass
*oc
, void *data
)
216 DeviceClass
*dc
= DEVICE_CLASS(oc
);
217 AspeedSoCClass
*sc
= ASPEED_SOC_CLASS(oc
);
219 sc
->info
= (AspeedSoCInfo
*) data
;
220 dc
->realize
= aspeed_soc_realize
;
223 * Reason: creates an ARM CPU, thus use after free(), see
224 * arm_cpu_class_init()
226 dc
->cannot_destroy_with_object_finalize_yet
= true;
229 static const TypeInfo aspeed_soc_type_info
= {
230 .name
= TYPE_ASPEED_SOC
,
231 .parent
= TYPE_DEVICE
,
232 .instance_init
= aspeed_soc_init
,
233 .instance_size
= sizeof(AspeedSoCState
),
234 .class_size
= sizeof(AspeedSoCClass
),
238 static void aspeed_soc_register_types(void)
242 type_register_static(&aspeed_soc_type_info
);
243 for (i
= 0; i
< ARRAY_SIZE(aspeed_socs
); ++i
) {
245 .name
= aspeed_socs
[i
].name
,
246 .parent
= TYPE_ASPEED_SOC
,
247 .class_init
= aspeed_soc_class_init
,
248 .class_data
= (void *) &aspeed_socs
[i
],
254 type_init(aspeed_soc_register_types
)