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aspeed: Parameterise number of MACs
[mirror_qemu.git] / hw / arm / aspeed_soc.c
1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
6 *
7 * Copyright 2016 IBM Corp.
8 *
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
11 */
12
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "cpu.h"
16 #include "exec/address-spaces.h"
17 #include "hw/misc/unimp.h"
18 #include "hw/arm/aspeed_soc.h"
19 #include "hw/char/serial.h"
20 #include "qemu/log.h"
21 #include "qemu/module.h"
22 #include "qemu/error-report.h"
23 #include "hw/i2c/aspeed_i2c.h"
24 #include "net/net.h"
25 #include "sysemu/sysemu.h"
26
27 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
28
29 static const hwaddr aspeed_soc_ast2400_memmap[] = {
30 [ASPEED_IOMEM] = 0x1E600000,
31 [ASPEED_FMC] = 0x1E620000,
32 [ASPEED_SPI1] = 0x1E630000,
33 [ASPEED_VIC] = 0x1E6C0000,
34 [ASPEED_SDMC] = 0x1E6E0000,
35 [ASPEED_SCU] = 0x1E6E2000,
36 [ASPEED_XDMA] = 0x1E6E7000,
37 [ASPEED_ADC] = 0x1E6E9000,
38 [ASPEED_SRAM] = 0x1E720000,
39 [ASPEED_SDHCI] = 0x1E740000,
40 [ASPEED_GPIO] = 0x1E780000,
41 [ASPEED_RTC] = 0x1E781000,
42 [ASPEED_TIMER1] = 0x1E782000,
43 [ASPEED_WDT] = 0x1E785000,
44 [ASPEED_PWM] = 0x1E786000,
45 [ASPEED_LPC] = 0x1E789000,
46 [ASPEED_IBT] = 0x1E789140,
47 [ASPEED_I2C] = 0x1E78A000,
48 [ASPEED_ETH1] = 0x1E660000,
49 [ASPEED_ETH2] = 0x1E680000,
50 [ASPEED_UART1] = 0x1E783000,
51 [ASPEED_UART5] = 0x1E784000,
52 [ASPEED_VUART] = 0x1E787000,
53 [ASPEED_SDRAM] = 0x40000000,
54 };
55
56 static const hwaddr aspeed_soc_ast2500_memmap[] = {
57 [ASPEED_IOMEM] = 0x1E600000,
58 [ASPEED_FMC] = 0x1E620000,
59 [ASPEED_SPI1] = 0x1E630000,
60 [ASPEED_SPI2] = 0x1E631000,
61 [ASPEED_VIC] = 0x1E6C0000,
62 [ASPEED_SDMC] = 0x1E6E0000,
63 [ASPEED_SCU] = 0x1E6E2000,
64 [ASPEED_XDMA] = 0x1E6E7000,
65 [ASPEED_ADC] = 0x1E6E9000,
66 [ASPEED_SRAM] = 0x1E720000,
67 [ASPEED_SDHCI] = 0x1E740000,
68 [ASPEED_GPIO] = 0x1E780000,
69 [ASPEED_RTC] = 0x1E781000,
70 [ASPEED_TIMER1] = 0x1E782000,
71 [ASPEED_WDT] = 0x1E785000,
72 [ASPEED_PWM] = 0x1E786000,
73 [ASPEED_LPC] = 0x1E789000,
74 [ASPEED_IBT] = 0x1E789140,
75 [ASPEED_I2C] = 0x1E78A000,
76 [ASPEED_ETH1] = 0x1E660000,
77 [ASPEED_ETH2] = 0x1E680000,
78 [ASPEED_UART1] = 0x1E783000,
79 [ASPEED_UART5] = 0x1E784000,
80 [ASPEED_VUART] = 0x1E787000,
81 [ASPEED_SDRAM] = 0x80000000,
82 };
83
84 static const int aspeed_soc_ast2400_irqmap[] = {
85 [ASPEED_UART1] = 9,
86 [ASPEED_UART2] = 32,
87 [ASPEED_UART3] = 33,
88 [ASPEED_UART4] = 34,
89 [ASPEED_UART5] = 10,
90 [ASPEED_VUART] = 8,
91 [ASPEED_FMC] = 19,
92 [ASPEED_SDMC] = 0,
93 [ASPEED_SCU] = 21,
94 [ASPEED_ADC] = 31,
95 [ASPEED_GPIO] = 20,
96 [ASPEED_RTC] = 22,
97 [ASPEED_TIMER1] = 16,
98 [ASPEED_TIMER2] = 17,
99 [ASPEED_TIMER3] = 18,
100 [ASPEED_TIMER4] = 35,
101 [ASPEED_TIMER5] = 36,
102 [ASPEED_TIMER6] = 37,
103 [ASPEED_TIMER7] = 38,
104 [ASPEED_TIMER8] = 39,
105 [ASPEED_WDT] = 27,
106 [ASPEED_PWM] = 28,
107 [ASPEED_LPC] = 8,
108 [ASPEED_IBT] = 8, /* LPC */
109 [ASPEED_I2C] = 12,
110 [ASPEED_ETH1] = 2,
111 [ASPEED_ETH2] = 3,
112 [ASPEED_XDMA] = 6,
113 [ASPEED_SDHCI] = 26,
114 };
115
116 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
117
118 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
119 {
120 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
121
122 return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[ctrl]);
123 }
124
125 static void aspeed_soc_init(Object *obj)
126 {
127 AspeedSoCState *s = ASPEED_SOC(obj);
128 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
129 int i;
130 char socname[8];
131 char typename[64];
132
133 if (sscanf(sc->name, "%7s", socname) != 1) {
134 g_assert_not_reached();
135 }
136
137 for (i = 0; i < sc->num_cpus; i++) {
138 object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
139 sizeof(s->cpu[i]), sc->cpu_type,
140 &error_abort, NULL);
141 }
142
143 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
144 sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
145 typename);
146 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
147 sc->silicon_rev);
148 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
149 "hw-strap1", &error_abort);
150 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
151 "hw-strap2", &error_abort);
152 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
153 "hw-prot-key", &error_abort);
154
155 sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic),
156 TYPE_ASPEED_VIC);
157
158 sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
159 TYPE_ASPEED_RTC);
160
161 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
162 sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
163 sizeof(s->timerctrl), typename);
164 object_property_add_const_link(OBJECT(&s->timerctrl), "scu",
165 OBJECT(&s->scu), &error_abort);
166
167 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
168 sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
169 typename);
170
171 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
172 sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
173 typename);
174 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
175 &error_abort);
176 object_property_add_alias(obj, "dram", OBJECT(&s->fmc), "dram",
177 &error_abort);
178
179 for (i = 0; i < sc->spis_num; i++) {
180 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
181 sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
182 sizeof(s->spi[i]), typename);
183 }
184
185 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
186 sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
187 typename);
188 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
189 "ram-size", &error_abort);
190 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
191 "max-ram-size", &error_abort);
192
193 for (i = 0; i < sc->wdts_num; i++) {
194 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
195 sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
196 sizeof(s->wdt[i]), typename);
197 object_property_add_const_link(OBJECT(&s->wdt[i]), "scu",
198 OBJECT(&s->scu), &error_abort);
199 }
200
201 for (i = 0; i < sc->macs_num; i++) {
202 sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
203 sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
204 }
205
206 sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
207 TYPE_ASPEED_XDMA);
208
209 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
210 sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio),
211 typename);
212
213 sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),
214 TYPE_ASPEED_SDHCI);
215
216 /* Init sd card slot class here so that they're under the correct parent */
217 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
218 sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),
219 sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
220 }
221 }
222
223 static void aspeed_soc_realize(DeviceState *dev, Error **errp)
224 {
225 int i;
226 AspeedSoCState *s = ASPEED_SOC(dev);
227 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
228 Error *err = NULL, *local_err = NULL;
229
230 /* IO space */
231 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM],
232 ASPEED_SOC_IOMEM_SIZE);
233
234 if (s->num_cpus > sc->num_cpus) {
235 warn_report("%s: invalid number of CPUs %d, using default %d",
236 sc->name, s->num_cpus, sc->num_cpus);
237 s->num_cpus = sc->num_cpus;
238 }
239
240 /* CPU */
241 for (i = 0; i < s->num_cpus; i++) {
242 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
243 if (err) {
244 error_propagate(errp, err);
245 return;
246 }
247 }
248
249 /* SRAM */
250 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
251 sc->sram_size, &err);
252 if (err) {
253 error_propagate(errp, err);
254 return;
255 }
256 memory_region_add_subregion(get_system_memory(),
257 sc->memmap[ASPEED_SRAM], &s->sram);
258
259 /* SCU */
260 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
261 if (err) {
262 error_propagate(errp, err);
263 return;
264 }
265 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);
266
267 /* VIC */
268 object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
269 if (err) {
270 error_propagate(errp, err);
271 return;
272 }
273 sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_VIC]);
274 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
275 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
276 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
277 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
278
279 /* RTC */
280 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
281 if (err) {
282 error_propagate(errp, err);
283 return;
284 }
285 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]);
286 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
287 aspeed_soc_get_irq(s, ASPEED_RTC));
288
289 /* Timer */
290 object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
291 if (err) {
292 error_propagate(errp, err);
293 return;
294 }
295 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
296 sc->memmap[ASPEED_TIMER1]);
297 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
298 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
299 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
300 }
301
302 /* UART - attach an 8250 to the IO space as our UART5 */
303 if (serial_hd(0)) {
304 qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
305 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2,
306 uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
307 }
308
309 /* I2C */
310 object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
311 if (err) {
312 error_propagate(errp, err);
313 return;
314 }
315 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]);
316 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
317 aspeed_soc_get_irq(s, ASPEED_I2C));
318
319 /* FMC, The number of CS is set at the board level */
320 object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM],
321 "sdram-base", &err);
322 if (err) {
323 error_propagate(errp, err);
324 return;
325 }
326 object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
327 if (err) {
328 error_propagate(errp, err);
329 return;
330 }
331 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]);
332 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
333 s->fmc.ctrl->flash_window_base);
334 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
335 aspeed_soc_get_irq(s, ASPEED_FMC));
336
337 /* SPI */
338 for (i = 0; i < sc->spis_num; i++) {
339 object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
340 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
341 &local_err);
342 error_propagate(&err, local_err);
343 if (err) {
344 error_propagate(errp, err);
345 return;
346 }
347 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
348 sc->memmap[ASPEED_SPI1 + i]);
349 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
350 s->spi[i].ctrl->flash_window_base);
351 }
352
353 /* SDMC - SDRAM Memory Controller */
354 object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
355 if (err) {
356 error_propagate(errp, err);
357 return;
358 }
359 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]);
360
361 /* Watch dog */
362 for (i = 0; i < sc->wdts_num; i++) {
363 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
364
365 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
366 if (err) {
367 error_propagate(errp, err);
368 return;
369 }
370 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
371 sc->memmap[ASPEED_WDT] + i * awc->offset);
372 }
373
374 /* Net */
375 for (i = 0; i < nb_nics && i < sc->macs_num; i++) {
376 qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
377 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
378 &err);
379 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
380 &local_err);
381 error_propagate(&err, local_err);
382 if (err) {
383 error_propagate(errp, err);
384 return;
385 }
386 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
387 sc->memmap[ASPEED_ETH1 + i]);
388 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
389 aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
390 }
391
392 /* XDMA */
393 object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
394 if (err) {
395 error_propagate(errp, err);
396 return;
397 }
398 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
399 sc->memmap[ASPEED_XDMA]);
400 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
401 aspeed_soc_get_irq(s, ASPEED_XDMA));
402
403 /* GPIO */
404 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
405 if (err) {
406 error_propagate(errp, err);
407 return;
408 }
409 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]);
410 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
411 aspeed_soc_get_irq(s, ASPEED_GPIO));
412
413 /* SDHCI */
414 object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
415 if (err) {
416 error_propagate(errp, err);
417 return;
418 }
419 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
420 sc->memmap[ASPEED_SDHCI]);
421 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
422 aspeed_soc_get_irq(s, ASPEED_SDHCI));
423 }
424 static Property aspeed_soc_properties[] = {
425 DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
426 DEFINE_PROP_END_OF_LIST(),
427 };
428
429 static void aspeed_soc_class_init(ObjectClass *oc, void *data)
430 {
431 DeviceClass *dc = DEVICE_CLASS(oc);
432
433 dc->realize = aspeed_soc_realize;
434 /* Reason: Uses serial_hds and nd_table in realize() directly */
435 dc->user_creatable = false;
436 dc->props = aspeed_soc_properties;
437 }
438
439 static const TypeInfo aspeed_soc_type_info = {
440 .name = TYPE_ASPEED_SOC,
441 .parent = TYPE_DEVICE,
442 .instance_size = sizeof(AspeedSoCState),
443 .class_size = sizeof(AspeedSoCClass),
444 .class_init = aspeed_soc_class_init,
445 .abstract = true,
446 };
447
448 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
449 {
450 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
451
452 sc->name = "ast2400-a1";
453 sc->cpu_type = ARM_CPU_TYPE_NAME("arm926");
454 sc->silicon_rev = AST2400_A1_SILICON_REV;
455 sc->sram_size = 0x8000;
456 sc->spis_num = 1;
457 sc->wdts_num = 2;
458 sc->macs_num = 2;
459 sc->irqmap = aspeed_soc_ast2400_irqmap;
460 sc->memmap = aspeed_soc_ast2400_memmap;
461 sc->num_cpus = 1;
462 }
463
464 static const TypeInfo aspeed_soc_ast2400_type_info = {
465 .name = "ast2400-a1",
466 .parent = TYPE_ASPEED_SOC,
467 .instance_init = aspeed_soc_init,
468 .instance_size = sizeof(AspeedSoCState),
469 .class_init = aspeed_soc_ast2400_class_init,
470 };
471
472 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
473 {
474 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
475
476 sc->name = "ast2500-a1";
477 sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
478 sc->silicon_rev = AST2500_A1_SILICON_REV;
479 sc->sram_size = 0x9000;
480 sc->spis_num = 2;
481 sc->wdts_num = 3;
482 sc->macs_num = 2;
483 sc->irqmap = aspeed_soc_ast2500_irqmap;
484 sc->memmap = aspeed_soc_ast2500_memmap;
485 sc->num_cpus = 1;
486 }
487
488 static const TypeInfo aspeed_soc_ast2500_type_info = {
489 .name = "ast2500-a1",
490 .parent = TYPE_ASPEED_SOC,
491 .instance_init = aspeed_soc_init,
492 .instance_size = sizeof(AspeedSoCState),
493 .class_init = aspeed_soc_ast2500_class_init,
494 };
495 static void aspeed_soc_register_types(void)
496 {
497 type_register_static(&aspeed_soc_type_info);
498 type_register_static(&aspeed_soc_ast2400_type_info);
499 type_register_static(&aspeed_soc_ast2500_type_info);
500 };
501
502 type_init(aspeed_soc_register_types)
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