hw/arm/aspeed_soc.c

   1 /*
   2  * ASPEED SoC family
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  * Jeremy Kerr <jk@ozlabs.org>
   6  *
   7  * Copyright 2016 IBM Corp.
   8  *
   9  * This code is licensed under the GPL version 2 or later.  See
  10  * the COPYING file in the top-level directory.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qapi/error.h"
  15 #include "qemu-common.h"
  16 #include "cpu.h"
  17 #include "exec/address-spaces.h"
  18 #include "hw/arm/aspeed_soc.h"
  19 #include "hw/char/serial.h"
  20 #include "qemu/log.h"
  21 #include "hw/i2c/aspeed_i2c.h"
  22
  23 #define ASPEED_SOC_UART_5_BASE      0x00184000
  24 #define ASPEED_SOC_IOMEM_SIZE       0x00200000
  25 #define ASPEED_SOC_IOMEM_BASE       0x1E600000
  26 #define ASPEED_SOC_FMC_BASE         0x1E620000
  27 #define ASPEED_SOC_SPI_BASE         0x1E630000
  28 #define ASPEED_SOC_VIC_BASE         0x1E6C0000
  29 #define ASPEED_SOC_SDMC_BASE        0x1E6E0000
  30 #define ASPEED_SOC_SCU_BASE         0x1E6E2000
  31 #define ASPEED_SOC_TIMER_BASE       0x1E782000
  32 #define ASPEED_SOC_I2C_BASE         0x1E78A000
  33
  34 static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
  35 static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
  36
  37 #define AST2400_SDRAM_BASE       0x40000000
  38 #define AST2500_SDRAM_BASE       0x80000000
  39
  40 static const hwaddr aspeed_soc_ast2400_spi_bases[] = { ASPEED_SOC_SPI_BASE };
  41
  42 static const hwaddr aspeed_soc_ast2500_spi_bases[] = { ASPEED_SOC_SPI_BASE };
  43
  44 static const AspeedSoCInfo aspeed_socs[] = {
  45     { "ast2400-a0", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE,
  46       1, aspeed_soc_ast2400_spi_bases },
  47     { "ast2400",    "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE,
  48       1, aspeed_soc_ast2400_spi_bases },
  49     { "ast2500-a1", "arm1176", AST2500_A1_SILICON_REV, AST2500_SDRAM_BASE,
  50       1, aspeed_soc_ast2500_spi_bases },
  51 };
  52
  53 /*
  54  * IO handlers: simply catch any reads/writes to IO addresses that aren't
  55  * handled by a device mapping.
  56  */
  57
  58 static uint64_t aspeed_soc_io_read(void *p, hwaddr offset, unsigned size)
  59 {
  60     qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
  61                   __func__, offset, size);
  62     return 0;
  63 }
  64
  65 static void aspeed_soc_io_write(void *opaque, hwaddr offset, uint64_t value,
  66                 unsigned size)
  67 {
  68     qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
  69                   __func__, offset, value, size);
  70 }
  71
  72 static const MemoryRegionOps aspeed_soc_io_ops = {
  73     .read = aspeed_soc_io_read,
  74     .write = aspeed_soc_io_write,
  75     .endianness = DEVICE_LITTLE_ENDIAN,
  76 };
  77
  78 static void aspeed_soc_init(Object *obj)
  79 {
  80     AspeedSoCState *s = ASPEED_SOC(obj);
  81     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
  82     int i;
  83
  84     s->cpu = cpu_arm_init(sc->info->cpu_model);
  85
  86     object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
  87     object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
  88     qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default());
  89
  90     object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
  91     object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL);
  92     qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default());
  93
  94     object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C);
  95     object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL);
  96     qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default());
  97
  98     object_initialize(&s->scu, sizeof(s->scu), TYPE_ASPEED_SCU);
  99     object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL);
 100     qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
 101     qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
 102                          sc->info->silicon_rev);
 103     object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
 104                               "hw-strap1", &error_abort);
 105     object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
 106                               "hw-strap2", &error_abort);
 107
 108     object_initialize(&s->fmc, sizeof(s->fmc), "aspeed.smc.fmc");
 109     object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL);
 110     qdev_set_parent_bus(DEVICE(&s->fmc), sysbus_get_default());
 111
 112     for (i = 0; i < sc->info->spis_num; i++) {
 113         object_initialize(&s->spi[i], sizeof(s->spi[i]), "aspeed.smc.spi");
 114         object_property_add_child(obj, "spi", OBJECT(&s->spi[i]), NULL);
 115         qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
 116     }
 117
 118     object_initialize(&s->sdmc, sizeof(s->sdmc), TYPE_ASPEED_SDMC);
 119     object_property_add_child(obj, "sdmc", OBJECT(&s->sdmc), NULL);
 120     qdev_set_parent_bus(DEVICE(&s->sdmc), sysbus_get_default());
 121     qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",
 122                          sc->info->silicon_rev);
 123     object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
 124                               "ram-size", &error_abort);
 125 }
 126
 127 static void aspeed_soc_realize(DeviceState *dev, Error **errp)
 128 {
 129     int i;
 130     AspeedSoCState *s = ASPEED_SOC(dev);
 131     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 132     Error *err = NULL, *local_err = NULL;
 133
 134     /* IO space */
 135     memory_region_init_io(&s->iomem, NULL, &aspeed_soc_io_ops, NULL,
 136             "aspeed_soc.io", ASPEED_SOC_IOMEM_SIZE);
 137     memory_region_add_subregion_overlap(get_system_memory(),
 138                                         ASPEED_SOC_IOMEM_BASE, &s->iomem, -1);
 139
 140     /* VIC */
 141     object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
 142     if (err) {
 143         error_propagate(errp, err);
 144         return;
 145     }
 146     sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, ASPEED_SOC_VIC_BASE);
 147     sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
 148                        qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
 149     sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
 150                        qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
 151
 152     /* Timer */
 153     object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
 154     if (err) {
 155         error_propagate(errp, err);
 156         return;
 157     }
 158     sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BASE);
 159     for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {
 160         qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]);
 161         sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
 162     }
 163
 164     /* SCU */
 165     object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
 166     if (err) {
 167         error_propagate(errp, err);
 168         return;
 169     }
 170     sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE);
 171
 172     /* UART - attach an 8250 to the IO space as our UART5 */
 173     if (serial_hds[0]) {
 174         qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
 175         serial_mm_init(&s->iomem, ASPEED_SOC_UART_5_BASE, 2,
 176                        uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN);
 177     }
 178
 179     /* I2C */
 180     object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
 181     if (err) {
 182         error_propagate(errp, err);
 183         return;
 184     }
 185     sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE);
 186     sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
 187                        qdev_get_gpio_in(DEVICE(&s->vic), 12));
 188
 189     /* FMC */
 190     object_property_set_int(OBJECT(&s->fmc), 1, "num-cs", &err);
 191     object_property_set_bool(OBJECT(&s->fmc), true, "realized", &local_err);
 192     error_propagate(&err, local_err);
 193     if (err) {
 194         error_propagate(errp, err);
 195         return;
 196     }
 197     sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, ASPEED_SOC_FMC_BASE);
 198     sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
 199                     s->fmc.ctrl->flash_window_base);
 200     sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
 201                        qdev_get_gpio_in(DEVICE(&s->vic), 19));
 202
 203     /* SPI */
 204     for (i = 0; i < sc->info->spis_num; i++) {
 205         object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
 206         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
 207                                  &local_err);
 208         error_propagate(&err, local_err);
 209         if (err) {
 210             error_propagate(errp, err);
 211             return;
 212         }
 213         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, sc->info->spi_bases[i]);
 214         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
 215                         s->spi[i].ctrl->flash_window_base);
 216     }
 217
 218     /* SDMC - SDRAM Memory Controller */
 219     object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
 220     if (err) {
 221         error_propagate(errp, err);
 222         return;
 223     }
 224     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
 225 }
 226
 227 static void aspeed_soc_class_init(ObjectClass *oc, void *data)
 228 {
 229     DeviceClass *dc = DEVICE_CLASS(oc);
 230     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
 231
 232     sc->info = (AspeedSoCInfo *) data;
 233     dc->realize = aspeed_soc_realize;
 234
 235     /*
 236      * Reason: creates an ARM CPU, thus use after free(), see
 237      * arm_cpu_class_init()
 238      */
 239     dc->cannot_destroy_with_object_finalize_yet = true;
 240 }
 241
 242 static const TypeInfo aspeed_soc_type_info = {
 243     .name           = TYPE_ASPEED_SOC,
 244     .parent         = TYPE_DEVICE,
 245     .instance_init  = aspeed_soc_init,
 246     .instance_size  = sizeof(AspeedSoCState),
 247     .class_size     = sizeof(AspeedSoCClass),
 248     .abstract       = true,
 249 };
 250
 251 static void aspeed_soc_register_types(void)
 252 {
 253     int i;
 254
 255     type_register_static(&aspeed_soc_type_info);
 256     for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) {
 257         TypeInfo ti = {
 258             .name       = aspeed_socs[i].name,
 259             .parent     = TYPE_ASPEED_SOC,
 260             .class_init = aspeed_soc_class_init,
 261             .class_data = (void *) &aspeed_socs[i],
 262         };
 263         type_register(&ti);
 264     }
 265 }
 266
 267 type_init(aspeed_soc_register_types)