4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
7 * Copyright 2016 IBM Corp.
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
16 #include "exec/address-spaces.h"
17 #include "hw/misc/unimp.h"
18 #include "hw/arm/aspeed_soc.h"
19 #include "hw/char/serial.h"
21 #include "qemu/module.h"
22 #include "qemu/error-report.h"
23 #include "hw/i2c/aspeed_i2c.h"
25 #include "sysemu/sysemu.h"
27 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
29 static const hwaddr aspeed_soc_ast2400_memmap
[] = {
30 [ASPEED_IOMEM
] = 0x1E600000,
31 [ASPEED_FMC
] = 0x1E620000,
32 [ASPEED_SPI1
] = 0x1E630000,
33 [ASPEED_VIC
] = 0x1E6C0000,
34 [ASPEED_SDMC
] = 0x1E6E0000,
35 [ASPEED_SCU
] = 0x1E6E2000,
36 [ASPEED_XDMA
] = 0x1E6E7000,
37 [ASPEED_ADC
] = 0x1E6E9000,
38 [ASPEED_SRAM
] = 0x1E720000,
39 [ASPEED_SDHCI
] = 0x1E740000,
40 [ASPEED_GPIO
] = 0x1E780000,
41 [ASPEED_RTC
] = 0x1E781000,
42 [ASPEED_TIMER1
] = 0x1E782000,
43 [ASPEED_WDT
] = 0x1E785000,
44 [ASPEED_PWM
] = 0x1E786000,
45 [ASPEED_LPC
] = 0x1E789000,
46 [ASPEED_IBT
] = 0x1E789140,
47 [ASPEED_I2C
] = 0x1E78A000,
48 [ASPEED_ETH1
] = 0x1E660000,
49 [ASPEED_ETH2
] = 0x1E680000,
50 [ASPEED_UART1
] = 0x1E783000,
51 [ASPEED_UART5
] = 0x1E784000,
52 [ASPEED_VUART
] = 0x1E787000,
53 [ASPEED_SDRAM
] = 0x40000000,
56 static const hwaddr aspeed_soc_ast2500_memmap
[] = {
57 [ASPEED_IOMEM
] = 0x1E600000,
58 [ASPEED_FMC
] = 0x1E620000,
59 [ASPEED_SPI1
] = 0x1E630000,
60 [ASPEED_SPI2
] = 0x1E631000,
61 [ASPEED_VIC
] = 0x1E6C0000,
62 [ASPEED_SDMC
] = 0x1E6E0000,
63 [ASPEED_SCU
] = 0x1E6E2000,
64 [ASPEED_XDMA
] = 0x1E6E7000,
65 [ASPEED_ADC
] = 0x1E6E9000,
66 [ASPEED_SRAM
] = 0x1E720000,
67 [ASPEED_SDHCI
] = 0x1E740000,
68 [ASPEED_GPIO
] = 0x1E780000,
69 [ASPEED_RTC
] = 0x1E781000,
70 [ASPEED_TIMER1
] = 0x1E782000,
71 [ASPEED_WDT
] = 0x1E785000,
72 [ASPEED_PWM
] = 0x1E786000,
73 [ASPEED_LPC
] = 0x1E789000,
74 [ASPEED_IBT
] = 0x1E789140,
75 [ASPEED_I2C
] = 0x1E78A000,
76 [ASPEED_ETH1
] = 0x1E660000,
77 [ASPEED_ETH2
] = 0x1E680000,
78 [ASPEED_UART1
] = 0x1E783000,
79 [ASPEED_UART5
] = 0x1E784000,
80 [ASPEED_VUART
] = 0x1E787000,
81 [ASPEED_SDRAM
] = 0x80000000,
84 static const int aspeed_soc_ast2400_irqmap
[] = {
100 [ASPEED_TIMER4
] = 35,
101 [ASPEED_TIMER5
] = 36,
102 [ASPEED_TIMER6
] = 37,
103 [ASPEED_TIMER7
] = 38,
104 [ASPEED_TIMER8
] = 39,
108 [ASPEED_IBT
] = 8, /* LPC */
116 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
118 static const AspeedSoCInfo aspeed_socs
[] = {
120 .name
= "ast2400-a1",
121 .cpu_type
= ARM_CPU_TYPE_NAME("arm926"),
122 .silicon_rev
= AST2400_A1_SILICON_REV
,
126 .irqmap
= aspeed_soc_ast2400_irqmap
,
127 .memmap
= aspeed_soc_ast2400_memmap
,
130 .name
= "ast2500-a1",
131 .cpu_type
= ARM_CPU_TYPE_NAME("arm1176"),
132 .silicon_rev
= AST2500_A1_SILICON_REV
,
136 .irqmap
= aspeed_soc_ast2500_irqmap
,
137 .memmap
= aspeed_soc_ast2500_memmap
,
142 static qemu_irq
aspeed_soc_get_irq(AspeedSoCState
*s
, int ctrl
)
144 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
146 return qdev_get_gpio_in(DEVICE(&s
->vic
), sc
->info
->irqmap
[ctrl
]);
149 static void aspeed_soc_init(Object
*obj
)
151 AspeedSoCState
*s
= ASPEED_SOC(obj
);
152 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
157 if (sscanf(sc
->info
->name
, "%7s", socname
) != 1) {
158 g_assert_not_reached();
161 for (i
= 0; i
< sc
->info
->num_cpus
; i
++) {
162 object_initialize_child(obj
, "cpu[*]", OBJECT(&s
->cpu
[i
]),
163 sizeof(s
->cpu
[i
]), sc
->info
->cpu_type
,
167 snprintf(typename
, sizeof(typename
), "aspeed.scu-%s", socname
);
168 sysbus_init_child_obj(obj
, "scu", OBJECT(&s
->scu
), sizeof(s
->scu
),
170 qdev_prop_set_uint32(DEVICE(&s
->scu
), "silicon-rev",
171 sc
->info
->silicon_rev
);
172 object_property_add_alias(obj
, "hw-strap1", OBJECT(&s
->scu
),
173 "hw-strap1", &error_abort
);
174 object_property_add_alias(obj
, "hw-strap2", OBJECT(&s
->scu
),
175 "hw-strap2", &error_abort
);
176 object_property_add_alias(obj
, "hw-prot-key", OBJECT(&s
->scu
),
177 "hw-prot-key", &error_abort
);
179 sysbus_init_child_obj(obj
, "vic", OBJECT(&s
->vic
), sizeof(s
->vic
),
182 sysbus_init_child_obj(obj
, "rtc", OBJECT(&s
->rtc
), sizeof(s
->rtc
),
185 snprintf(typename
, sizeof(typename
), "aspeed.timer-%s", socname
);
186 sysbus_init_child_obj(obj
, "timerctrl", OBJECT(&s
->timerctrl
),
187 sizeof(s
->timerctrl
), typename
);
188 object_property_add_const_link(OBJECT(&s
->timerctrl
), "scu",
189 OBJECT(&s
->scu
), &error_abort
);
191 snprintf(typename
, sizeof(typename
), "aspeed.i2c-%s", socname
);
192 sysbus_init_child_obj(obj
, "i2c", OBJECT(&s
->i2c
), sizeof(s
->i2c
),
195 snprintf(typename
, sizeof(typename
), "aspeed.fmc-%s", socname
);
196 sysbus_init_child_obj(obj
, "fmc", OBJECT(&s
->fmc
), sizeof(s
->fmc
),
198 object_property_add_alias(obj
, "num-cs", OBJECT(&s
->fmc
), "num-cs",
200 object_property_add_alias(obj
, "dram", OBJECT(&s
->fmc
), "dram",
203 for (i
= 0; i
< sc
->info
->spis_num
; i
++) {
204 snprintf(typename
, sizeof(typename
), "aspeed.spi%d-%s", i
+ 1, socname
);
205 sysbus_init_child_obj(obj
, "spi[*]", OBJECT(&s
->spi
[i
]),
206 sizeof(s
->spi
[i
]), typename
);
209 snprintf(typename
, sizeof(typename
), "aspeed.sdmc-%s", socname
);
210 sysbus_init_child_obj(obj
, "sdmc", OBJECT(&s
->sdmc
), sizeof(s
->sdmc
),
212 object_property_add_alias(obj
, "ram-size", OBJECT(&s
->sdmc
),
213 "ram-size", &error_abort
);
214 object_property_add_alias(obj
, "max-ram-size", OBJECT(&s
->sdmc
),
215 "max-ram-size", &error_abort
);
217 for (i
= 0; i
< sc
->info
->wdts_num
; i
++) {
218 snprintf(typename
, sizeof(typename
), "aspeed.wdt-%s", socname
);
219 sysbus_init_child_obj(obj
, "wdt[*]", OBJECT(&s
->wdt
[i
]),
220 sizeof(s
->wdt
[i
]), typename
);
221 object_property_add_const_link(OBJECT(&s
->wdt
[i
]), "scu",
222 OBJECT(&s
->scu
), &error_abort
);
225 for (i
= 0; i
< ASPEED_MACS_NUM
; i
++) {
226 sysbus_init_child_obj(obj
, "ftgmac100[*]", OBJECT(&s
->ftgmac100
[i
]),
227 sizeof(s
->ftgmac100
[i
]), TYPE_FTGMAC100
);
230 sysbus_init_child_obj(obj
, "xdma", OBJECT(&s
->xdma
), sizeof(s
->xdma
),
233 snprintf(typename
, sizeof(typename
), "aspeed.gpio-%s", socname
);
234 sysbus_init_child_obj(obj
, "gpio", OBJECT(&s
->gpio
), sizeof(s
->gpio
),
237 sysbus_init_child_obj(obj
, "sdc", OBJECT(&s
->sdhci
), sizeof(s
->sdhci
),
240 /* Init sd card slot class here so that they're under the correct parent */
241 for (i
= 0; i
< ASPEED_SDHCI_NUM_SLOTS
; ++i
) {
242 sysbus_init_child_obj(obj
, "sdhci[*]", OBJECT(&s
->sdhci
.slots
[i
]),
243 sizeof(s
->sdhci
.slots
[i
]), TYPE_SYSBUS_SDHCI
);
247 static void aspeed_soc_realize(DeviceState
*dev
, Error
**errp
)
250 AspeedSoCState
*s
= ASPEED_SOC(dev
);
251 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
252 Error
*err
= NULL
, *local_err
= NULL
;
255 create_unimplemented_device("aspeed_soc.io", sc
->info
->memmap
[ASPEED_IOMEM
],
256 ASPEED_SOC_IOMEM_SIZE
);
258 if (s
->num_cpus
> sc
->info
->num_cpus
) {
259 warn_report("%s: invalid number of CPUs %d, using default %d",
260 sc
->info
->name
, s
->num_cpus
, sc
->info
->num_cpus
);
261 s
->num_cpus
= sc
->info
->num_cpus
;
265 for (i
= 0; i
< s
->num_cpus
; i
++) {
266 object_property_set_bool(OBJECT(&s
->cpu
[i
]), true, "realized", &err
);
268 error_propagate(errp
, err
);
274 memory_region_init_ram(&s
->sram
, OBJECT(dev
), "aspeed.sram",
275 sc
->info
->sram_size
, &err
);
277 error_propagate(errp
, err
);
280 memory_region_add_subregion(get_system_memory(),
281 sc
->info
->memmap
[ASPEED_SRAM
], &s
->sram
);
284 object_property_set_bool(OBJECT(&s
->scu
), true, "realized", &err
);
286 error_propagate(errp
, err
);
289 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->scu
), 0, sc
->info
->memmap
[ASPEED_SCU
]);
292 object_property_set_bool(OBJECT(&s
->vic
), true, "realized", &err
);
294 error_propagate(errp
, err
);
297 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->vic
), 0, sc
->info
->memmap
[ASPEED_VIC
]);
298 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->vic
), 0,
299 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_IRQ
));
300 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->vic
), 1,
301 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_FIQ
));
304 object_property_set_bool(OBJECT(&s
->rtc
), true, "realized", &err
);
306 error_propagate(errp
, err
);
309 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->rtc
), 0, sc
->info
->memmap
[ASPEED_RTC
]);
310 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->rtc
), 0,
311 aspeed_soc_get_irq(s
, ASPEED_RTC
));
314 object_property_set_bool(OBJECT(&s
->timerctrl
), true, "realized", &err
);
316 error_propagate(errp
, err
);
319 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->timerctrl
), 0,
320 sc
->info
->memmap
[ASPEED_TIMER1
]);
321 for (i
= 0; i
< ASPEED_TIMER_NR_TIMERS
; i
++) {
322 qemu_irq irq
= aspeed_soc_get_irq(s
, ASPEED_TIMER1
+ i
);
323 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->timerctrl
), i
, irq
);
326 /* UART - attach an 8250 to the IO space as our UART5 */
328 qemu_irq uart5
= aspeed_soc_get_irq(s
, ASPEED_UART5
);
329 serial_mm_init(get_system_memory(), sc
->info
->memmap
[ASPEED_UART5
], 2,
330 uart5
, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN
);
334 object_property_set_bool(OBJECT(&s
->i2c
), true, "realized", &err
);
336 error_propagate(errp
, err
);
339 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->i2c
), 0, sc
->info
->memmap
[ASPEED_I2C
]);
340 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->i2c
), 0,
341 aspeed_soc_get_irq(s
, ASPEED_I2C
));
343 /* FMC, The number of CS is set at the board level */
344 object_property_set_int(OBJECT(&s
->fmc
), sc
->info
->memmap
[ASPEED_SDRAM
],
347 error_propagate(errp
, err
);
350 object_property_set_bool(OBJECT(&s
->fmc
), true, "realized", &err
);
352 error_propagate(errp
, err
);
355 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->fmc
), 0, sc
->info
->memmap
[ASPEED_FMC
]);
356 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->fmc
), 1,
357 s
->fmc
.ctrl
->flash_window_base
);
358 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->fmc
), 0,
359 aspeed_soc_get_irq(s
, ASPEED_FMC
));
362 for (i
= 0; i
< sc
->info
->spis_num
; i
++) {
363 object_property_set_int(OBJECT(&s
->spi
[i
]), 1, "num-cs", &err
);
364 object_property_set_bool(OBJECT(&s
->spi
[i
]), true, "realized",
366 error_propagate(&err
, local_err
);
368 error_propagate(errp
, err
);
371 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 0,
372 sc
->info
->memmap
[ASPEED_SPI1
+ i
]);
373 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 1,
374 s
->spi
[i
].ctrl
->flash_window_base
);
377 /* SDMC - SDRAM Memory Controller */
378 object_property_set_bool(OBJECT(&s
->sdmc
), true, "realized", &err
);
380 error_propagate(errp
, err
);
383 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sdmc
), 0, sc
->info
->memmap
[ASPEED_SDMC
]);
386 for (i
= 0; i
< sc
->info
->wdts_num
; i
++) {
387 AspeedWDTClass
*awc
= ASPEED_WDT_GET_CLASS(&s
->wdt
[i
]);
389 object_property_set_bool(OBJECT(&s
->wdt
[i
]), true, "realized", &err
);
391 error_propagate(errp
, err
);
394 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->wdt
[i
]), 0,
395 sc
->info
->memmap
[ASPEED_WDT
] + i
* awc
->offset
);
399 for (i
= 0; i
< nb_nics
; i
++) {
400 qdev_set_nic_properties(DEVICE(&s
->ftgmac100
[i
]), &nd_table
[i
]);
401 object_property_set_bool(OBJECT(&s
->ftgmac100
[i
]), true, "aspeed",
403 object_property_set_bool(OBJECT(&s
->ftgmac100
[i
]), true, "realized",
405 error_propagate(&err
, local_err
);
407 error_propagate(errp
, err
);
410 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ftgmac100
[i
]), 0,
411 sc
->info
->memmap
[ASPEED_ETH1
+ i
]);
412 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->ftgmac100
[i
]), 0,
413 aspeed_soc_get_irq(s
, ASPEED_ETH1
+ i
));
417 object_property_set_bool(OBJECT(&s
->xdma
), true, "realized", &err
);
419 error_propagate(errp
, err
);
422 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->xdma
), 0,
423 sc
->info
->memmap
[ASPEED_XDMA
]);
424 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->xdma
), 0,
425 aspeed_soc_get_irq(s
, ASPEED_XDMA
));
428 object_property_set_bool(OBJECT(&s
->gpio
), true, "realized", &err
);
430 error_propagate(errp
, err
);
433 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpio
), 0, sc
->info
->memmap
[ASPEED_GPIO
]);
434 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpio
), 0,
435 aspeed_soc_get_irq(s
, ASPEED_GPIO
));
438 object_property_set_bool(OBJECT(&s
->sdhci
), true, "realized", &err
);
440 error_propagate(errp
, err
);
443 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sdhci
), 0,
444 sc
->info
->memmap
[ASPEED_SDHCI
]);
445 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->sdhci
), 0,
446 aspeed_soc_get_irq(s
, ASPEED_SDHCI
));
448 static Property aspeed_soc_properties
[] = {
449 DEFINE_PROP_UINT32("num-cpus", AspeedSoCState
, num_cpus
, 0),
450 DEFINE_PROP_END_OF_LIST(),
453 static void aspeed_soc_class_init(ObjectClass
*oc
, void *data
)
455 DeviceClass
*dc
= DEVICE_CLASS(oc
);
456 AspeedSoCClass
*sc
= ASPEED_SOC_CLASS(oc
);
458 sc
->info
= (AspeedSoCInfo
*) data
;
459 dc
->realize
= aspeed_soc_realize
;
460 /* Reason: Uses serial_hds and nd_table in realize() directly */
461 dc
->user_creatable
= false;
462 dc
->props
= aspeed_soc_properties
;
465 static const TypeInfo aspeed_soc_type_info
= {
466 .name
= TYPE_ASPEED_SOC
,
467 .parent
= TYPE_DEVICE
,
468 .instance_init
= aspeed_soc_init
,
469 .instance_size
= sizeof(AspeedSoCState
),
470 .class_size
= sizeof(AspeedSoCClass
),
474 static void aspeed_soc_register_types(void)
478 type_register_static(&aspeed_soc_type_info
);
479 for (i
= 0; i
< ARRAY_SIZE(aspeed_socs
); ++i
) {
481 .name
= aspeed_socs
[i
].name
,
482 .parent
= TYPE_ASPEED_SOC
,
483 .class_init
= aspeed_soc_class_init
,
484 .class_data
= (void *) &aspeed_socs
[i
],
490 type_init(aspeed_soc_register_types
)