hw/arm/digic.c

   1 /*
   2  * QEMU model of the Canon DIGIC SoC.
   3  *
   4  * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
   5  *
   6  * This model is based on reverse engineering efforts
   7  * made by CHDK (http://chdk.wikia.com) and
   8  * Magic Lantern (http://www.magiclantern.fm) projects
   9  * contributors.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19  * GNU General Public License for more details.
  20  *
  21  */
  22
  23 #include "qemu/osdep.h"
  24 #include "qapi/error.h"
  25 #include "hw/arm/digic.h"
  26 #include "sysemu/sysemu.h"
  27
  28 #define DIGIC4_TIMER_BASE(n)    (0xc0210000 + (n) * 0x100)
  29
  30 #define DIGIC_UART_BASE          0xc0800000
  31
  32 static void digic_init(Object *obj)
  33 {
  34     DigicState *s = DIGIC(obj);
  35     int i;
  36
  37     object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
  38                             "arm946-" TYPE_ARM_CPU, &error_abort, NULL);
  39
  40     for (i = 0; i < DIGIC4_NB_TIMERS; i++) {
  41 #define DIGIC_TIMER_NAME_MLEN    11
  42         char name[DIGIC_TIMER_NAME_MLEN];
  43
  44         snprintf(name, DIGIC_TIMER_NAME_MLEN, "timer[%d]", i);
  45         sysbus_init_child_obj(obj, name, &s->timer[i], sizeof(s->timer[i]),
  46                               TYPE_DIGIC_TIMER);
  47     }
  48
  49     sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart),
  50                           TYPE_DIGIC_UART);
  51 }
  52
  53 static void digic_realize(DeviceState *dev, Error **errp)
  54 {
  55     DigicState *s = DIGIC(dev);
  56     Error *err = NULL;
  57     SysBusDevice *sbd;
  58     int i;
  59
  60     object_property_set_bool(OBJECT(&s->cpu), true, "reset-hivecs", &err);
  61     if (err != NULL) {
  62         error_propagate(errp, err);
  63         return;
  64     }
  65
  66     object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
  67     if (err != NULL) {
  68         error_propagate(errp, err);
  69         return;
  70     }
  71
  72     for (i = 0; i < DIGIC4_NB_TIMERS; i++) {
  73         object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
  74         if (err != NULL) {
  75             error_propagate(errp, err);
  76             return;
  77         }
  78
  79         sbd = SYS_BUS_DEVICE(&s->timer[i]);
  80         sysbus_mmio_map(sbd, 0, DIGIC4_TIMER_BASE(i));
  81     }
  82
  83     qdev_prop_set_chr(DEVICE(&s->uart), "chardev", serial_hd(0));
  84     object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);
  85     if (err != NULL) {
  86         error_propagate(errp, err);
  87         return;
  88     }
  89
  90     sbd = SYS_BUS_DEVICE(&s->uart);
  91     sysbus_mmio_map(sbd, 0, DIGIC_UART_BASE);
  92 }
  93
  94 static void digic_class_init(ObjectClass *oc, void *data)
  95 {
  96     DeviceClass *dc = DEVICE_CLASS(oc);
  97
  98     dc->realize = digic_realize;
  99     /* Reason: Uses serial_hds in the realize function --> not usable twice */
 100     dc->user_creatable = false;
 101 }
 102
 103 static const TypeInfo digic_type_info = {
 104     .name = TYPE_DIGIC,
 105     .parent = TYPE_DEVICE,
 106     .instance_size = sizeof(DigicState),
 107     .instance_init = digic_init,
 108     .class_init = digic_class_init,
 109 };
 110
 111 static void digic_register_types(void)
 112 {
 113     type_register_static(&digic_type_info);
 114 }
 115
 116 type_init(digic_register_types)