2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
4 * i.MX31 SOC emulation.
6 * Based on hw/arm/fsl-imx31.c
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
25 #include "hw/arm/fsl-imx31.h"
26 #include "sysemu/sysemu.h"
27 #include "exec/address-spaces.h"
28 #include "hw/qdev-properties.h"
29 #include "chardev/char.h"
31 static void fsl_imx31_init(Object
*obj
)
33 FslIMX31State
*s
= FSL_IMX31(obj
);
36 object_initialize_child(obj
, "cpu", &s
->cpu
, sizeof(s
->cpu
),
37 ARM_CPU_TYPE_NAME("arm1136"),
40 sysbus_init_child_obj(obj
, "avic", &s
->avic
, sizeof(s
->avic
),
43 sysbus_init_child_obj(obj
, "ccm", &s
->ccm
, sizeof(s
->ccm
), TYPE_IMX31_CCM
);
45 for (i
= 0; i
< FSL_IMX31_NUM_UARTS
; i
++) {
46 sysbus_init_child_obj(obj
, "uart[*]", &s
->uart
[i
], sizeof(s
->uart
[i
]),
50 sysbus_init_child_obj(obj
, "gpt", &s
->gpt
, sizeof(s
->gpt
), TYPE_IMX31_GPT
);
52 for (i
= 0; i
< FSL_IMX31_NUM_EPITS
; i
++) {
53 sysbus_init_child_obj(obj
, "epit[*]", &s
->epit
[i
], sizeof(s
->epit
[i
]),
57 for (i
= 0; i
< FSL_IMX31_NUM_I2CS
; i
++) {
58 sysbus_init_child_obj(obj
, "i2c[*]", &s
->i2c
[i
], sizeof(s
->i2c
[i
]),
62 for (i
= 0; i
< FSL_IMX31_NUM_GPIOS
; i
++) {
63 sysbus_init_child_obj(obj
, "gpio[*]", &s
->gpio
[i
], sizeof(s
->gpio
[i
]),
68 static void fsl_imx31_realize(DeviceState
*dev
, Error
**errp
)
70 FslIMX31State
*s
= FSL_IMX31(dev
);
74 object_property_set_bool(OBJECT(&s
->cpu
), true, "realized", &err
);
76 error_propagate(errp
, err
);
80 object_property_set_bool(OBJECT(&s
->avic
), true, "realized", &err
);
82 error_propagate(errp
, err
);
85 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->avic
), 0, FSL_IMX31_AVIC_ADDR
);
86 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->avic
), 0,
87 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_IRQ
));
88 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->avic
), 1,
89 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_FIQ
));
91 object_property_set_bool(OBJECT(&s
->ccm
), true, "realized", &err
);
93 error_propagate(errp
, err
);
96 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ccm
), 0, FSL_IMX31_CCM_ADDR
);
98 /* Initialize all UARTS */
99 for (i
= 0; i
< FSL_IMX31_NUM_UARTS
; i
++) {
100 static const struct {
103 } serial_table
[FSL_IMX31_NUM_UARTS
] = {
104 { FSL_IMX31_UART1_ADDR
, FSL_IMX31_UART1_IRQ
},
105 { FSL_IMX31_UART2_ADDR
, FSL_IMX31_UART2_IRQ
},
108 qdev_prop_set_chr(DEVICE(&s
->uart
[i
]), "chardev", serial_hd(i
));
110 object_property_set_bool(OBJECT(&s
->uart
[i
]), true, "realized", &err
);
112 error_propagate(errp
, err
);
116 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->uart
[i
]), 0, serial_table
[i
].addr
);
117 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->uart
[i
]), 0,
118 qdev_get_gpio_in(DEVICE(&s
->avic
),
119 serial_table
[i
].irq
));
122 s
->gpt
.ccm
= IMX_CCM(&s
->ccm
);
124 object_property_set_bool(OBJECT(&s
->gpt
), true, "realized", &err
);
126 error_propagate(errp
, err
);
130 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpt
), 0, FSL_IMX31_GPT_ADDR
);
131 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpt
), 0,
132 qdev_get_gpio_in(DEVICE(&s
->avic
), FSL_IMX31_GPT_IRQ
));
134 /* Initialize all EPIT timers */
135 for (i
= 0; i
< FSL_IMX31_NUM_EPITS
; i
++) {
136 static const struct {
139 } epit_table
[FSL_IMX31_NUM_EPITS
] = {
140 { FSL_IMX31_EPIT1_ADDR
, FSL_IMX31_EPIT1_IRQ
},
141 { FSL_IMX31_EPIT2_ADDR
, FSL_IMX31_EPIT2_IRQ
},
144 s
->epit
[i
].ccm
= IMX_CCM(&s
->ccm
);
146 object_property_set_bool(OBJECT(&s
->epit
[i
]), true, "realized", &err
);
148 error_propagate(errp
, err
);
152 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->epit
[i
]), 0, epit_table
[i
].addr
);
153 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->epit
[i
]), 0,
154 qdev_get_gpio_in(DEVICE(&s
->avic
),
158 /* Initialize all I2C */
159 for (i
= 0; i
< FSL_IMX31_NUM_I2CS
; i
++) {
160 static const struct {
163 } i2c_table
[FSL_IMX31_NUM_I2CS
] = {
164 { FSL_IMX31_I2C1_ADDR
, FSL_IMX31_I2C1_IRQ
},
165 { FSL_IMX31_I2C2_ADDR
, FSL_IMX31_I2C2_IRQ
},
166 { FSL_IMX31_I2C3_ADDR
, FSL_IMX31_I2C3_IRQ
}
169 /* Initialize the I2C */
170 object_property_set_bool(OBJECT(&s
->i2c
[i
]), true, "realized", &err
);
172 error_propagate(errp
, err
);
176 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->i2c
[i
]), 0, i2c_table
[i
].addr
);
177 /* Connect I2C IRQ to PIC */
178 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->i2c
[i
]), 0,
179 qdev_get_gpio_in(DEVICE(&s
->avic
),
183 /* Initialize all GPIOs */
184 for (i
= 0; i
< FSL_IMX31_NUM_GPIOS
; i
++) {
185 static const struct {
188 } gpio_table
[FSL_IMX31_NUM_GPIOS
] = {
189 { FSL_IMX31_GPIO1_ADDR
, FSL_IMX31_GPIO1_IRQ
},
190 { FSL_IMX31_GPIO2_ADDR
, FSL_IMX31_GPIO2_IRQ
},
191 { FSL_IMX31_GPIO3_ADDR
, FSL_IMX31_GPIO3_IRQ
}
194 object_property_set_bool(OBJECT(&s
->gpio
[i
]), false, "has-edge-sel",
196 object_property_set_bool(OBJECT(&s
->gpio
[i
]), true, "realized", &err
);
198 error_propagate(errp
, err
);
201 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpio
[i
]), 0, gpio_table
[i
].addr
);
202 /* Connect GPIO IRQ to PIC */
203 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpio
[i
]), 0,
204 qdev_get_gpio_in(DEVICE(&s
->avic
),
208 /* On a real system, the first 16k is a `secure boot rom' */
209 memory_region_init_rom(&s
->secure_rom
, NULL
, "imx31.secure_rom",
210 FSL_IMX31_SECURE_ROM_SIZE
, &err
);
212 error_propagate(errp
, err
);
215 memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR
,
218 /* There is also a 16k ROM */
219 memory_region_init_rom(&s
->rom
, NULL
, "imx31.rom",
220 FSL_IMX31_ROM_SIZE
, &err
);
222 error_propagate(errp
, err
);
225 memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR
,
228 /* initialize internal RAM (16 KB) */
229 memory_region_init_ram(&s
->iram
, NULL
, "imx31.iram", FSL_IMX31_IRAM_SIZE
,
232 error_propagate(errp
, err
);
235 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR
,
238 /* internal RAM (16 KB) is aliased over 256 MB - 16 KB */
239 memory_region_init_alias(&s
->iram_alias
, NULL
, "imx31.iram_alias",
240 &s
->iram
, 0, FSL_IMX31_IRAM_ALIAS_SIZE
);
241 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR
,
245 static void fsl_imx31_class_init(ObjectClass
*oc
, void *data
)
247 DeviceClass
*dc
= DEVICE_CLASS(oc
);
249 dc
->realize
= fsl_imx31_realize
;
250 dc
->desc
= "i.MX31 SOC";
252 * Reason: uses serial_hds in realize and the kzm board does not
253 * support multiple CPUs
255 dc
->user_creatable
= false;
258 static const TypeInfo fsl_imx31_type_info
= {
259 .name
= TYPE_FSL_IMX31
,
260 .parent
= TYPE_DEVICE
,
261 .instance_size
= sizeof(FslIMX31State
),
262 .instance_init
= fsl_imx31_init
,
263 .class_init
= fsl_imx31_class_init
,
266 static void fsl_imx31_register_types(void)
268 type_register_static(&fsl_imx31_type_info
);
271 type_init(fsl_imx31_register_types
)