2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
4 * i.MX31 SOC emulation.
6 * Based on hw/arm/fsl-imx31.c
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
25 #include "hw/arm/fsl-imx31.h"
26 #include "sysemu/sysemu.h"
27 #include "exec/address-spaces.h"
28 #include "hw/boards.h"
29 #include "chardev/char.h"
31 static void fsl_imx31_init(Object
*obj
)
33 FslIMX31State
*s
= FSL_IMX31(obj
);
36 object_initialize(&s
->cpu
, sizeof(s
->cpu
), "arm1136-" TYPE_ARM_CPU
);
38 sysbus_init_child_obj(obj
, "avic", &s
->avic
, sizeof(s
->avic
),
41 sysbus_init_child_obj(obj
, "ccm", &s
->ccm
, sizeof(s
->ccm
), TYPE_IMX31_CCM
);
43 for (i
= 0; i
< FSL_IMX31_NUM_UARTS
; i
++) {
44 sysbus_init_child_obj(obj
, "uart[*]", &s
->uart
[i
], sizeof(s
->uart
[i
]),
48 sysbus_init_child_obj(obj
, "gpt", &s
->gpt
, sizeof(s
->gpt
), TYPE_IMX31_GPT
);
50 for (i
= 0; i
< FSL_IMX31_NUM_EPITS
; i
++) {
51 sysbus_init_child_obj(obj
, "epit[*]", &s
->epit
[i
], sizeof(s
->epit
[i
]),
55 for (i
= 0; i
< FSL_IMX31_NUM_I2CS
; i
++) {
56 sysbus_init_child_obj(obj
, "i2c[*]", &s
->i2c
[i
], sizeof(s
->i2c
[i
]),
60 for (i
= 0; i
< FSL_IMX31_NUM_GPIOS
; i
++) {
61 sysbus_init_child_obj(obj
, "gpio[*]", &s
->gpio
[i
], sizeof(s
->gpio
[i
]),
66 static void fsl_imx31_realize(DeviceState
*dev
, Error
**errp
)
68 FslIMX31State
*s
= FSL_IMX31(dev
);
72 object_property_set_bool(OBJECT(&s
->cpu
), true, "realized", &err
);
74 error_propagate(errp
, err
);
78 object_property_set_bool(OBJECT(&s
->avic
), true, "realized", &err
);
80 error_propagate(errp
, err
);
83 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->avic
), 0, FSL_IMX31_AVIC_ADDR
);
84 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->avic
), 0,
85 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_IRQ
));
86 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->avic
), 1,
87 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_FIQ
));
89 object_property_set_bool(OBJECT(&s
->ccm
), true, "realized", &err
);
91 error_propagate(errp
, err
);
94 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ccm
), 0, FSL_IMX31_CCM_ADDR
);
96 /* Initialize all UARTS */
97 for (i
= 0; i
< FSL_IMX31_NUM_UARTS
; i
++) {
101 } serial_table
[FSL_IMX31_NUM_UARTS
] = {
102 { FSL_IMX31_UART1_ADDR
, FSL_IMX31_UART1_IRQ
},
103 { FSL_IMX31_UART2_ADDR
, FSL_IMX31_UART2_IRQ
},
106 qdev_prop_set_chr(DEVICE(&s
->uart
[i
]), "chardev", serial_hd(i
));
108 object_property_set_bool(OBJECT(&s
->uart
[i
]), true, "realized", &err
);
110 error_propagate(errp
, err
);
114 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->uart
[i
]), 0, serial_table
[i
].addr
);
115 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->uart
[i
]), 0,
116 qdev_get_gpio_in(DEVICE(&s
->avic
),
117 serial_table
[i
].irq
));
120 s
->gpt
.ccm
= IMX_CCM(&s
->ccm
);
122 object_property_set_bool(OBJECT(&s
->gpt
), true, "realized", &err
);
124 error_propagate(errp
, err
);
128 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpt
), 0, FSL_IMX31_GPT_ADDR
);
129 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpt
), 0,
130 qdev_get_gpio_in(DEVICE(&s
->avic
), FSL_IMX31_GPT_IRQ
));
132 /* Initialize all EPIT timers */
133 for (i
= 0; i
< FSL_IMX31_NUM_EPITS
; i
++) {
134 static const struct {
137 } epit_table
[FSL_IMX31_NUM_EPITS
] = {
138 { FSL_IMX31_EPIT1_ADDR
, FSL_IMX31_EPIT1_IRQ
},
139 { FSL_IMX31_EPIT2_ADDR
, FSL_IMX31_EPIT2_IRQ
},
142 s
->epit
[i
].ccm
= IMX_CCM(&s
->ccm
);
144 object_property_set_bool(OBJECT(&s
->epit
[i
]), true, "realized", &err
);
146 error_propagate(errp
, err
);
150 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->epit
[i
]), 0, epit_table
[i
].addr
);
151 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->epit
[i
]), 0,
152 qdev_get_gpio_in(DEVICE(&s
->avic
),
156 /* Initialize all I2C */
157 for (i
= 0; i
< FSL_IMX31_NUM_I2CS
; i
++) {
158 static const struct {
161 } i2c_table
[FSL_IMX31_NUM_I2CS
] = {
162 { FSL_IMX31_I2C1_ADDR
, FSL_IMX31_I2C1_IRQ
},
163 { FSL_IMX31_I2C2_ADDR
, FSL_IMX31_I2C2_IRQ
},
164 { FSL_IMX31_I2C3_ADDR
, FSL_IMX31_I2C3_IRQ
}
167 /* Initialize the I2C */
168 object_property_set_bool(OBJECT(&s
->i2c
[i
]), true, "realized", &err
);
170 error_propagate(errp
, err
);
174 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->i2c
[i
]), 0, i2c_table
[i
].addr
);
175 /* Connect I2C IRQ to PIC */
176 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->i2c
[i
]), 0,
177 qdev_get_gpio_in(DEVICE(&s
->avic
),
181 /* Initialize all GPIOs */
182 for (i
= 0; i
< FSL_IMX31_NUM_GPIOS
; i
++) {
183 static const struct {
186 } gpio_table
[FSL_IMX31_NUM_GPIOS
] = {
187 { FSL_IMX31_GPIO1_ADDR
, FSL_IMX31_GPIO1_IRQ
},
188 { FSL_IMX31_GPIO2_ADDR
, FSL_IMX31_GPIO2_IRQ
},
189 { FSL_IMX31_GPIO3_ADDR
, FSL_IMX31_GPIO3_IRQ
}
192 object_property_set_bool(OBJECT(&s
->gpio
[i
]), false, "has-edge-sel",
194 object_property_set_bool(OBJECT(&s
->gpio
[i
]), true, "realized", &err
);
196 error_propagate(errp
, err
);
199 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpio
[i
]), 0, gpio_table
[i
].addr
);
200 /* Connect GPIO IRQ to PIC */
201 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpio
[i
]), 0,
202 qdev_get_gpio_in(DEVICE(&s
->avic
),
206 /* On a real system, the first 16k is a `secure boot rom' */
207 memory_region_init_rom(&s
->secure_rom
, NULL
, "imx31.secure_rom",
208 FSL_IMX31_SECURE_ROM_SIZE
, &err
);
210 error_propagate(errp
, err
);
213 memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR
,
216 /* There is also a 16k ROM */
217 memory_region_init_rom(&s
->rom
, NULL
, "imx31.rom",
218 FSL_IMX31_ROM_SIZE
, &err
);
220 error_propagate(errp
, err
);
223 memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR
,
226 /* initialize internal RAM (16 KB) */
227 memory_region_init_ram(&s
->iram
, NULL
, "imx31.iram", FSL_IMX31_IRAM_SIZE
,
230 error_propagate(errp
, err
);
233 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR
,
236 /* internal RAM (16 KB) is aliased over 256 MB - 16 KB */
237 memory_region_init_alias(&s
->iram_alias
, NULL
, "imx31.iram_alias",
238 &s
->iram
, 0, FSL_IMX31_IRAM_ALIAS_SIZE
);
239 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR
,
243 static void fsl_imx31_class_init(ObjectClass
*oc
, void *data
)
245 DeviceClass
*dc
= DEVICE_CLASS(oc
);
247 dc
->realize
= fsl_imx31_realize
;
248 dc
->desc
= "i.MX31 SOC";
250 * Reason: uses serial_hds in realize and the kzm board does not
251 * support multiple CPUs
253 dc
->user_creatable
= false;
256 static const TypeInfo fsl_imx31_type_info
= {
257 .name
= TYPE_FSL_IMX31
,
258 .parent
= TYPE_DEVICE
,
259 .instance_size
= sizeof(FslIMX31State
),
260 .instance_init
= fsl_imx31_init
,
261 .class_init
= fsl_imx31_class_init
,
264 static void fsl_imx31_register_types(void)
266 type_register_static(&fsl_imx31_type_info
);
269 type_init(fsl_imx31_register_types
)