hw/arm/fsl-imx31.c

   1 /*
   2  * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
   3  *
   4  * i.MX31 SOC emulation.
   5  *
   6  * Based on hw/arm/fsl-imx31.c
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License as published by the
  10  *  Free Software Foundation; either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16  *  for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License along
  19  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "hw/arm/fsl-imx31.h"
  24 #include "sysemu/sysemu.h"
  25 #include "exec/address-spaces.h"
  26 #include "hw/boards.h"
  27 #include "sysemu/char.h"
  28
  29 static void fsl_imx31_init(Object *obj)
  30 {
  31     FslIMX31State *s = FSL_IMX31(obj);
  32     int i;
  33
  34     object_initialize(&s->cpu, sizeof(s->cpu), "arm1136-" TYPE_ARM_CPU);
  35
  36     object_initialize(&s->avic, sizeof(s->avic), TYPE_IMX_AVIC);
  37     qdev_set_parent_bus(DEVICE(&s->avic), sysbus_get_default());
  38
  39     object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX31_CCM);
  40     qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default());
  41
  42     for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
  43         object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL);
  44         qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
  45     }
  46
  47     object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX_GPT);
  48     qdev_set_parent_bus(DEVICE(&s->gpt), sysbus_get_default());
  49
  50     for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
  51         object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT);
  52         qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default());
  53     }
  54
  55     for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
  56         object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C);
  57         qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default());
  58     }
  59
  60     for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
  61         object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO);
  62         qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default());
  63     }
  64 }
  65
  66 static void fsl_imx31_realize(DeviceState *dev, Error **errp)
  67 {
  68     FslIMX31State *s = FSL_IMX31(dev);
  69     uint16_t i;
  70     Error *err = NULL;
  71
  72     object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
  73     if (err) {
  74         error_propagate(errp, err);
  75         return;
  76     }
  77
  78     object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
  79     if (err) {
  80         error_propagate(errp, err);
  81         return;
  82     }
  83     sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR);
  84     sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
  85                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
  86     sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
  87                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
  88
  89     object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
  90     if (err) {
  91         error_propagate(errp, err);
  92         return;
  93     }
  94     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR);
  95
  96     /* Initialize all UARTS */
  97     for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
  98         static const struct {
  99             hwaddr addr;
 100             unsigned int irq;
 101         } serial_table[FSL_IMX31_NUM_UARTS] = {
 102             { FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ },
 103             { FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ },
 104         };
 105
 106         if (i < MAX_SERIAL_PORTS) {
 107             CharDriverState *chr;
 108
 109             chr = serial_hds[i];
 110
 111             if (!chr) {
 112                 char label[20];
 113                 snprintf(label, sizeof(label), "imx31.uart%d", i);
 114                 chr = qemu_chr_new(label, "null", NULL);
 115             }
 116
 117             qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
 118         }
 119
 120         object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
 121         if (err) {
 122             error_propagate(errp, err);
 123             return;
 124         }
 125
 126         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
 127         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 128                            qdev_get_gpio_in(DEVICE(&s->avic),
 129                                             serial_table[i].irq));
 130     }
 131
 132     s->gpt.ccm = IMX_CCM(&s->ccm);
 133
 134     object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
 135     if (err) {
 136         error_propagate(errp, err);
 137         return;
 138     }
 139
 140     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR);
 141     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
 142                        qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ));
 143
 144     /* Initialize all EPIT timers */
 145     for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
 146         static const struct {
 147             hwaddr addr;
 148             unsigned int irq;
 149         } epit_table[FSL_IMX31_NUM_EPITS] = {
 150             { FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ },
 151             { FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ },
 152         };
 153
 154         s->epit[i].ccm = IMX_CCM(&s->ccm);
 155
 156         object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
 157         if (err) {
 158             error_propagate(errp, err);
 159             return;
 160         }
 161
 162         sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
 163         sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
 164                            qdev_get_gpio_in(DEVICE(&s->avic),
 165                                             epit_table[i].irq));
 166     }
 167
 168     /* Initialize all I2C */
 169     for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
 170         static const struct {
 171             hwaddr addr;
 172             unsigned int irq;
 173         } i2c_table[FSL_IMX31_NUM_I2CS] = {
 174             { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ },
 175             { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ },
 176             { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ }
 177         };
 178
 179         /* Initialize the I2C */
 180         object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
 181         if (err) {
 182             error_propagate(errp, err);
 183             return;
 184         }
 185         /* Map I2C memory */
 186         sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
 187         /* Connect I2C IRQ to PIC */
 188         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
 189                            qdev_get_gpio_in(DEVICE(&s->avic),
 190                                             i2c_table[i].irq));
 191     }
 192
 193     /* Initialize all GPIOs */
 194     for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
 195         static const struct {
 196             hwaddr addr;
 197             unsigned int irq;
 198         } gpio_table[FSL_IMX31_NUM_GPIOS] = {
 199             { FSL_IMX31_GPIO1_ADDR, FSL_IMX31_GPIO1_IRQ },
 200             { FSL_IMX31_GPIO2_ADDR, FSL_IMX31_GPIO2_IRQ },
 201             { FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ }
 202         };
 203
 204         object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel",
 205                                  &error_abort);
 206         object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
 207         if (err) {
 208             error_propagate(errp, err);
 209             return;
 210         }
 211         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
 212         /* Connect GPIO IRQ to PIC */
 213         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
 214                            qdev_get_gpio_in(DEVICE(&s->avic),
 215                                             gpio_table[i].irq));
 216     }
 217
 218     /* On a real system, the first 16k is a `secure boot rom' */
 219     memory_region_init_rom_device(&s->secure_rom, NULL, NULL, NULL,
 220                                   "imx31.secure_rom",
 221                                   FSL_IMX31_SECURE_ROM_SIZE, &err);
 222     if (err) {
 223         error_propagate(errp, err);
 224         return;
 225     }
 226     memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR,
 227                                 &s->secure_rom);
 228
 229     /* There is also a 16k ROM */
 230     memory_region_init_rom_device(&s->rom, NULL, NULL, NULL, "imx31.rom",
 231                                   FSL_IMX31_ROM_SIZE, &err);
 232     if (err) {
 233         error_propagate(errp, err);
 234         return;
 235     }
 236     memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR,
 237                                 &s->rom);
 238
 239     /* initialize internal RAM (16 KB) */
 240     memory_region_init_ram(&s->iram, NULL, "imx31.iram", FSL_IMX31_IRAM_SIZE,
 241                            &err);
 242     if (err) {
 243         error_propagate(errp, err);
 244         return;
 245     }
 246     memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR,
 247                                 &s->iram);
 248     vmstate_register_ram_global(&s->iram);
 249
 250     /* internal RAM (16 KB) is aliased over 256 MB - 16 KB */
 251     memory_region_init_alias(&s->iram_alias, NULL, "imx31.iram_alias",
 252                              &s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE);
 253     memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR,
 254                                 &s->iram_alias);
 255 }
 256
 257 static void fsl_imx31_class_init(ObjectClass *oc, void *data)
 258 {
 259     DeviceClass *dc = DEVICE_CLASS(oc);
 260
 261     dc->realize = fsl_imx31_realize;
 262
 263     /*
 264      * Reason: creates an ARM CPU, thus use after free(), see
 265      * arm_cpu_class_init()
 266      */
 267     dc->cannot_destroy_with_object_finalize_yet = true;
 268     dc->desc = "i.MX31 SOC";
 269 }
 270
 271 static const TypeInfo fsl_imx31_type_info = {
 272     .name = TYPE_FSL_IMX31,
 273     .parent = TYPE_DEVICE,
 274     .instance_size = sizeof(FslIMX31State),
 275     .instance_init = fsl_imx31_init,
 276     .class_init = fsl_imx31_class_init,
 277 };
 278
 279 static void fsl_imx31_register_types(void)
 280 {
 281     type_register_static(&fsl_imx31_type_info);
 282 }
 283
 284 type_init(fsl_imx31_register_types)