hw/arm/fsl-imx31.c

   1 /*
   2  * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
   3  *
   4  * i.MX31 SOC emulation.
   5  *
   6  * Based on hw/arm/fsl-imx31.c
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License as published by the
  10  *  Free Software Foundation; either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16  *  for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License along
  19  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "qapi/error.h"
  24 #include "cpu.h"
  25 #include "hw/arm/fsl-imx31.h"
  26 #include "sysemu/sysemu.h"
  27 #include "exec/address-spaces.h"
  28 #include "hw/boards.h"
  29 #include "chardev/char.h"
  30
  31 static void fsl_imx31_init(Object *obj)
  32 {
  33     FslIMX31State *s = FSL_IMX31(obj);
  34     int i;
  35
  36     object_initialize(&s->cpu, sizeof(s->cpu), "arm1136-" TYPE_ARM_CPU);
  37
  38     sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic),
  39                           TYPE_IMX_AVIC);
  40
  41     sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX31_CCM);
  42
  43     for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
  44         sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]),
  45                               TYPE_IMX_SERIAL);
  46     }
  47
  48     sysbus_init_child_obj(obj, "gpt", &s->gpt, sizeof(s->gpt), TYPE_IMX31_GPT);
  49
  50     for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
  51         sysbus_init_child_obj(obj, "epit[*]", &s->epit[i], sizeof(s->epit[i]),
  52                               TYPE_IMX_EPIT);
  53     }
  54
  55     for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
  56         sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]),
  57                               TYPE_IMX_I2C);
  58     }
  59
  60     for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
  61         sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
  62                               TYPE_IMX_GPIO);
  63     }
  64 }
  65
  66 static void fsl_imx31_realize(DeviceState *dev, Error **errp)
  67 {
  68     FslIMX31State *s = FSL_IMX31(dev);
  69     uint16_t i;
  70     Error *err = NULL;
  71
  72     object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
  73     if (err) {
  74         error_propagate(errp, err);
  75         return;
  76     }
  77
  78     object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
  79     if (err) {
  80         error_propagate(errp, err);
  81         return;
  82     }
  83     sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR);
  84     sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
  85                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
  86     sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
  87                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
  88
  89     object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
  90     if (err) {
  91         error_propagate(errp, err);
  92         return;
  93     }
  94     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR);
  95
  96     /* Initialize all UARTS */
  97     for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
  98         static const struct {
  99             hwaddr addr;
 100             unsigned int irq;
 101         } serial_table[FSL_IMX31_NUM_UARTS] = {
 102             { FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ },
 103             { FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ },
 104         };
 105
 106         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
 107
 108         object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
 109         if (err) {
 110             error_propagate(errp, err);
 111             return;
 112         }
 113
 114         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
 115         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 116                            qdev_get_gpio_in(DEVICE(&s->avic),
 117                                             serial_table[i].irq));
 118     }
 119
 120     s->gpt.ccm = IMX_CCM(&s->ccm);
 121
 122     object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
 123     if (err) {
 124         error_propagate(errp, err);
 125         return;
 126     }
 127
 128     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR);
 129     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
 130                        qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ));
 131
 132     /* Initialize all EPIT timers */
 133     for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
 134         static const struct {
 135             hwaddr addr;
 136             unsigned int irq;
 137         } epit_table[FSL_IMX31_NUM_EPITS] = {
 138             { FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ },
 139             { FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ },
 140         };
 141
 142         s->epit[i].ccm = IMX_CCM(&s->ccm);
 143
 144         object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
 145         if (err) {
 146             error_propagate(errp, err);
 147             return;
 148         }
 149
 150         sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
 151         sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
 152                            qdev_get_gpio_in(DEVICE(&s->avic),
 153                                             epit_table[i].irq));
 154     }
 155
 156     /* Initialize all I2C */
 157     for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
 158         static const struct {
 159             hwaddr addr;
 160             unsigned int irq;
 161         } i2c_table[FSL_IMX31_NUM_I2CS] = {
 162             { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ },
 163             { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ },
 164             { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ }
 165         };
 166
 167         /* Initialize the I2C */
 168         object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
 169         if (err) {
 170             error_propagate(errp, err);
 171             return;
 172         }
 173         /* Map I2C memory */
 174         sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
 175         /* Connect I2C IRQ to PIC */
 176         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
 177                            qdev_get_gpio_in(DEVICE(&s->avic),
 178                                             i2c_table[i].irq));
 179     }
 180
 181     /* Initialize all GPIOs */
 182     for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
 183         static const struct {
 184             hwaddr addr;
 185             unsigned int irq;
 186         } gpio_table[FSL_IMX31_NUM_GPIOS] = {
 187             { FSL_IMX31_GPIO1_ADDR, FSL_IMX31_GPIO1_IRQ },
 188             { FSL_IMX31_GPIO2_ADDR, FSL_IMX31_GPIO2_IRQ },
 189             { FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ }
 190         };
 191
 192         object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel",
 193                                  &error_abort);
 194         object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
 195         if (err) {
 196             error_propagate(errp, err);
 197             return;
 198         }
 199         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
 200         /* Connect GPIO IRQ to PIC */
 201         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
 202                            qdev_get_gpio_in(DEVICE(&s->avic),
 203                                             gpio_table[i].irq));
 204     }
 205
 206     /* On a real system, the first 16k is a `secure boot rom' */
 207     memory_region_init_rom(&s->secure_rom, NULL, "imx31.secure_rom",
 208                            FSL_IMX31_SECURE_ROM_SIZE, &err);
 209     if (err) {
 210         error_propagate(errp, err);
 211         return;
 212     }
 213     memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR,
 214                                 &s->secure_rom);
 215
 216     /* There is also a 16k ROM */
 217     memory_region_init_rom(&s->rom, NULL, "imx31.rom",
 218                            FSL_IMX31_ROM_SIZE, &err);
 219     if (err) {
 220         error_propagate(errp, err);
 221         return;
 222     }
 223     memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR,
 224                                 &s->rom);
 225
 226     /* initialize internal RAM (16 KB) */
 227     memory_region_init_ram(&s->iram, NULL, "imx31.iram", FSL_IMX31_IRAM_SIZE,
 228                            &err);
 229     if (err) {
 230         error_propagate(errp, err);
 231         return;
 232     }
 233     memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR,
 234                                 &s->iram);
 235
 236     /* internal RAM (16 KB) is aliased over 256 MB - 16 KB */
 237     memory_region_init_alias(&s->iram_alias, NULL, "imx31.iram_alias",
 238                              &s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE);
 239     memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR,
 240                                 &s->iram_alias);
 241 }
 242
 243 static void fsl_imx31_class_init(ObjectClass *oc, void *data)
 244 {
 245     DeviceClass *dc = DEVICE_CLASS(oc);
 246
 247     dc->realize = fsl_imx31_realize;
 248     dc->desc = "i.MX31 SOC";
 249     /*
 250      * Reason: uses serial_hds in realize and the kzm board does not
 251      * support multiple CPUs
 252      */
 253     dc->user_creatable = false;
 254 }
 255
 256 static const TypeInfo fsl_imx31_type_info = {
 257     .name = TYPE_FSL_IMX31,
 258     .parent = TYPE_DEVICE,
 259     .instance_size = sizeof(FslIMX31State),
 260     .instance_init = fsl_imx31_init,
 261     .class_init = fsl_imx31_class_init,
 262 };
 263
 264 static void fsl_imx31_register_types(void)
 265 {
 266     type_register_static(&fsl_imx31_type_info);
 267 }
 268
 269 type_init(fsl_imx31_register_types)