hw/arm/fsl-imx31.c

   1 /*
   2  * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
   3  *
   4  * i.MX31 SOC emulation.
   5  *
   6  * Based on hw/arm/fsl-imx31.c
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License as published by the
  10  *  Free Software Foundation; either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16  *  for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License along
  19  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "qapi/error.h"
  24 #include "cpu.h"
  25 #include "hw/arm/fsl-imx31.h"
  26 #include "sysemu/sysemu.h"
  27 #include "exec/address-spaces.h"
  28 #include "hw/qdev-properties.h"
  29 #include "chardev/char.h"
  30
  31 static void fsl_imx31_init(Object *obj)
  32 {
  33     FslIMX31State *s = FSL_IMX31(obj);
  34     int i;
  35
  36     object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm1136"));
  37
  38     object_initialize_child(obj, "avic", &s->avic, TYPE_IMX_AVIC);
  39
  40     object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX31_CCM);
  41
  42     for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
  43         object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_IMX_SERIAL);
  44     }
  45
  46     object_initialize_child(obj, "gpt", &s->gpt, TYPE_IMX31_GPT);
  47
  48     for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
  49         object_initialize_child(obj, "epit[*]", &s->epit[i], TYPE_IMX_EPIT);
  50     }
  51
  52     for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
  53         object_initialize_child(obj, "i2c[*]", &s->i2c[i], TYPE_IMX_I2C);
  54     }
  55
  56     for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
  57         object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_IMX_GPIO);
  58     }
  59
  60     object_initialize_child(obj, "wdt", &s->wdt, TYPE_IMX2_WDT);
  61 }
  62
  63 static void fsl_imx31_realize(DeviceState *dev, Error **errp)
  64 {
  65     FslIMX31State *s = FSL_IMX31(dev);
  66     uint16_t i;
  67     Error *err = NULL;
  68
  69     qdev_realize(DEVICE(&s->cpu), NULL, &err);
  70     if (err) {
  71         error_propagate(errp, err);
  72         return;
  73     }
  74
  75     sysbus_realize(SYS_BUS_DEVICE(&s->avic), &err);
  76     if (err) {
  77         error_propagate(errp, err);
  78         return;
  79     }
  80     sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR);
  81     sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
  82                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
  83     sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
  84                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
  85
  86     sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &err);
  87     if (err) {
  88         error_propagate(errp, err);
  89         return;
  90     }
  91     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR);
  92
  93     /* Initialize all UARTS */
  94     for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
  95         static const struct {
  96             hwaddr addr;
  97             unsigned int irq;
  98         } serial_table[FSL_IMX31_NUM_UARTS] = {
  99             { FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ },
 100             { FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ },
 101         };
 102
 103         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
 104
 105         sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &err);
 106         if (err) {
 107             error_propagate(errp, err);
 108             return;
 109         }
 110
 111         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
 112         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 113                            qdev_get_gpio_in(DEVICE(&s->avic),
 114                                             serial_table[i].irq));
 115     }
 116
 117     s->gpt.ccm = IMX_CCM(&s->ccm);
 118
 119     sysbus_realize(SYS_BUS_DEVICE(&s->gpt), &err);
 120     if (err) {
 121         error_propagate(errp, err);
 122         return;
 123     }
 124
 125     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR);
 126     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
 127                        qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ));
 128
 129     /* Initialize all EPIT timers */
 130     for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
 131         static const struct {
 132             hwaddr addr;
 133             unsigned int irq;
 134         } epit_table[FSL_IMX31_NUM_EPITS] = {
 135             { FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ },
 136             { FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ },
 137         };
 138
 139         s->epit[i].ccm = IMX_CCM(&s->ccm);
 140
 141         sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &err);
 142         if (err) {
 143             error_propagate(errp, err);
 144             return;
 145         }
 146
 147         sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
 148         sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
 149                            qdev_get_gpio_in(DEVICE(&s->avic),
 150                                             epit_table[i].irq));
 151     }
 152
 153     /* Initialize all I2C */
 154     for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
 155         static const struct {
 156             hwaddr addr;
 157             unsigned int irq;
 158         } i2c_table[FSL_IMX31_NUM_I2CS] = {
 159             { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ },
 160             { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ },
 161             { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ }
 162         };
 163
 164         /* Initialize the I2C */
 165         sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &err);
 166         if (err) {
 167             error_propagate(errp, err);
 168             return;
 169         }
 170         /* Map I2C memory */
 171         sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
 172         /* Connect I2C IRQ to PIC */
 173         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
 174                            qdev_get_gpio_in(DEVICE(&s->avic),
 175                                             i2c_table[i].irq));
 176     }
 177
 178     /* Initialize all GPIOs */
 179     for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
 180         static const struct {
 181             hwaddr addr;
 182             unsigned int irq;
 183         } gpio_table[FSL_IMX31_NUM_GPIOS] = {
 184             { FSL_IMX31_GPIO1_ADDR, FSL_IMX31_GPIO1_IRQ },
 185             { FSL_IMX31_GPIO2_ADDR, FSL_IMX31_GPIO2_IRQ },
 186             { FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ }
 187         };
 188
 189         object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel",
 190                                  &error_abort);
 191         sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &err);
 192         if (err) {
 193             error_propagate(errp, err);
 194             return;
 195         }
 196         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
 197         /* Connect GPIO IRQ to PIC */
 198         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
 199                            qdev_get_gpio_in(DEVICE(&s->avic),
 200                                             gpio_table[i].irq));
 201     }
 202
 203     /* Watchdog */
 204     sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_abort);
 205     sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX31_WDT_ADDR);
 206
 207     /* On a real system, the first 16k is a `secure boot rom' */
 208     memory_region_init_rom(&s->secure_rom, OBJECT(dev), "imx31.secure_rom",
 209                            FSL_IMX31_SECURE_ROM_SIZE, &err);
 210     if (err) {
 211         error_propagate(errp, err);
 212         return;
 213     }
 214     memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR,
 215                                 &s->secure_rom);
 216
 217     /* There is also a 16k ROM */
 218     memory_region_init_rom(&s->rom, OBJECT(dev), "imx31.rom",
 219                            FSL_IMX31_ROM_SIZE, &err);
 220     if (err) {
 221         error_propagate(errp, err);
 222         return;
 223     }
 224     memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR,
 225                                 &s->rom);
 226
 227     /* initialize internal RAM (16 KB) */
 228     memory_region_init_ram(&s->iram, NULL, "imx31.iram", FSL_IMX31_IRAM_SIZE,
 229                            &err);
 230     if (err) {
 231         error_propagate(errp, err);
 232         return;
 233     }
 234     memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR,
 235                                 &s->iram);
 236
 237     /* internal RAM (16 KB) is aliased over 256 MB - 16 KB */
 238     memory_region_init_alias(&s->iram_alias, OBJECT(dev), "imx31.iram_alias",
 239                              &s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE);
 240     memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR,
 241                                 &s->iram_alias);
 242 }
 243
 244 static void fsl_imx31_class_init(ObjectClass *oc, void *data)
 245 {
 246     DeviceClass *dc = DEVICE_CLASS(oc);
 247
 248     dc->realize = fsl_imx31_realize;
 249     dc->desc = "i.MX31 SOC";
 250     /*
 251      * Reason: uses serial_hds in realize and the kzm board does not
 252      * support multiple CPUs
 253      */
 254     dc->user_creatable = false;
 255 }
 256
 257 static const TypeInfo fsl_imx31_type_info = {
 258     .name = TYPE_FSL_IMX31,
 259     .parent = TYPE_DEVICE,
 260     .instance_size = sizeof(FslIMX31State),
 261     .instance_init = fsl_imx31_init,
 262     .class_init = fsl_imx31_class_init,
 263 };
 264
 265 static void fsl_imx31_register_types(void)
 266 {
 267     type_register_static(&fsl_imx31_type_info);
 268 }
 269
 270 type_init(fsl_imx31_register_types)