hw/arm/fsl-imx6ul.c

   1 /*
   2  * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
   3  *
   4  * i.MX6UL SOC emulation.
   5  *
   6  * Based on hw/arm/fsl-imx7.c
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "qapi/error.h"
  21 #include "hw/arm/fsl-imx6ul.h"
  22 #include "hw/misc/unimp.h"
  23 #include "hw/usb/imx-usb-phy.h"
  24 #include "hw/boards.h"
  25 #include "sysemu/sysemu.h"
  26 #include "qemu/error-report.h"
  27 #include "qemu/module.h"
  28
  29 #define NAME_SIZE 20
  30
  31 static void fsl_imx6ul_init(Object *obj)
  32 {
  33     FslIMX6ULState *s = FSL_IMX6UL(obj);
  34     char name[NAME_SIZE];
  35     int i;
  36
  37     object_initialize_child(obj, "cpu0", &s->cpu,
  38                             ARM_CPU_TYPE_NAME("cortex-a7"));
  39
  40     /*
  41      * A7MPCORE
  42      */
  43     object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
  44                             TYPE_A15MPCORE_PRIV);
  45
  46     /*
  47      * CCM
  48      */
  49     object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6UL_CCM);
  50
  51     /*
  52      * SRC
  53      */
  54     object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC);
  55
  56     /*
  57      * GPCv2
  58      */
  59     object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
  60
  61     /*
  62      * SNVS
  63      */
  64     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
  65
  66     /*
  67      * GPIOs
  68      */
  69     for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
  70         snprintf(name, NAME_SIZE, "gpio%d", i);
  71         object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
  72     }
  73
  74     /*
  75      * GPTs
  76      */
  77     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
  78         snprintf(name, NAME_SIZE, "gpt%d", i);
  79         object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX6UL_GPT);
  80     }
  81
  82     /*
  83      * EPITs
  84      */
  85     for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
  86         snprintf(name, NAME_SIZE, "epit%d", i + 1);
  87         object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT);
  88     }
  89
  90     /*
  91      * eCSPIs
  92      */
  93     for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
  94         snprintf(name, NAME_SIZE, "spi%d", i + 1);
  95         object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
  96     }
  97
  98     /*
  99      * I2Cs
 100      */
 101     for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
 102         snprintf(name, NAME_SIZE, "i2c%d", i + 1);
 103         object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
 104     }
 105
 106     /*
 107      * UARTs
 108      */
 109     for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
 110         snprintf(name, NAME_SIZE, "uart%d", i);
 111         object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
 112     }
 113
 114     /*
 115      * Ethernets
 116      */
 117     for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
 118         snprintf(name, NAME_SIZE, "eth%d", i);
 119         object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
 120     }
 121
 122     /*
 123      * USB PHYs
 124      */
 125     for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
 126         snprintf(name, NAME_SIZE, "usbphy%d", i);
 127         object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
 128     }
 129
 130     /*
 131      * USBs
 132      */
 133     for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
 134         snprintf(name, NAME_SIZE, "usb%d", i);
 135         object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
 136     }
 137
 138     /*
 139      * SDHCIs
 140      */
 141     for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
 142         snprintf(name, NAME_SIZE, "usdhc%d", i);
 143         object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
 144     }
 145
 146     /*
 147      * Watchdogs
 148      */
 149     for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
 150         snprintf(name, NAME_SIZE, "wdt%d", i);
 151         object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
 152     }
 153 }
 154
 155 static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
 156 {
 157     MachineState *ms = MACHINE(qdev_get_machine());
 158     FslIMX6ULState *s = FSL_IMX6UL(dev);
 159     int i;
 160     char name[NAME_SIZE];
 161     SysBusDevice *sbd;
 162     DeviceState *d;
 163
 164     if (ms->smp.cpus > 1) {
 165         error_setg(errp, "%s: Only a single CPU is supported (%d requested)",
 166                    TYPE_FSL_IMX6UL, ms->smp.cpus);
 167         return;
 168     }
 169
 170     qdev_realize(DEVICE(&s->cpu), NULL, &error_abort);
 171
 172     /*
 173      * A7MPCORE
 174      */
 175     object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", 1, &error_abort);
 176     object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
 177                             FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL, &error_abort);
 178     sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
 179     sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR);
 180
 181     sbd = SYS_BUS_DEVICE(&s->a7mpcore);
 182     d = DEVICE(&s->cpu);
 183
 184     sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(d, ARM_CPU_IRQ));
 185     sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(d, ARM_CPU_FIQ));
 186     sysbus_connect_irq(sbd, 2, qdev_get_gpio_in(d, ARM_CPU_VIRQ));
 187     sysbus_connect_irq(sbd, 3, qdev_get_gpio_in(d, ARM_CPU_VFIQ));
 188
 189     /*
 190      * A7MPCORE DAP
 191      */
 192     create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
 193                                 FSL_IMX6UL_A7MPCORE_DAP_SIZE);
 194
 195     /*
 196      * GPTs
 197      */
 198     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
 199         static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = {
 200             FSL_IMX6UL_GPT1_ADDR,
 201             FSL_IMX6UL_GPT2_ADDR,
 202         };
 203
 204         static const int FSL_IMX6UL_GPTn_IRQ[FSL_IMX6UL_NUM_GPTS] = {
 205             FSL_IMX6UL_GPT1_IRQ,
 206             FSL_IMX6UL_GPT2_IRQ,
 207         };
 208
 209         s->gpt[i].ccm = IMX_CCM(&s->ccm);
 210         sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort);
 211
 212         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0,
 213                         FSL_IMX6UL_GPTn_ADDR[i]);
 214
 215         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
 216                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 217                                             FSL_IMX6UL_GPTn_IRQ[i]));
 218     }
 219
 220     /*
 221      * EPITs
 222      */
 223     for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
 224         static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = {
 225             FSL_IMX6UL_EPIT1_ADDR,
 226             FSL_IMX6UL_EPIT2_ADDR,
 227         };
 228
 229         static const int FSL_IMX6UL_EPITn_IRQ[FSL_IMX6UL_NUM_EPITS] = {
 230             FSL_IMX6UL_EPIT1_IRQ,
 231             FSL_IMX6UL_EPIT2_IRQ,
 232         };
 233
 234         s->epit[i].ccm = IMX_CCM(&s->ccm);
 235         sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &error_abort);
 236
 237         sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0,
 238                         FSL_IMX6UL_EPITn_ADDR[i]);
 239
 240         sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
 241                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 242                                             FSL_IMX6UL_EPITn_IRQ[i]));
 243     }
 244
 245     /*
 246      * GPIOs
 247      */
 248     for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
 249         static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = {
 250             FSL_IMX6UL_GPIO1_ADDR,
 251             FSL_IMX6UL_GPIO2_ADDR,
 252             FSL_IMX6UL_GPIO3_ADDR,
 253             FSL_IMX6UL_GPIO4_ADDR,
 254             FSL_IMX6UL_GPIO5_ADDR,
 255         };
 256
 257         static const int FSL_IMX6UL_GPIOn_LOW_IRQ[FSL_IMX6UL_NUM_GPIOS] = {
 258             FSL_IMX6UL_GPIO1_LOW_IRQ,
 259             FSL_IMX6UL_GPIO2_LOW_IRQ,
 260             FSL_IMX6UL_GPIO3_LOW_IRQ,
 261             FSL_IMX6UL_GPIO4_LOW_IRQ,
 262             FSL_IMX6UL_GPIO5_LOW_IRQ,
 263         };
 264
 265         static const int FSL_IMX6UL_GPIOn_HIGH_IRQ[FSL_IMX6UL_NUM_GPIOS] = {
 266             FSL_IMX6UL_GPIO1_HIGH_IRQ,
 267             FSL_IMX6UL_GPIO2_HIGH_IRQ,
 268             FSL_IMX6UL_GPIO3_HIGH_IRQ,
 269             FSL_IMX6UL_GPIO4_HIGH_IRQ,
 270             FSL_IMX6UL_GPIO5_HIGH_IRQ,
 271         };
 272
 273         sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort);
 274
 275         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0,
 276                         FSL_IMX6UL_GPIOn_ADDR[i]);
 277
 278         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
 279                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 280                                             FSL_IMX6UL_GPIOn_LOW_IRQ[i]));
 281
 282         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
 283                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 284                                             FSL_IMX6UL_GPIOn_HIGH_IRQ[i]));
 285     }
 286
 287     /*
 288      * IOMUXC
 289      */
 290     create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR,
 291                                 FSL_IMX6UL_IOMUXC_SIZE);
 292     create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR,
 293                                 FSL_IMX6UL_IOMUXC_GPR_SIZE);
 294
 295     /*
 296      * CCM
 297      */
 298     sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_abort);
 299     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6UL_CCM_ADDR);
 300
 301     /*
 302      * SRC
 303      */
 304     sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort);
 305     sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6UL_SRC_ADDR);
 306
 307     /*
 308      * GPCv2
 309      */
 310     sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
 311     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
 312
 313     /*
 314      * ECSPIs
 315      */
 316     for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
 317         static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
 318             FSL_IMX6UL_ECSPI1_ADDR,
 319             FSL_IMX6UL_ECSPI2_ADDR,
 320             FSL_IMX6UL_ECSPI3_ADDR,
 321             FSL_IMX6UL_ECSPI4_ADDR,
 322         };
 323
 324         static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = {
 325             FSL_IMX6UL_ECSPI1_IRQ,
 326             FSL_IMX6UL_ECSPI2_IRQ,
 327             FSL_IMX6UL_ECSPI3_IRQ,
 328             FSL_IMX6UL_ECSPI4_IRQ,
 329         };
 330
 331         /* Initialize the SPI */
 332         sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &error_abort);
 333
 334         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
 335                         FSL_IMX6UL_SPIn_ADDR[i]);
 336
 337         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
 338                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 339                                             FSL_IMX6UL_SPIn_IRQ[i]));
 340     }
 341
 342     /*
 343      * I2Cs
 344      */
 345     for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
 346         static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = {
 347             FSL_IMX6UL_I2C1_ADDR,
 348             FSL_IMX6UL_I2C2_ADDR,
 349             FSL_IMX6UL_I2C3_ADDR,
 350             FSL_IMX6UL_I2C4_ADDR,
 351         };
 352
 353         static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = {
 354             FSL_IMX6UL_I2C1_IRQ,
 355             FSL_IMX6UL_I2C2_IRQ,
 356             FSL_IMX6UL_I2C3_IRQ,
 357             FSL_IMX6UL_I2C4_IRQ,
 358         };
 359
 360         sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &error_abort);
 361         sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX6UL_I2Cn_ADDR[i]);
 362
 363         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
 364                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 365                                             FSL_IMX6UL_I2Cn_IRQ[i]));
 366     }
 367
 368     /*
 369      * UARTs
 370      */
 371     for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
 372         static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = {
 373             FSL_IMX6UL_UART1_ADDR,
 374             FSL_IMX6UL_UART2_ADDR,
 375             FSL_IMX6UL_UART3_ADDR,
 376             FSL_IMX6UL_UART4_ADDR,
 377             FSL_IMX6UL_UART5_ADDR,
 378             FSL_IMX6UL_UART6_ADDR,
 379             FSL_IMX6UL_UART7_ADDR,
 380             FSL_IMX6UL_UART8_ADDR,
 381         };
 382
 383         static const int FSL_IMX6UL_UARTn_IRQ[FSL_IMX6UL_NUM_UARTS] = {
 384             FSL_IMX6UL_UART1_IRQ,
 385             FSL_IMX6UL_UART2_IRQ,
 386             FSL_IMX6UL_UART3_IRQ,
 387             FSL_IMX6UL_UART4_IRQ,
 388             FSL_IMX6UL_UART5_IRQ,
 389             FSL_IMX6UL_UART6_IRQ,
 390             FSL_IMX6UL_UART7_IRQ,
 391             FSL_IMX6UL_UART8_IRQ,
 392         };
 393
 394         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
 395
 396         sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &error_abort);
 397
 398         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0,
 399                         FSL_IMX6UL_UARTn_ADDR[i]);
 400
 401         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 402                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 403                                             FSL_IMX6UL_UARTn_IRQ[i]));
 404     }
 405
 406     /*
 407      * Ethernets
 408      *
 409      * We must use two loops since phy_connected affects the other interface
 410      * and we have to set all properties before calling sysbus_realize().
 411      */
 412     for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
 413         object_property_set_bool(OBJECT(&s->eth[i]), "phy-connected",
 414                                  s->phy_connected[i], &error_abort);
 415         /*
 416          * If the MDIO bus on this controller is not connected, assume the
 417          * other controller provides support for it.
 418          */
 419         if (!s->phy_connected[i]) {
 420             object_property_set_link(OBJECT(&s->eth[1 - i]), "phy-consumer",
 421                                      OBJECT(&s->eth[i]), &error_abort);
 422         }
 423     }
 424
 425     for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
 426         static const hwaddr FSL_IMX6UL_ENETn_ADDR[FSL_IMX6UL_NUM_ETHS] = {
 427             FSL_IMX6UL_ENET1_ADDR,
 428             FSL_IMX6UL_ENET2_ADDR,
 429         };
 430
 431         static const int FSL_IMX6UL_ENETn_IRQ[FSL_IMX6UL_NUM_ETHS] = {
 432             FSL_IMX6UL_ENET1_IRQ,
 433             FSL_IMX6UL_ENET2_IRQ,
 434         };
 435
 436         static const int FSL_IMX6UL_ENETn_TIMER_IRQ[FSL_IMX6UL_NUM_ETHS] = {
 437             FSL_IMX6UL_ENET1_TIMER_IRQ,
 438             FSL_IMX6UL_ENET2_TIMER_IRQ,
 439         };
 440
 441         object_property_set_uint(OBJECT(&s->eth[i]), "phy-num",
 442                                  s->phy_num[i], &error_abort);
 443         object_property_set_uint(OBJECT(&s->eth[i]), "tx-ring-num",
 444                                  FSL_IMX6UL_ETH_NUM_TX_RINGS, &error_abort);
 445         qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]);
 446         sysbus_realize(SYS_BUS_DEVICE(&s->eth[i]), &error_abort);
 447
 448         sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0,
 449                         FSL_IMX6UL_ENETn_ADDR[i]);
 450
 451         sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0,
 452                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 453                                             FSL_IMX6UL_ENETn_IRQ[i]));
 454
 455         sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1,
 456                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 457                                             FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
 458     }
 459
 460     /*
 461      * USB PHYs
 462      */
 463     for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
 464         static const hwaddr
 465                      FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] = {
 466             FSL_IMX6UL_USBPHY1_ADDR,
 467             FSL_IMX6UL_USBPHY2_ADDR,
 468         };
 469
 470         sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
 471         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
 472                         FSL_IMX6UL_USB_PHYn_ADDR[i]);
 473     }
 474
 475     /*
 476      * USBs
 477      */
 478     for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
 479         static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS] = {
 480             FSL_IMX6UL_USBO2_USB1_ADDR,
 481             FSL_IMX6UL_USBO2_USB2_ADDR,
 482         };
 483
 484         static const int FSL_IMX6UL_USBn_IRQ[] = {
 485             FSL_IMX6UL_USB1_IRQ,
 486             FSL_IMX6UL_USB2_IRQ,
 487         };
 488
 489         sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
 490         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
 491                         FSL_IMX6UL_USB02_USBn_ADDR[i]);
 492         sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
 493                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 494                                             FSL_IMX6UL_USBn_IRQ[i]));
 495     }
 496
 497     /*
 498      * USDHCs
 499      */
 500     for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
 501         static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = {
 502             FSL_IMX6UL_USDHC1_ADDR,
 503             FSL_IMX6UL_USDHC2_ADDR,
 504         };
 505
 506         static const int FSL_IMX6UL_USDHCn_IRQ[FSL_IMX6UL_NUM_USDHCS] = {
 507             FSL_IMX6UL_USDHC1_IRQ,
 508             FSL_IMX6UL_USDHC2_IRQ,
 509         };
 510
 511         object_property_set_uint(OBJECT(&s->usdhc[i]), "vendor",
 512                                  SDHCI_VENDOR_IMX, &error_abort);
 513         sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort);
 514
 515         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
 516                         FSL_IMX6UL_USDHCn_ADDR[i]);
 517
 518         sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
 519                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 520                                             FSL_IMX6UL_USDHCn_IRQ[i]));
 521     }
 522
 523     /*
 524      * SNVS
 525      */
 526     sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
 527     sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
 528
 529     /*
 530      * Watchdogs
 531      */
 532     for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
 533         static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
 534             FSL_IMX6UL_WDOG1_ADDR,
 535             FSL_IMX6UL_WDOG2_ADDR,
 536             FSL_IMX6UL_WDOG3_ADDR,
 537         };
 538
 539         static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = {
 540             FSL_IMX6UL_WDOG1_IRQ,
 541             FSL_IMX6UL_WDOG2_IRQ,
 542             FSL_IMX6UL_WDOG3_IRQ,
 543         };
 544
 545         object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support",
 546                                  true, &error_abort);
 547         sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort);
 548
 549         sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
 550                         FSL_IMX6UL_WDOGn_ADDR[i]);
 551         sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
 552                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 553                                             FSL_IMX6UL_WDOGn_IRQ[i]));
 554     }
 555
 556     /*
 557      * SDMA
 558      */
 559     create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR,
 560                                 FSL_IMX6UL_SDMA_SIZE);
 561
 562     /*
 563      * SAIs (Audio SSI (Synchronous Serial Interface))
 564      */
 565     for (i = 0; i < FSL_IMX6UL_NUM_SAIS; i++) {
 566         static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] = {
 567             FSL_IMX6UL_SAI1_ADDR,
 568             FSL_IMX6UL_SAI2_ADDR,
 569             FSL_IMX6UL_SAI3_ADDR,
 570         };
 571
 572         snprintf(name, NAME_SIZE, "sai%d", i);
 573         create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i],
 574                                     FSL_IMX6UL_SAIn_SIZE);
 575     }
 576
 577     /*
 578      * PWMs
 579      */
 580     for (i = 0; i < FSL_IMX6UL_NUM_PWMS; i++) {
 581         static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] = {
 582             FSL_IMX6UL_PWM1_ADDR,
 583             FSL_IMX6UL_PWM2_ADDR,
 584             FSL_IMX6UL_PWM3_ADDR,
 585             FSL_IMX6UL_PWM4_ADDR,
 586         };
 587
 588         snprintf(name, NAME_SIZE, "pwm%d", i);
 589         create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i],
 590                                     FSL_IMX6UL_PWMn_SIZE);
 591     }
 592
 593     /*
 594      * Audio ASRC (asynchronous sample rate converter)
 595      */
 596     create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR,
 597                                 FSL_IMX6UL_ASRC_SIZE);
 598
 599     /*
 600      * CANs
 601      */
 602     for (i = 0; i < FSL_IMX6UL_NUM_CANS; i++) {
 603         static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] = {
 604             FSL_IMX6UL_CAN1_ADDR,
 605             FSL_IMX6UL_CAN2_ADDR,
 606         };
 607
 608         snprintf(name, NAME_SIZE, "can%d", i);
 609         create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i],
 610                                     FSL_IMX6UL_CANn_SIZE);
 611     }
 612
 613     /*
 614      * APHB_DMA
 615      */
 616     create_unimplemented_device("aphb_dma", FSL_IMX6UL_APBH_DMA_ADDR,
 617                                 FSL_IMX6UL_APBH_DMA_SIZE);
 618
 619     /*
 620      * ADCs
 621      */
 622     for (i = 0; i < FSL_IMX6UL_NUM_ADCS; i++) {
 623         static const hwaddr FSL_IMX6UL_ADCn_ADDR[FSL_IMX6UL_NUM_ADCS] = {
 624             FSL_IMX6UL_ADC1_ADDR,
 625             FSL_IMX6UL_ADC2_ADDR,
 626         };
 627
 628         snprintf(name, NAME_SIZE, "adc%d", i);
 629         create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i],
 630                                     FSL_IMX6UL_ADCn_SIZE);
 631     }
 632
 633     /*
 634      * LCD
 635      */
 636     create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
 637                                 FSL_IMX6UL_LCDIF_SIZE);
 638
 639     /*
 640      * ROM memory
 641      */
 642     memory_region_init_rom(&s->rom, OBJECT(dev), "imx6ul.rom",
 643                            FSL_IMX6UL_ROM_SIZE, &error_abort);
 644     memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_ROM_ADDR,
 645                                 &s->rom);
 646
 647     /*
 648      * CAAM memory
 649      */
 650     memory_region_init_rom(&s->caam, OBJECT(dev), "imx6ul.caam",
 651                            FSL_IMX6UL_CAAM_MEM_SIZE, &error_abort);
 652     memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_CAAM_MEM_ADDR,
 653                                 &s->caam);
 654
 655     /*
 656      * OCRAM memory
 657      */
 658     memory_region_init_ram(&s->ocram, NULL, "imx6ul.ocram",
 659                            FSL_IMX6UL_OCRAM_MEM_SIZE,
 660                            &error_abort);
 661     memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_OCRAM_MEM_ADDR,
 662                                 &s->ocram);
 663
 664     /*
 665      * internal OCRAM (128 KB) is aliased over 512 KB
 666      */
 667     memory_region_init_alias(&s->ocram_alias, OBJECT(dev),
 668                              "imx6ul.ocram_alias", &s->ocram, 0,
 669                              FSL_IMX6UL_OCRAM_ALIAS_SIZE);
 670     memory_region_add_subregion(get_system_memory(),
 671                                 FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias);
 672 }
 673
 674 static Property fsl_imx6ul_properties[] = {
 675     DEFINE_PROP_UINT32("fec1-phy-num", FslIMX6ULState, phy_num[0], 0),
 676     DEFINE_PROP_UINT32("fec2-phy-num", FslIMX6ULState, phy_num[1], 1),
 677     DEFINE_PROP_BOOL("fec1-phy-connected", FslIMX6ULState, phy_connected[0],
 678                      true),
 679     DEFINE_PROP_BOOL("fec2-phy-connected", FslIMX6ULState, phy_connected[1],
 680                      true),
 681     DEFINE_PROP_END_OF_LIST(),
 682 };
 683
 684 static void fsl_imx6ul_class_init(ObjectClass *oc, void *data)
 685 {
 686     DeviceClass *dc = DEVICE_CLASS(oc);
 687
 688     device_class_set_props(dc, fsl_imx6ul_properties);
 689     dc->realize = fsl_imx6ul_realize;
 690     dc->desc = "i.MX6UL SOC";
 691     /* Reason: Uses serial_hds and nd_table in realize() directly */
 692     dc->user_creatable = false;
 693 }
 694
 695 static const TypeInfo fsl_imx6ul_type_info = {
 696     .name = TYPE_FSL_IMX6UL,
 697     .parent = TYPE_DEVICE,
 698     .instance_size = sizeof(FslIMX6ULState),
 699     .instance_init = fsl_imx6ul_init,
 700     .class_init = fsl_imx6ul_class_init,
 701 };
 702
 703 static void fsl_imx6ul_register_types(void)
 704 {
 705     type_register_static(&fsl_imx6ul_type_info);
 706 }
 707 type_init(fsl_imx6ul_register_types)